Lines Matching +full:dynamic +full:- +full:power +full:- +full:coefficient
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3328-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3328-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
37 #address-cells = <2>;
38 #size-cells = <0>;
42 compatible = "arm,cortex-a53";
45 #cooling-cells = <2>;
46 cpu-idle-states = <&CPU_SLEEP>;
47 dynamic-power-coefficient = <120>;
48 enable-method = "psci";
49 operating-points-v2 = <&cpu0_opp_table>;
50 i-cache-size = <0x8000>;
51 i-cache-line-size = <64>;
52 i-cache-sets = <256>;
53 d-cache-size = <0x8000>;
54 d-cache-line-size = <64>;
55 d-cache-sets = <128>;
56 next-level-cache = <&l2_cache>;
61 compatible = "arm,cortex-a53";
64 #cooling-cells = <2>;
65 cpu-idle-states = <&CPU_SLEEP>;
66 dynamic-power-coefficient = <120>;
67 enable-method = "psci";
68 operating-points-v2 = <&cpu0_opp_table>;
69 i-cache-size = <0x8000>;
70 i-cache-line-size = <64>;
71 i-cache-sets = <256>;
72 d-cache-size = <0x8000>;
73 d-cache-line-size = <64>;
74 d-cache-sets = <128>;
75 next-level-cache = <&l2_cache>;
80 compatible = "arm,cortex-a53";
83 #cooling-cells = <2>;
84 cpu-idle-states = <&CPU_SLEEP>;
85 dynamic-power-coefficient = <120>;
86 enable-method = "psci";
87 operating-points-v2 = <&cpu0_opp_table>;
88 i-cache-size = <0x8000>;
89 i-cache-line-size = <64>;
90 i-cache-sets = <256>;
91 d-cache-size = <0x8000>;
92 d-cache-line-size = <64>;
93 d-cache-sets = <128>;
94 next-level-cache = <&l2_cache>;
99 compatible = "arm,cortex-a53";
102 #cooling-cells = <2>;
103 cpu-idle-states = <&CPU_SLEEP>;
104 dynamic-power-coefficient = <120>;
105 enable-method = "psci";
106 operating-points-v2 = <&cpu0_opp_table>;
107 i-cache-size = <0x8000>;
108 i-cache-line-size = <64>;
109 i-cache-sets = <256>;
110 d-cache-size = <0x8000>;
111 d-cache-line-size = <64>;
112 d-cache-sets = <128>;
113 next-level-cache = <&l2_cache>;
116 idle-states {
117 entry-method = "psci";
119 CPU_SLEEP: cpu-sleep {
120 compatible = "arm,idle-state";
121 local-timer-stop;
122 arm,psci-suspend-param = <0x0010000>;
123 entry-latency-us = <120>;
124 exit-latency-us = <250>;
125 min-residency-us = <900>;
129 l2_cache: l2-cache {
131 cache-level = <2>;
132 cache-unified;
133 cache-size = <0x40000>;
134 cache-line-size = <64>;
135 cache-sets = <256>;
139 cpu0_opp_table: opp-table-0 {
140 compatible = "operating-points-v2";
141 opp-shared;
143 opp-408000000 {
144 opp-hz = /bits/ 64 <408000000>;
145 opp-microvolt = <950000>;
146 clock-latency-ns = <40000>;
147 opp-suspend;
149 opp-600000000 {
150 opp-hz = /bits/ 64 <600000000>;
151 opp-microvolt = <950000>;
152 clock-latency-ns = <40000>;
154 opp-816000000 {
155 opp-hz = /bits/ 64 <816000000>;
156 opp-microvolt = <1000000>;
157 clock-latency-ns = <40000>;
159 opp-1008000000 {
160 opp-hz = /bits/ 64 <1008000000>;
161 opp-microvolt = <1100000>;
162 clock-latency-ns = <40000>;
164 opp-1200000000 {
165 opp-hz = /bits/ 64 <1200000000>;
166 opp-microvolt = <1225000>;
167 clock-latency-ns = <40000>;
169 opp-1296000000 {
170 opp-hz = /bits/ 64 <1296000000>;
171 opp-microvolt = <1300000>;
172 clock-latency-ns = <40000>;
176 analog_sound: analog-sound {
177 compatible = "simple-audio-card";
178 simple-audio-card,format = "i2s";
179 simple-audio-card,mclk-fs = <256>;
180 simple-audio-card,name = "Analog";
183 simple-audio-card,cpu {
184 sound-dai = <&i2s1>;
187 simple-audio-card,codec {
188 sound-dai = <&codec>;
192 arm-pmu {
193 compatible = "arm,cortex-a53-pmu";
198 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
201 display_subsystem: display-subsystem {
202 compatible = "rockchip,display-subsystem";
206 hdmi_sound: hdmi-sound {
207 compatible = "simple-audio-card";
208 simple-audio-card,format = "i2s";
209 simple-audio-card,mclk-fs = <128>;
210 simple-audio-card,name = "HDMI";
213 simple-audio-card,cpu {
214 sound-dai = <&i2s0>;
217 simple-audio-card,codec {
218 sound-dai = <&hdmi>;
223 compatible = "arm,psci-1.0", "arm,psci-0.2";
228 compatible = "arm,armv8-timer";
236 compatible = "fixed-clock";
237 #clock-cells = <0>;
238 clock-frequency = <24000000>;
239 clock-output-names = "xin24m";
243 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
247 clock-names = "i2s_clk", "i2s_hclk";
249 dma-names = "tx", "rx";
250 #sound-dai-cells = <0>;
255 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
259 clock-names = "i2s_clk", "i2s_hclk";
261 dma-names = "tx", "rx";
262 #sound-dai-cells = <0>;
267 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
271 clock-names = "i2s_clk", "i2s_hclk";
273 dma-names = "tx", "rx";
274 #sound-dai-cells = <0>;
279 compatible = "rockchip,rk3328-spdif";
283 clock-names = "mclk", "hclk";
285 dma-names = "tx";
286 pinctrl-names = "default";
287 pinctrl-0 = <&spdifm2_tx>;
288 #sound-dai-cells = <0>;
296 clock-names = "pdm_clk", "pdm_hclk";
298 dma-names = "rx";
299 pinctrl-names = "default", "sleep";
300 pinctrl-0 = <&pdmm0_clk
305 pinctrl-1 = <&pdmm0_clk_sleep
314 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
317 io_domains: io-domains {
318 compatible = "rockchip,rk3328-io-voltage-domain";
323 compatible = "rockchip,rk3328-grf-gpio";
324 gpio-controller;
325 #gpio-cells = <2>;
328 power: power-controller { label
329 compatible = "rockchip,rk3328-power-controller";
330 #power-domain-cells = <1>;
331 #address-cells = <1>;
332 #size-cells = <0>;
334 power-domain@RK3328_PD_HEVC {
337 #power-domain-cells = <0>;
339 power-domain@RK3328_PD_VIDEO {
345 #power-domain-cells = <0>;
347 power-domain@RK3328_PD_VPU {
350 #power-domain-cells = <0>;
354 reboot-mode {
355 compatible = "syscon-reboot-mode";
357 mode-normal = <BOOT_NORMAL>;
358 mode-recovery = <BOOT_RECOVERY>;
359 mode-bootloader = <BOOT_FASTBOOT>;
360 mode-loader = <BOOT_BL_DOWNLOAD>;
365 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
369 clock-names = "baudclk", "apb_pclk";
371 dma-names = "tx", "rx";
372 pinctrl-names = "default";
373 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
374 reg-io-width = <4>;
375 reg-shift = <2>;
380 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
384 clock-names = "baudclk", "apb_pclk";
386 dma-names = "tx", "rx";
387 pinctrl-names = "default";
388 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
389 reg-io-width = <4>;
390 reg-shift = <2>;
395 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
399 clock-names = "baudclk", "apb_pclk";
401 dma-names = "tx", "rx";
402 pinctrl-names = "default";
403 pinctrl-0 = <&uart2m1_xfer>;
404 reg-io-width = <4>;
405 reg-shift = <2>;
410 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
413 #address-cells = <1>;
414 #size-cells = <0>;
416 clock-names = "i2c", "pclk";
417 pinctrl-names = "default";
418 pinctrl-0 = <&i2c0_xfer>;
423 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
426 #address-cells = <1>;
427 #size-cells = <0>;
429 clock-names = "i2c", "pclk";
430 pinctrl-names = "default";
431 pinctrl-0 = <&i2c1_xfer>;
436 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
439 #address-cells = <1>;
440 #size-cells = <0>;
442 clock-names = "i2c", "pclk";
443 pinctrl-names = "default";
444 pinctrl-0 = <&i2c2_xfer>;
449 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
452 #address-cells = <1>;
453 #size-cells = <0>;
455 clock-names = "i2c", "pclk";
456 pinctrl-names = "default";
457 pinctrl-0 = <&i2c3_xfer>;
462 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
465 #address-cells = <1>;
466 #size-cells = <0>;
468 clock-names = "spiclk", "apb_pclk";
470 dma-names = "tx", "rx";
471 pinctrl-names = "default";
472 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
477 compatible = "rockchip,rk3328-wdt", "snps,dw-wdt";
484 compatible = "rockchip,rk3328-pwm";
487 clock-names = "pwm", "pclk";
488 pinctrl-names = "default";
489 pinctrl-0 = <&pwm0_pin>;
490 #pwm-cells = <3>;
495 compatible = "rockchip,rk3328-pwm";
498 clock-names = "pwm", "pclk";
499 pinctrl-names = "default";
500 pinctrl-0 = <&pwm1_pin>;
501 #pwm-cells = <3>;
506 compatible = "rockchip,rk3328-pwm";
509 clock-names = "pwm", "pclk";
510 pinctrl-names = "default";
511 pinctrl-0 = <&pwm2_pin>;
512 #pwm-cells = <3>;
517 compatible = "rockchip,rk3328-pwm";
520 clock-names = "pwm", "pclk";
521 pinctrl-names = "default";
522 pinctrl-0 = <&pwmir_pin>;
523 #pwm-cells = <3>;
527 dmac: dma-controller@ff1f0000 {
532 arm,pl330-periph-burst;
534 clock-names = "apb_pclk";
535 #dma-cells = <1>;
538 thermal-zones {
539 soc_thermal: soc-thermal {
540 polling-delay-passive = <20>;
541 polling-delay = <1000>;
542 sustainable-power = <1000>;
544 thermal-sensors = <&tsadc 0>;
547 threshold: trip-point0 {
552 target: trip-point1 {
557 soc_crit: soc-crit {
564 cooling-maps {
567 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
579 compatible = "rockchip,rk3328-tsadc";
582 assigned-clocks = <&cru SCLK_TSADC>;
583 assigned-clock-rates = <50000>;
585 clock-names = "tsadc", "apb_pclk";
586 pinctrl-names = "init", "default", "sleep";
587 pinctrl-0 = <&otp_pin>;
588 pinctrl-1 = <&otp_out>;
589 pinctrl-2 = <&otp_pin>;
591 reset-names = "tsadc-apb";
593 rockchip,hw-tshut-temp = <100000>;
594 #thermal-sensor-cells = <1>;
599 compatible = "rockchip,rk3328-efuse";
601 #address-cells = <1>;
602 #size-cells = <1>;
604 clock-names = "pclk_efuse";
605 rockchip,efuse-size = <0x20>;
611 cpu_leakage: cpu-leakage@17 {
614 logic_leakage: logic-leakage@19 {
617 efuse_cpu_version: cpu-version@1a {
624 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
627 #io-channel-cells = <1>;
629 clock-names = "saradc", "apb_pclk";
631 reset-names = "saradc-apb";
636 compatible = "rockchip,rk3328-mali", "arm,mali-450";
645 interrupt-names = "gp",
653 clock-names = "bus", "core";
662 clock-names = "aclk", "iface";
663 #iommu-cells = <0>;
672 clock-names = "aclk", "iface";
673 #iommu-cells = <0>;
677 vpu: video-codec@ff350000 {
678 compatible = "rockchip,rk3328-vpu";
681 interrupt-names = "vdpu";
683 clock-names = "aclk", "hclk";
685 power-domains = <&power RK3328_PD_VPU>;
693 clock-names = "aclk", "iface";
694 #iommu-cells = <0>;
695 power-domains = <&power RK3328_PD_VPU>;
698 vdec: video-codec@ff360000 {
699 compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec";
704 clock-names = "axi", "ahb", "cabac", "core";
705 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>,
707 assigned-clock-rates = <400000000>, <400000000>, <300000000>;
709 power-domains = <&power RK3328_PD_VIDEO>;
717 clock-names = "aclk", "iface";
718 #iommu-cells = <0>;
719 power-domains = <&power RK3328_PD_VIDEO>;
723 compatible = "rockchip,rk3328-vop";
727 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
729 reset-names = "axi", "ahb", "dclk";
735 remote-endpoint = <&hdmi_in_vop>;
745 clock-names = "aclk", "iface";
746 #iommu-cells = <0>;
751 compatible = "rockchip,rk3328-dw-hdmi";
753 reg-io-width = <4>;
758 clock-names = "iahb",
762 phy-names = "hdmi";
763 pinctrl-names = "default";
764 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
766 #sound-dai-cells = <0>;
770 #address-cells = <1>;
771 #size-cells = <0>;
777 remote-endpoint = <&vop_out_hdmi>;
788 compatible = "rockchip,rk3328-codec";
791 clock-names = "pclk", "mclk";
793 #sound-dai-cells = <0>;
798 compatible = "rockchip,rk3328-hdmi-phy";
802 clock-names = "sysclk", "refoclk", "refpclk";
803 clock-output-names = "hdmi_phy";
804 #clock-cells = <0>;
805 nvmem-cells = <&efuse_cpu_version>;
806 nvmem-cell-names = "cpu-version";
807 #phy-cells = <0>;
811 cru: clock-controller@ff440000 {
812 compatible = "rockchip,rk3328-cru";
815 clock-names = "xin24m";
817 #clock-cells = <1>;
818 #reset-cells = <1>;
819 assigned-clocks =
842 assigned-clock-parents =
846 assigned-clock-rates =
866 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
867 "simple-mfd";
869 #address-cells = <1>;
870 #size-cells = <1>;
873 compatible = "rockchip,rk3328-usb2phy";
876 clock-names = "phyclk";
877 clock-output-names = "usb480m_phy";
878 #clock-cells = <0>;
879 assigned-clocks = <&cru USB480M>;
880 assigned-clock-parents = <&u2phy>;
883 u2phy_otg: otg-port {
884 #phy-cells = <0>;
888 interrupt-names = "otg-bvalid", "otg-id",
893 u2phy_host: host-port {
894 #phy-cells = <0>;
896 interrupt-names = "linestate";
903 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
908 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
909 fifo-depth = <0x100>;
910 max-frequency = <150000000>;
912 reset-names = "reset";
917 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
922 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
923 fifo-depth = <0x100>;
924 max-frequency = <150000000>;
926 reset-names = "reset";
931 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
936 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
937 fifo-depth = <0x100>;
938 max-frequency = <150000000>;
940 reset-names = "reset";
945 compatible = "rockchip,rk3328-gmac";
948 interrupt-names = "macirq";
953 clock-names = "stmmaceth", "mac_clk_rx",
958 reset-names = "stmmaceth";
960 tx-fifo-depth = <2048>;
961 rx-fifo-depth = <4096>;
967 compatible = "rockchip,rk3328-gmac";
971 interrupt-names = "macirq";
976 clock-names = "stmmaceth", "mac_clk_rx",
981 reset-names = "stmmaceth";
982 phy-mode = "rmii";
983 phy-handle = <&phy>;
984 tx-fifo-depth = <2048>;
985 rx-fifo-depth = <4096>;
991 compatible = "snps,dwmac-mdio";
992 #address-cells = <1>;
993 #size-cells = <0>;
995 phy: ethernet-phy@0 {
996 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
1000 pinctrl-names = "default";
1001 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
1002 phy-is-integrated;
1008 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
1013 clock-names = "otg";
1015 g-np-tx-fifo-size = <16>;
1016 g-rx-fifo-size = <280>;
1017 g-tx-fifo-size = <256 128 128 64 32 16>;
1019 phy-names = "usb2-phy";
1024 compatible = "generic-ehci";
1029 phy-names = "usb";
1034 compatible = "generic-ohci";
1039 phy-names = "usb";
1044 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
1049 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1050 fifo-depth = <0x100>;
1051 max-frequency = <150000000>;
1053 reset-names = "reset";
1058 compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
1063 clock-names = "ref_clk", "suspend_clk",
1067 snps,dis-del-phy-power-chg-quirk;
1069 snps,dis-tx-ipgap-linecheck-quirk;
1070 snps,dis-u2-freeclk-exists-quirk;
1076 gic: interrupt-controller@ff811000 {
1077 compatible = "arm,gic-400";
1078 #interrupt-cells = <3>;
1079 #address-cells = <0>;
1080 interrupt-controller;
1090 compatible = "rockchip,rk3328-crypto";
1095 clock-names = "hclk_master", "hclk_slave", "sclk";
1097 reset-names = "crypto-rst";
1101 compatible = "rockchip,rk3328-pinctrl";
1103 #address-cells = <2>;
1104 #size-cells = <2>;
1108 compatible = "rockchip,gpio-bank";
1113 gpio-controller;
1114 #gpio-cells = <2>;
1116 interrupt-controller;
1117 #interrupt-cells = <2>;
1121 compatible = "rockchip,gpio-bank";
1126 gpio-controller;
1127 #gpio-cells = <2>;
1129 interrupt-controller;
1130 #interrupt-cells = <2>;
1134 compatible = "rockchip,gpio-bank";
1139 gpio-controller;
1140 #gpio-cells = <2>;
1142 interrupt-controller;
1143 #interrupt-cells = <2>;
1147 compatible = "rockchip,gpio-bank";
1152 gpio-controller;
1153 #gpio-cells = <2>;
1155 interrupt-controller;
1156 #interrupt-cells = <2>;
1159 pcfg_pull_up: pcfg-pull-up {
1160 bias-pull-up;
1163 pcfg_pull_down: pcfg-pull-down {
1164 bias-pull-down;
1167 pcfg_pull_none: pcfg-pull-none {
1168 bias-disable;
1171 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1172 bias-disable;
1173 drive-strength = <2>;
1176 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1177 bias-pull-up;
1178 drive-strength = <2>;
1181 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1182 bias-pull-up;
1183 drive-strength = <4>;
1186 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1187 bias-disable;
1188 drive-strength = <4>;
1191 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1192 bias-pull-down;
1193 drive-strength = <4>;
1196 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1197 bias-disable;
1198 drive-strength = <8>;
1201 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1202 bias-pull-up;
1203 drive-strength = <8>;
1206 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1207 bias-disable;
1208 drive-strength = <12>;
1211 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1212 bias-pull-up;
1213 drive-strength = <12>;
1216 pcfg_output_high: pcfg-output-high {
1217 output-high;
1220 pcfg_output_low: pcfg-output-low {
1221 output-low;
1224 pcfg_input_high: pcfg-input-high {
1225 bias-pull-up;
1226 input-enable;
1229 pcfg_input: pcfg-input {
1230 input-enable;
1234 i2c0_xfer: i2c0-xfer {
1241 i2c1_xfer: i2c1-xfer {
1248 i2c2_xfer: i2c2-xfer {
1255 i2c3_xfer: i2c3-xfer {
1259 i2c3_pins: i2c3-pins {
1267 hdmii2c_xfer: hdmii2c-xfer {
1273 pdm-0 {
1274 pdmm0_clk: pdmm0-clk {
1278 pdmm0_fsync: pdmm0-fsync {
1282 pdmm0_sdi0: pdmm0-sdi0 {
1286 pdmm0_sdi1: pdmm0-sdi1 {
1290 pdmm0_sdi2: pdmm0-sdi2 {
1294 pdmm0_sdi3: pdmm0-sdi3 {
1298 pdmm0_clk_sleep: pdmm0-clk-sleep {
1303 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1308 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1313 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
1318 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1323 pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1330 otp_pin: otp-pin {
1334 otp_out: otp-out {
1340 uart0_xfer: uart0-xfer {
1345 uart0_cts: uart0-cts {
1349 uart0_rts: uart0-rts {
1353 uart0_rts_pin: uart0-rts-pin {
1359 uart1_xfer: uart1-xfer {
1364 uart1_cts: uart1-cts {
1368 uart1_rts: uart1-rts {
1372 uart1_rts_pin: uart1-rts-pin {
1377 uart2-0 {
1378 uart2m0_xfer: uart2m0-xfer {
1384 uart2-1 {
1385 uart2m1_xfer: uart2m1-xfer {
1391 spi0-0 {
1392 spi0m0_clk: spi0m0-clk {
1396 spi0m0_cs0: spi0m0-cs0 {
1400 spi0m0_tx: spi0m0-tx {
1404 spi0m0_rx: spi0m0-rx {
1408 spi0m0_cs1: spi0m0-cs1 {
1413 spi0-1 {
1414 spi0m1_clk: spi0m1-clk {
1418 spi0m1_cs0: spi0m1-cs0 {
1422 spi0m1_tx: spi0m1-tx {
1426 spi0m1_rx: spi0m1-rx {
1430 spi0m1_cs1: spi0m1-cs1 {
1435 spi0-2 {
1436 spi0m2_clk: spi0m2-clk {
1440 spi0m2_cs0: spi0m2-cs0 {
1444 spi0m2_tx: spi0m2-tx {
1448 spi0m2_rx: spi0m2-rx {
1454 i2s1_mclk: i2s1-mclk {
1458 i2s1_sclk: i2s1-sclk {
1462 i2s1_lrckrx: i2s1-lrckrx {
1466 i2s1_lrcktx: i2s1-lrcktx {
1470 i2s1_sdi: i2s1-sdi {
1474 i2s1_sdo: i2s1-sdo {
1478 i2s1_sdio1: i2s1-sdio1 {
1482 i2s1_sdio2: i2s1-sdio2 {
1486 i2s1_sdio3: i2s1-sdio3 {
1490 i2s1_sleep: i2s1-sleep {
1504 i2s2-0 {
1505 i2s2m0_mclk: i2s2m0-mclk {
1509 i2s2m0_sclk: i2s2m0-sclk {
1513 i2s2m0_lrckrx: i2s2m0-lrckrx {
1517 i2s2m0_lrcktx: i2s2m0-lrcktx {
1521 i2s2m0_sdi: i2s2m0-sdi {
1525 i2s2m0_sdo: i2s2m0-sdo {
1529 i2s2m0_sleep: i2s2m0-sleep {
1540 i2s2-1 {
1541 i2s2m1_mclk: i2s2m1-mclk {
1545 i2s2m1_sclk: i2s2m1-sclk {
1549 i2s2m1_lrckrx: i2sm1-lrckrx {
1553 i2s2m1_lrcktx: i2s2m1-lrcktx {
1557 i2s2m1_sdi: i2s2m1-sdi {
1561 i2s2m1_sdo: i2s2m1-sdo {
1565 i2s2m1_sleep: i2s2m1-sleep {
1575 spdif-0 {
1576 spdifm0_tx: spdifm0-tx {
1581 spdif-1 {
1582 spdifm1_tx: spdifm1-tx {
1587 spdif-2 {
1588 spdifm2_tx: spdifm2-tx {
1593 sdmmc0-0 {
1594 sdmmc0m0_pwren: sdmmc0m0-pwren {
1598 sdmmc0m0_pin: sdmmc0m0-pin {
1603 sdmmc0-1 {
1604 sdmmc0m1_pwren: sdmmc0m1-pwren {
1608 sdmmc0m1_pin: sdmmc0m1-pin {
1614 sdmmc0_clk: sdmmc0-clk {
1618 sdmmc0_cmd: sdmmc0-cmd {
1622 sdmmc0_dectn: sdmmc0-dectn {
1626 sdmmc0_wrprt: sdmmc0-wrprt {
1630 sdmmc0_bus1: sdmmc0-bus1 {
1634 sdmmc0_bus4: sdmmc0-bus4 {
1641 sdmmc0_pins: sdmmc0-pins {
1655 sdmmc0ext_clk: sdmmc0ext-clk {
1659 sdmmc0ext_cmd: sdmmc0ext-cmd {
1663 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1667 sdmmc0ext_dectn: sdmmc0ext-dectn {
1671 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1675 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1683 sdmmc0ext_pins: sdmmc0ext-pins {
1697 sdmmc1_clk: sdmmc1-clk {
1701 sdmmc1_cmd: sdmmc1-cmd {
1705 sdmmc1_pwren: sdmmc1-pwren {
1709 sdmmc1_wrprt: sdmmc1-wrprt {
1713 sdmmc1_dectn: sdmmc1-dectn {
1717 sdmmc1_bus1: sdmmc1-bus1 {
1721 sdmmc1_bus4: sdmmc1-bus4 {
1728 sdmmc1_pins: sdmmc1-pins {
1743 emmc_clk: emmc-clk {
1747 emmc_cmd: emmc-cmd {
1751 emmc_pwren: emmc-pwren {
1755 emmc_rstnout: emmc-rstnout {
1759 emmc_bus1: emmc-bus1 {
1763 emmc_bus4: emmc-bus4 {
1771 emmc_bus8: emmc-bus8 {
1785 pwm0_pin: pwm0-pin {
1791 pwm1_pin: pwm1-pin {
1797 pwm2_pin: pwm2-pin {
1803 pwmir_pin: pwmir-pin {
1808 gmac-1 {
1809 rgmiim1_pins: rgmiim1-pins {
1858 rmiim1_pins: rmiim1-pins {
1897 fephyled_speed10: fephyled-speed10 {
1901 fephyled_duplex: fephyled-duplex {
1905 fephyled_rxm1: fephyled-rxm1 {
1909 fephyled_txm1: fephyled-txm1 {
1913 fephyled_linkm1: fephyled-linkm1 {
1919 tsadc_int: tsadc-int {
1922 tsadc_pin: tsadc-pin {
1928 hdmi_cec: hdmi-cec {
1932 hdmi_hpd: hdmi-hpd {
1937 cif-0 {
1938 dvp_d2d9_m0:dvp-d2d9-m0 {
1967 cif-1 {
1968 dvp_d2d9_m1:dvp-d2d9-m1 {