Lines Matching +full:0 +full:xff500000
38 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0x0 0x0>;
50 i-cache-size = <0x8000>;
53 d-cache-size = <0x8000>;
62 reg = <0x0 0x1>;
69 i-cache-size = <0x8000>;
72 d-cache-size = <0x8000>;
81 reg = <0x0 0x2>;
88 i-cache-size = <0x8000>;
91 d-cache-size = <0x8000>;
100 reg = <0x0 0x3>;
107 i-cache-size = <0x8000>;
110 d-cache-size = <0x8000>;
122 arm,psci-suspend-param = <0x0010000>;
133 cache-size = <0x40000>;
139 cpu0_opp_table: opp-table-0 {
237 #clock-cells = <0>;
244 reg = <0x0 0xff000000 0x0 0x1000>;
250 #sound-dai-cells = <0>;
256 reg = <0x0 0xff010000 0x0 0x1000>;
262 #sound-dai-cells = <0>;
268 reg = <0x0 0xff020000 0x0 0x1000>;
272 dmas = <&dmac 0>, <&dmac 1>;
274 #sound-dai-cells = <0>;
280 reg = <0x0 0xff030000 0x0 0x1000>;
287 pinctrl-0 = <&spdifm2_tx>;
288 #sound-dai-cells = <0>;
294 reg = <0x0 0xff040000 0x0 0x1000>;
300 pinctrl-0 = <&pdmm0_clk
315 reg = <0x0 0xff100000 0x0 0x1000>;
332 #size-cells = <0>;
336 #power-domain-cells = <0>;
344 #power-domain-cells = <0>;
349 #power-domain-cells = <0>;
355 offset = <0x5c8>;
365 reg = <0x0 0xff110000 0x0 0x100>;
372 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
380 reg = <0x0 0xff120000 0x0 0x100>;
387 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
395 reg = <0x0 0xff130000 0x0 0x100>;
402 pinctrl-0 = <&uart2m1_xfer>;
410 reg = <0x0 0xff150000 0x0 0x1000>;
413 #size-cells = <0>;
417 pinctrl-0 = <&i2c0_xfer>;
423 reg = <0x0 0xff160000 0x0 0x1000>;
426 #size-cells = <0>;
430 pinctrl-0 = <&i2c1_xfer>;
436 reg = <0x0 0xff170000 0x0 0x1000>;
439 #size-cells = <0>;
443 pinctrl-0 = <&i2c2_xfer>;
449 reg = <0x0 0xff180000 0x0 0x1000>;
452 #size-cells = <0>;
456 pinctrl-0 = <&i2c3_xfer>;
462 reg = <0x0 0xff190000 0x0 0x1000>;
465 #size-cells = <0>;
471 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
477 reg = <0x0 0xff1a0000 0x0 0x100>;
484 reg = <0x0 0xff1b0000 0x0 0x10>;
488 pinctrl-0 = <&pwm0_pin>;
495 reg = <0x0 0xff1b0010 0x0 0x10>;
499 pinctrl-0 = <&pwm1_pin>;
506 reg = <0x0 0xff1b0020 0x0 0x10>;
510 pinctrl-0 = <&pwm2_pin>;
517 reg = <0x0 0xff1b0030 0x0 0x10>;
521 pinctrl-0 = <&pwmir_pin>;
528 reg = <0x0 0xff1f0000 0x0 0x4000>;
529 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
543 thermal-sensors = <&tsadc 0>;
579 reg = <0x0 0xff250000 0x0 0x100>;
586 pinctrl-0 = <&otp_pin>;
599 reg = <0x0 0xff260000 0x0 0x50>;
604 rockchip,efuse-size = <0x20>;
608 reg = <0x07 0x10>;
611 reg = <0x17 0x1>;
614 reg = <0x19 0x1>;
617 reg = <0x1a 0x1>;
624 reg = <0x0 0xff280000 0x0 0x100>;
636 reg = <0x0 0xff300000 0x0 0x30000>;
658 reg = <0x0 0xff330200 0 0x100>;
662 #iommu-cells = <0>;
668 reg = <0x0 0xff340800 0x0 0x40>;
672 #iommu-cells = <0>;
678 reg = <0x0 0xff350000 0x0 0x800>;
689 reg = <0x0 0xff350800 0x0 0x40>;
693 #iommu-cells = <0>;
699 reg = <0x0 0xff360000 0x0 0x480>;
713 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
717 #iommu-cells = <0>;
723 reg = <0x0 0xff370000 0x0 0x3efc>;
734 #size-cells = <0>;
736 vop_out_hdmi: endpoint@0 {
737 reg = <0>;
745 reg = <0x0 0xff373f00 0x0 0x100>;
749 #iommu-cells = <0>;
755 reg = <0x0 0xff3c0000 0x0 0x20000>;
767 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
769 #sound-dai-cells = <0>;
774 #size-cells = <0>;
776 hdmi_in: port@0 {
777 reg = <0>;
792 reg = <0x0 0xff410000 0x0 0x1000>;
796 #sound-dai-cells = <0>;
802 reg = <0x0 0xff430000 0x0 0x10000>;
807 #clock-cells = <0>;
810 #phy-cells = <0>;
816 reg = <0x0 0xff440000 0x0 0x1000>;
848 <0>, <61440000>,
849 <0>, <24000000>,
869 reg = <0x0 0xff450000 0x0 0x10000>;
875 reg = <0x100 0x10>;
879 #clock-cells = <0>;
885 #phy-cells = <0>;
895 #phy-cells = <0>;
905 reg = <0x0 0xff500000 0x0 0x4000>;
910 fifo-depth = <0x100>;
919 reg = <0x0 0xff510000 0x0 0x4000>;
924 fifo-depth = <0x100>;
933 reg = <0x0 0xff520000 0x0 0x4000>;
938 fifo-depth = <0x100>;
947 reg = <0x0 0xff540000 0x0 0x10000>;
963 snps,txpbl = <0x4>;
969 reg = <0x0 0xff550000 0x0 0x10000>;
987 snps,txpbl = <0x4>;
994 #size-cells = <0>;
996 phy: ethernet-phy@0 {
998 reg = <0>;
1002 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
1011 reg = <0x0 0xff580000 0x0 0x40000>;
1026 reg = <0x0 0xff5c0000 0x0 0x10000>;
1036 reg = <0x0 0xff5d0000 0x0 0x10000>;
1046 reg = <0x0 0xff5f0000 0x0 0x4000>;
1051 fifo-depth = <0x100>;
1060 reg = <0x0 0xff600000 0x0 0x100000>;
1080 #address-cells = <0>;
1082 reg = <0x0 0xff811000 0 0x1000>,
1083 <0x0 0xff812000 0 0x2000>,
1084 <0x0 0xff814000 0 0x2000>,
1085 <0x0 0xff816000 0 0x2000>;
1092 reg = <0x0 0xff060000 0x0 0x4000>;
1110 reg = <0x0 0xff210000 0x0 0x100>;
1123 reg = <0x0 0xff220000 0x0 0x100>;
1136 reg = <0x0 0xff230000 0x0 0x100>;
1149 reg = <0x0 0xff240000 0x0 0x100>;
1257 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
1258 <0 RK_PA6 2 &pcfg_pull_none>;
1262 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1263 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1269 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
1270 <0 RK_PA6 1 &pcfg_pull_none>;
1274 pdm-0 {
1378 uart2-0 {
1392 spi0-0 {
1505 i2s2-0 {
1576 spdif-0 {
1578 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1590 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
1594 sdmmc0-0 {
1606 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
1610 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1761 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1766 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1774 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1844 <0 RK_PB0 1 &pcfg_pull_none_8ma>,
1846 <0 RK_PB4 1 &pcfg_pull_none_8ma>,
1848 <0 RK_PD0 1 &pcfg_pull_none_4ma>,
1850 <0 RK_PC0 1 &pcfg_pull_none_8ma>,
1852 <0 RK_PC1 1 &pcfg_pull_none_8ma>,
1854 <0 RK_PC7 1 &pcfg_pull_none_8ma>,
1856 <0 RK_PC6 1 &pcfg_pull_none_8ma>;
1883 <0 RK_PB3 1 &pcfg_pull_none>,
1885 <0 RK_PB4 1 &pcfg_pull_none>,
1887 <0 RK_PD0 1 &pcfg_pull_none>,
1889 <0 RK_PC3 1 &pcfg_pull_none>,
1891 <0 RK_PC0 1 &pcfg_pull_none>,
1893 <0 RK_PC1 1 &pcfg_pull_none>;
1899 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1903 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1930 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1934 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1938 cif-0 {