Lines Matching +full:0 +full:xff280000
38 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0x0 0x0>;
50 i-cache-size = <0x8000>;
53 d-cache-size = <0x8000>;
62 reg = <0x0 0x1>;
69 i-cache-size = <0x8000>;
72 d-cache-size = <0x8000>;
81 reg = <0x0 0x2>;
88 i-cache-size = <0x8000>;
91 d-cache-size = <0x8000>;
100 reg = <0x0 0x3>;
107 i-cache-size = <0x8000>;
110 d-cache-size = <0x8000>;
122 arm,psci-suspend-param = <0x0010000>;
133 cache-size = <0x40000>;
139 cpu0_opp_table: opp-table-0 {
237 #clock-cells = <0>;
244 reg = <0x0 0xff000000 0x0 0x1000>;
250 #sound-dai-cells = <0>;
256 reg = <0x0 0xff010000 0x0 0x1000>;
262 #sound-dai-cells = <0>;
268 reg = <0x0 0xff020000 0x0 0x1000>;
272 dmas = <&dmac 0>, <&dmac 1>;
274 #sound-dai-cells = <0>;
280 reg = <0x0 0xff030000 0x0 0x1000>;
287 pinctrl-0 = <&spdifm2_tx>;
288 #sound-dai-cells = <0>;
294 reg = <0x0 0xff040000 0x0 0x1000>;
300 pinctrl-0 = <&pdmm0_clk
315 reg = <0x0 0xff100000 0x0 0x1000>;
332 #size-cells = <0>;
337 #power-domain-cells = <0>;
345 #power-domain-cells = <0>;
350 #power-domain-cells = <0>;
356 offset = <0x5c8>;
366 reg = <0x0 0xff110000 0x0 0x100>;
373 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
381 reg = <0x0 0xff120000 0x0 0x100>;
388 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
396 reg = <0x0 0xff130000 0x0 0x100>;
403 pinctrl-0 = <&uart2m1_xfer>;
411 reg = <0x0 0xff150000 0x0 0x1000>;
414 #size-cells = <0>;
418 pinctrl-0 = <&i2c0_xfer>;
424 reg = <0x0 0xff160000 0x0 0x1000>;
427 #size-cells = <0>;
431 pinctrl-0 = <&i2c1_xfer>;
437 reg = <0x0 0xff170000 0x0 0x1000>;
440 #size-cells = <0>;
444 pinctrl-0 = <&i2c2_xfer>;
450 reg = <0x0 0xff180000 0x0 0x1000>;
453 #size-cells = <0>;
457 pinctrl-0 = <&i2c3_xfer>;
463 reg = <0x0 0xff190000 0x0 0x1000>;
466 #size-cells = <0>;
472 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
478 reg = <0x0 0xff1a0000 0x0 0x100>;
485 reg = <0x0 0xff1b0000 0x0 0x10>;
489 pinctrl-0 = <&pwm0_pin>;
496 reg = <0x0 0xff1b0010 0x0 0x10>;
500 pinctrl-0 = <&pwm1_pin>;
507 reg = <0x0 0xff1b0020 0x0 0x10>;
511 pinctrl-0 = <&pwm2_pin>;
518 reg = <0x0 0xff1b0030 0x0 0x10>;
522 pinctrl-0 = <&pwmir_pin>;
529 reg = <0x0 0xff1f0000 0x0 0x4000>;
530 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
544 thermal-sensors = <&tsadc 0>;
580 reg = <0x0 0xff250000 0x0 0x100>;
587 pinctrl-0 = <&otp_pin>;
600 reg = <0x0 0xff260000 0x0 0x50>;
605 rockchip,efuse-size = <0x20>;
609 reg = <0x07 0x10>;
612 reg = <0x17 0x1>;
615 reg = <0x19 0x1>;
618 reg = <0x1a 0x1>;
625 reg = <0x0 0xff280000 0x0 0x100>;
637 reg = <0x0 0xff300000 0x0 0x30000>;
659 reg = <0x0 0xff330200 0 0x100>;
663 #iommu-cells = <0>;
669 reg = <0x0 0xff340800 0x0 0x40>;
673 #iommu-cells = <0>;
679 reg = <0x0 0xff350000 0x0 0x800>;
690 reg = <0x0 0xff350800 0x0 0x40>;
694 #iommu-cells = <0>;
700 reg = <0x0 0xff360000 0x0 0x480>;
714 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
718 #iommu-cells = <0>;
724 reg = <0x0 0xff370000 0x0 0x3efc>;
735 #size-cells = <0>;
737 vop_out_hdmi: endpoint@0 {
738 reg = <0>;
746 reg = <0x0 0xff373f00 0x0 0x100>;
750 #iommu-cells = <0>;
756 reg = <0x0 0xff3c0000 0x0 0x20000>;
768 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
770 #sound-dai-cells = <0>;
775 #size-cells = <0>;
777 hdmi_in: port@0 {
778 reg = <0>;
793 reg = <0x0 0xff410000 0x0 0x1000>;
797 #sound-dai-cells = <0>;
803 reg = <0x0 0xff430000 0x0 0x10000>;
808 #clock-cells = <0>;
811 #phy-cells = <0>;
817 reg = <0x0 0xff440000 0x0 0x1000>;
851 <0>, <61440000>,
852 <0>, <24000000>,
872 reg = <0x0 0xff450000 0x0 0x10000>;
878 reg = <0x100 0x10>;
882 #clock-cells = <0>;
888 #phy-cells = <0>;
898 #phy-cells = <0>;
908 reg = <0x0 0xff500000 0x0 0x4000>;
913 fifo-depth = <0x100>;
922 reg = <0x0 0xff510000 0x0 0x4000>;
927 fifo-depth = <0x100>;
936 reg = <0x0 0xff520000 0x0 0x4000>;
941 fifo-depth = <0x100>;
950 reg = <0x0 0xff540000 0x0 0x10000>;
966 snps,txpbl = <0x4>;
972 reg = <0x0 0xff550000 0x0 0x10000>;
990 snps,txpbl = <0x4>;
997 #size-cells = <0>;
999 phy: ethernet-phy@0 {
1001 reg = <0>;
1005 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
1014 reg = <0x0 0xff580000 0x0 0x40000>;
1029 reg = <0x0 0xff5c0000 0x0 0x10000>;
1039 reg = <0x0 0xff5d0000 0x0 0x10000>;
1049 reg = <0x0 0xff5f0000 0x0 0x4000>;
1054 fifo-depth = <0x100>;
1063 reg = <0x0 0xff600000 0x0 0x100000>;
1083 #address-cells = <0>;
1085 reg = <0x0 0xff811000 0 0x1000>,
1086 <0x0 0xff812000 0 0x2000>,
1087 <0x0 0xff814000 0 0x2000>,
1088 <0x0 0xff816000 0 0x2000>;
1095 reg = <0x0 0xff060000 0x0 0x4000>;
1113 reg = <0x0 0xff210000 0x0 0x100>;
1126 reg = <0x0 0xff220000 0x0 0x100>;
1139 reg = <0x0 0xff230000 0x0 0x100>;
1152 reg = <0x0 0xff240000 0x0 0x100>;
1260 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
1261 <0 RK_PA6 2 &pcfg_pull_none>;
1265 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1266 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1272 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
1273 <0 RK_PA6 1 &pcfg_pull_none>;
1277 pdm-0 {
1381 uart2-0 {
1395 spi0-0 {
1508 i2s2-0 {
1579 spdif-0 {
1581 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1593 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
1597 sdmmc0-0 {
1609 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
1613 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1764 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1769 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1777 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1847 <0 RK_PB0 1 &pcfg_pull_none_8ma>,
1849 <0 RK_PB4 1 &pcfg_pull_none_8ma>,
1851 <0 RK_PD0 1 &pcfg_pull_none_4ma>,
1853 <0 RK_PC0 1 &pcfg_pull_none_8ma>,
1855 <0 RK_PC1 1 &pcfg_pull_none_8ma>,
1857 <0 RK_PC7 1 &pcfg_pull_none_8ma>,
1859 <0 RK_PC6 1 &pcfg_pull_none_8ma>;
1886 <0 RK_PB3 1 &pcfg_pull_none>,
1888 <0 RK_PB4 1 &pcfg_pull_none>,
1890 <0 RK_PD0 1 &pcfg_pull_none>,
1892 <0 RK_PC3 1 &pcfg_pull_none>,
1894 <0 RK_PC0 1 &pcfg_pull_none>,
1896 <0 RK_PC1 1 &pcfg_pull_none>;
1902 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1906 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1933 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1937 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1941 cif-0 {