Lines Matching +full:rk3328 +full:- +full:grf +full:- +full:gpio
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/clock/rk3308-cru.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
43 #address-cells = <2>;
44 #size-cells = <0>;
48 compatible = "arm,cortex-a35";
50 enable-method = "psci";
52 #cooling-cells = <2>;
53 dynamic-power-coefficient = <90>;
54 operating-points-v2 = <&cpu0_opp_table>;
55 cpu-idle-states = <&CPU_SLEEP>;
56 next-level-cache = <&l2>;
61 compatible = "arm,cortex-a35";
63 enable-method = "psci";
64 operating-points-v2 = <&cpu0_opp_table>;
65 cpu-idle-states = <&CPU_SLEEP>;
66 next-level-cache = <&l2>;
71 compatible = "arm,cortex-a35";
73 enable-method = "psci";
74 operating-points-v2 = <&cpu0_opp_table>;
75 cpu-idle-states = <&CPU_SLEEP>;
76 next-level-cache = <&l2>;
81 compatible = "arm,cortex-a35";
83 enable-method = "psci";
84 operating-points-v2 = <&cpu0_opp_table>;
85 cpu-idle-states = <&CPU_SLEEP>;
86 next-level-cache = <&l2>;
89 idle-states {
90 entry-method = "psci";
92 CPU_SLEEP: cpu-sleep {
93 compatible = "arm,idle-state";
94 local-timer-stop;
95 arm,psci-suspend-param = <0x0010000>;
96 entry-latency-us = <120>;
97 exit-latency-us = <250>;
98 min-residency-us = <900>;
102 l2: l2-cache {
104 cache-level = <2>;
105 cache-unified;
109 cpu0_opp_table: opp-table-0 {
110 compatible = "operating-points-v2";
111 opp-shared;
113 opp-408000000 {
114 opp-hz = /bits/ 64 <408000000>;
115 opp-microvolt = <950000 950000 1340000>;
116 clock-latency-ns = <40000>;
117 opp-suspend;
119 opp-600000000 {
120 opp-hz = /bits/ 64 <600000000>;
121 opp-microvolt = <950000 950000 1340000>;
122 clock-latency-ns = <40000>;
124 opp-816000000 {
125 opp-hz = /bits/ 64 <816000000>;
126 opp-microvolt = <1025000 1025000 1340000>;
127 clock-latency-ns = <40000>;
129 opp-1008000000 {
130 opp-hz = /bits/ 64 <1008000000>;
131 opp-microvolt = <1125000 1125000 1340000>;
132 clock-latency-ns = <40000>;
136 arm-pmu {
137 compatible = "arm,cortex-a35-pmu";
142 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
145 mac_clkin: external-mac-clock {
146 compatible = "fixed-clock";
147 clock-frequency = <50000000>;
148 clock-output-names = "mac_clkin";
149 #clock-cells = <0>;
153 compatible = "arm,psci-1.0";
158 compatible = "arm,armv8-timer";
166 compatible = "fixed-clock";
167 #clock-cells = <0>;
168 clock-frequency = <24000000>;
169 clock-output-names = "xin24m";
172 grf: grf@ff000000 { label
173 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd";
176 io_domains: io-domains {
177 compatible = "rockchip,rk3308-io-voltage-domain";
181 reboot-mode {
182 compatible = "syscon-reboot-mode";
184 mode-bootloader = <BOOT_BL_DOWNLOAD>;
185 mode-loader = <BOOT_BL_DOWNLOAD>;
186 mode-normal = <BOOT_NORMAL>;
187 mode-recovery = <BOOT_RECOVERY>;
188 mode-fastboot = <BOOT_FASTBOOT>;
193 compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd";
195 #address-cells = <1>;
196 #size-cells = <1>;
199 compatible = "rockchip,rk3308-usb2phy";
201 assigned-clocks = <&cru USB480M>;
202 assigned-clock-parents = <&u2phy>;
204 clock-names = "phyclk";
205 clock-output-names = "usb480m_phy";
206 #clock-cells = <0>;
209 u2phy_otg: otg-port {
213 interrupt-names = "otg-bvalid", "otg-id",
215 #phy-cells = <0>;
219 u2phy_host: host-port {
221 interrupt-names = "linestate";
222 #phy-cells = <0>;
229 compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd";
231 #address-cells = <1>;
232 #size-cells = <1>;
236 compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd";
238 #address-cells = <1>;
239 #size-cells = <1>;
243 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
246 clock-names = "i2c", "pclk";
248 pinctrl-names = "default";
249 pinctrl-0 = <&i2c0_xfer>;
250 #address-cells = <1>;
251 #size-cells = <0>;
256 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
259 clock-names = "i2c", "pclk";
261 pinctrl-names = "default";
262 pinctrl-0 = <&i2c1_xfer>;
263 #address-cells = <1>;
264 #size-cells = <0>;
269 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
272 clock-names = "i2c", "pclk";
274 pinctrl-names = "default";
275 pinctrl-0 = <&i2c2_xfer>;
276 #address-cells = <1>;
277 #size-cells = <0>;
282 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
285 clock-names = "i2c", "pclk";
287 pinctrl-names = "default";
288 pinctrl-0 = <&i2c3m0_xfer>;
289 #address-cells = <1>;
290 #size-cells = <0>;
295 compatible = "rockchip,rk3308-wdt", "snps,dw-wdt";
303 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
307 clock-names = "baudclk", "apb_pclk";
308 reg-shift = <2>;
309 reg-io-width = <4>;
310 pinctrl-names = "default";
311 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
316 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
320 clock-names = "baudclk", "apb_pclk";
321 reg-shift = <2>;
322 reg-io-width = <4>;
323 pinctrl-names = "default";
324 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
329 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
333 clock-names = "baudclk", "apb_pclk";
334 reg-shift = <2>;
335 reg-io-width = <4>;
336 pinctrl-names = "default";
337 pinctrl-0 = <&uart2m0_xfer>;
342 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
346 clock-names = "baudclk", "apb_pclk";
347 reg-shift = <2>;
348 reg-io-width = <4>;
349 pinctrl-names = "default";
350 pinctrl-0 = <&uart3_xfer>;
355 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
359 clock-names = "baudclk", "apb_pclk";
360 reg-shift = <2>;
361 reg-io-width = <4>;
362 pinctrl-names = "default";
363 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
368 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
371 #address-cells = <1>;
372 #size-cells = <0>;
374 clock-names = "spiclk", "apb_pclk";
376 dma-names = "tx", "rx";
377 pinctrl-names = "default";
378 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>;
383 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
386 #address-cells = <1>;
387 #size-cells = <0>;
389 clock-names = "spiclk", "apb_pclk";
391 dma-names = "tx", "rx";
392 pinctrl-names = "default";
393 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>;
398 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
401 #address-cells = <1>;
402 #size-cells = <0>;
404 clock-names = "spiclk", "apb_pclk";
406 dma-names = "tx", "rx";
407 pinctrl-names = "default";
408 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>;
413 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
416 clock-names = "pwm", "pclk";
417 pinctrl-names = "default";
418 pinctrl-0 = <&pwm8_pin>;
419 #pwm-cells = <3>;
424 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
427 clock-names = "pwm", "pclk";
428 pinctrl-names = "default";
429 pinctrl-0 = <&pwm9_pin>;
430 #pwm-cells = <3>;
435 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
438 clock-names = "pwm", "pclk";
439 pinctrl-names = "default";
440 pinctrl-0 = <&pwm10_pin>;
441 #pwm-cells = <3>;
446 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
449 clock-names = "pwm", "pclk";
450 pinctrl-names = "default";
451 pinctrl-0 = <&pwm11_pin>;
452 #pwm-cells = <3>;
457 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
460 clock-names = "pwm", "pclk";
461 pinctrl-names = "default";
462 pinctrl-0 = <&pwm4_pin>;
463 #pwm-cells = <3>;
468 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
471 clock-names = "pwm", "pclk";
472 pinctrl-names = "default";
473 pinctrl-0 = <&pwm5_pin>;
474 #pwm-cells = <3>;
479 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
482 clock-names = "pwm", "pclk";
483 pinctrl-names = "default";
484 pinctrl-0 = <&pwm6_pin>;
485 #pwm-cells = <3>;
490 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
493 clock-names = "pwm", "pclk";
494 pinctrl-names = "default";
495 pinctrl-0 = <&pwm7_pin>;
496 #pwm-cells = <3>;
501 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
504 clock-names = "pwm", "pclk";
505 pinctrl-names = "default";
506 pinctrl-0 = <&pwm0_pin>;
507 #pwm-cells = <3>;
512 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
515 clock-names = "pwm", "pclk";
516 pinctrl-names = "default";
517 pinctrl-0 = <&pwm1_pin>;
518 #pwm-cells = <3>;
523 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
526 clock-names = "pwm", "pclk";
527 pinctrl-names = "default";
528 pinctrl-0 = <&pwm2_pin>;
529 #pwm-cells = <3>;
534 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
537 clock-names = "pwm", "pclk";
538 pinctrl-names = "default";
539 pinctrl-0 = <&pwm3_pin>;
540 #pwm-cells = <3>;
545 compatible = "rockchip,rk3288-timer";
549 clock-names = "pclk", "timer";
553 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc";
557 clock-names = "saradc", "apb_pclk";
558 #io-channel-cells = <1>;
560 reset-names = "saradc-apb";
565 compatible = "rockchip,rk3308-otp";
567 #address-cells = <1>;
568 #size-cells = <1>;
571 clock-names = "otp", "apb_pclk", "phy";
573 reset-names = "phy";
579 cpu_leakage: cpu-leakage@17 {
583 logic_leakage: logic-leakage@18 {
588 dmac0: dma-controller@ff2c0000 {
593 arm,pl330-periph-burst;
595 clock-names = "apb_pclk";
596 #dma-cells = <1>;
599 dmac1: dma-controller@ff2d0000 {
604 arm,pl330-periph-burst;
606 clock-names = "apb_pclk";
607 #dma-cells = <1>;
611 * - can be clock producer or consumer
612 * - up to 8 capture channels and 2 playback channels
613 * - connected internally to audio codec
616 compatible = "rockchip,rk3308-i2s-tdm";
619 clock-names = "mclk_tx", "mclk_rx", "hclk";
624 dma-names = "rx", "tx";
626 reset-names = "tx-m", "rx-m";
627 rockchip,grf = <&grf>;
632 * - can be clock consumer only
633 * - up to 4 capture channels, no playback
634 * - connected internally to audio codec
637 compatible = "rockchip,rk3308-i2s-tdm";
640 clock-names = "mclk_tx", "mclk_rx", "hclk";
645 dma-names = "rx";
647 reset-names = "tx-m", "rx-m";
648 rockchip,grf = <&grf>;
653 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
657 clock-names = "i2s_clk", "i2s_hclk";
659 dma-names = "tx", "rx";
661 reset-names = "reset-m", "reset-h";
662 pinctrl-names = "default";
663 pinctrl-0 = <&i2s_2ch_0_sclk
671 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
675 clock-names = "i2s_clk", "i2s_hclk";
677 dma-names = "rx";
679 reset-names = "reset-m", "reset-h";
683 spdif_tx: spdif-tx@ff3a0000 {
684 compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif";
688 clock-names = "mclk", "hclk";
690 dma-names = "tx";
691 pinctrl-names = "default";
692 pinctrl-0 = <&spdif_out>;
697 compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb",
702 clock-names = "otg";
704 g-np-tx-fifo-size = <16>;
705 g-rx-fifo-size = <280>;
706 g-tx-fifo-size = <256 128 128 64 32 16>;
708 phy-names = "usb2-phy";
713 compatible = "generic-ehci";
718 phy-names = "usb";
723 compatible = "generic-ohci";
728 phy-names = "usb";
733 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
736 bus-width = <4>;
739 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
740 fifo-depth = <0x100>;
741 max-frequency = <150000000>;
742 pinctrl-names = "default";
743 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
748 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
751 bus-width = <8>;
754 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
755 fifo-depth = <0x100>;
756 max-frequency = <150000000>;
761 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
764 bus-width = <4>;
767 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
768 fifo-depth = <0x100>;
769 max-frequency = <150000000>;
770 pinctrl-names = "default";
771 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
775 nfc: nand-controller@ff4b0000 {
776 compatible = "rockchip,rk3308-nfc",
777 "rockchip,rv1108-nfc";
781 clock-names = "ahb", "nfc";
782 assigned-clocks = <&cru SCLK_NANDC>;
783 assigned-clock-rates = <150000000>;
784 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
786 pinctrl-names = "default";
791 compatible = "rockchip,rk3308-gmac";
794 interrupt-names = "macirq";
799 clock-names = "stmmaceth", "mac_clk_rx",
803 phy-mode = "rmii";
804 pinctrl-names = "default";
805 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
807 reset-names = "stmmaceth";
808 rockchip,grf = <&grf>;
817 clock-names = "clk_sfc", "hclk_sfc";
818 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
819 pinctrl-names = "default";
823 cru: clock-controller@ff500000 {
824 compatible = "rockchip,rk3308-cru";
827 clock-names = "xin24m";
828 rockchip,grf = <&grf>;
829 #clock-cells = <1>;
830 #reset-cells = <1>;
831 assigned-clocks = <&cru SCLK_RTC32K>;
832 assigned-clock-rates = <32768>;
836 compatible = "rockchip,rk3308-codec";
838 rockchip,grf = <&grf>;
839 clock-names = "mclk_tx", "mclk_rx", "hclk";
843 reset-names = "codec";
845 #sound-dai-cells = <0>;
849 gic: interrupt-controller@ff580000 {
850 compatible = "arm,gic-400";
856 #interrupt-cells = <3>;
857 interrupt-controller;
858 #address-cells = <0>;
862 compatible = "mmio-sram";
865 #address-cells = <1>;
866 #size-cells = <1>;
869 ddr-sram@0 {
874 vad_sram: vad-sram@8000 {
880 compatible = "rockchip,rk3308-pinctrl";
881 rockchip,grf = <&grf>;
882 #address-cells = <2>;
883 #size-cells = <2>;
886 gpio0: gpio@ff220000 {
887 compatible = "rockchip,gpio-bank";
891 gpio-controller;
892 #gpio-cells = <2>;
893 interrupt-controller;
894 #interrupt-cells = <2>;
897 gpio1: gpio@ff230000 {
898 compatible = "rockchip,gpio-bank";
902 gpio-controller;
903 #gpio-cells = <2>;
904 interrupt-controller;
905 #interrupt-cells = <2>;
908 gpio2: gpio@ff240000 {
909 compatible = "rockchip,gpio-bank";
913 gpio-controller;
914 #gpio-cells = <2>;
915 interrupt-controller;
916 #interrupt-cells = <2>;
919 gpio3: gpio@ff250000 {
920 compatible = "rockchip,gpio-bank";
924 gpio-controller;
925 #gpio-cells = <2>;
926 interrupt-controller;
927 #interrupt-cells = <2>;
930 gpio4: gpio@ff260000 {
931 compatible = "rockchip,gpio-bank";
935 gpio-controller;
936 #gpio-cells = <2>;
937 interrupt-controller;
938 #interrupt-cells = <2>;
941 pcfg_pull_up: pcfg-pull-up {
942 bias-pull-up;
945 pcfg_pull_down: pcfg-pull-down {
946 bias-pull-down;
949 pcfg_pull_none: pcfg-pull-none {
950 bias-disable;
953 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
954 bias-disable;
955 drive-strength = <2>;
958 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
959 bias-pull-up;
960 drive-strength = <2>;
963 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
964 bias-pull-up;
965 drive-strength = <4>;
968 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
969 bias-disable;
970 drive-strength = <4>;
973 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
974 bias-pull-down;
975 drive-strength = <4>;
978 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
979 bias-disable;
980 drive-strength = <8>;
983 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
984 bias-pull-up;
985 drive-strength = <8>;
988 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
989 bias-disable;
990 drive-strength = <12>;
993 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
994 bias-pull-up;
995 drive-strength = <12>;
998 pcfg_pull_none_smt: pcfg-pull-none-smt {
999 bias-disable;
1000 input-schmitt-enable;
1003 pcfg_output_high: pcfg-output-high {
1004 output-high;
1007 pcfg_output_low: pcfg-output-low {
1008 output-low;
1011 pcfg_input_high: pcfg-input-high {
1012 bias-pull-up;
1013 input-enable;
1016 pcfg_input: pcfg-input {
1017 input-enable;
1021 emmc_clk: emmc-clk {
1026 emmc_cmd: emmc-cmd {
1031 emmc_pwren: emmc-pwren {
1036 emmc_rstn: emmc-rstn {
1041 emmc_bus1: emmc-bus1 {
1046 emmc_bus4: emmc-bus4 {
1054 emmc_bus8: emmc-bus8 {
1068 flash_csn0: flash-csn0 {
1073 flash_rdy: flash-rdy {
1078 flash_ale: flash-ale {
1083 flash_cle: flash-cle {
1088 flash_wrn: flash-wrn {
1093 flash_rdn: flash-rdn {
1098 flash_bus8: flash-bus8 {
1112 sfc_bus4: sfc-bus4 {
1120 sfc_bus2: sfc-bus2 {
1126 sfc_cs0: sfc-cs0 {
1131 sfc_clk: sfc-clk {
1138 rmii_pins: rmii-pins {
1160 mac_refclk_12ma: mac-refclk-12ma {
1165 mac_refclk: mac-refclk {
1171 gmac-m1 {
1172 rmiim1_pins: rmiim1-pins {
1194 macm1_refclk_12ma: macm1-refclk-12ma {
1199 macm1_refclk: macm1-refclk {
1206 i2c0_xfer: i2c0-xfer {
1214 i2c1_xfer: i2c1-xfer {
1222 i2c2_xfer: i2c2-xfer {
1229 i2c3-m0 {
1230 i2c3m0_xfer: i2c3m0-xfer {
1237 i2c3-m1 {
1238 i2c3m1_xfer: i2c3m1-xfer {
1245 i2c3-m2 {
1246 i2c3m2_xfer: i2c3m2-xfer {
1254 i2s_2ch_0_mclk: i2s-2ch-0-mclk {
1259 i2s_2ch_0_sclk: i2s-2ch-0-sclk {
1264 i2s_2ch_0_lrck: i2s-2ch-0-lrck {
1269 i2s_2ch_0_sdo: i2s-2ch-0-sdo {
1274 i2s_2ch_0_sdi: i2s-2ch-0-sdi {
1281 i2s_8ch_0_mclk: i2s-8ch-0-mclk {
1286 i2s_8ch_0_sclktx: i2s-8ch-0-sclktx {
1291 i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx {
1296 i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx {
1301 i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx {
1306 i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 {
1311 i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 {
1316 i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 {
1321 i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 {
1326 i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 {
1331 i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 {
1336 i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 {
1341 i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 {
1348 i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk {
1353 i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx {
1358 i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx {
1363 i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx {
1368 i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx {
1373 i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 {
1378 i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 {
1383 i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 {
1388 i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 {
1393 i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 {
1400 i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk {
1405 i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx {
1410 i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx {
1415 i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx {
1420 i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx {
1425 i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 {
1430 i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 {
1435 i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 {
1440 i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 {
1445 i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 {
1452 pdm_m0_clk: pdm-m0-clk {
1457 pdm_m0_sdi0: pdm-m0-sdi0 {
1462 pdm_m0_sdi1: pdm-m0-sdi1 {
1467 pdm_m0_sdi2: pdm-m0-sdi2 {
1472 pdm_m0_sdi3: pdm-m0-sdi3 {
1479 pdm_m1_clk: pdm-m1-clk {
1484 pdm_m1_sdi0: pdm-m1-sdi0 {
1489 pdm_m1_sdi1: pdm-m1-sdi1 {
1494 pdm_m1_sdi2: pdm-m1-sdi2 {
1499 pdm_m1_sdi3: pdm-m1-sdi3 {
1506 pdm_m2_clkm: pdm-m2-clkm {
1511 pdm_m2_clk: pdm-m2-clk {
1516 pdm_m2_sdi0: pdm-m2-sdi0 {
1521 pdm_m2_sdi1: pdm-m2-sdi1 {
1526 pdm_m2_sdi2: pdm-m2-sdi2 {
1531 pdm_m2_sdi3: pdm-m2-sdi3 {
1538 pwm0_pin: pwm0-pin {
1543 pwm0_pin_pull_down: pwm0-pin-pull-down {
1550 pwm1_pin: pwm1-pin {
1555 pwm1_pin_pull_down: pwm1-pin-pull-down {
1562 pwm2_pin: pwm2-pin {
1567 pwm2_pin_pull_down: pwm2-pin-pull-down {
1574 pwm3_pin: pwm3-pin {
1579 pwm3_pin_pull_down: pwm3-pin-pull-down {
1586 pwm4_pin: pwm4-pin {
1591 pwm4_pin_pull_down: pwm4-pin-pull-down {
1598 pwm5_pin: pwm5-pin {
1603 pwm5_pin_pull_down: pwm5-pin-pull-down {
1610 pwm6_pin: pwm6-pin {
1615 pwm6_pin_pull_down: pwm6-pin-pull-down {
1622 pwm7_pin: pwm7-pin {
1627 pwm7_pin_pull_down: pwm7-pin-pull-down {
1634 pwm8_pin: pwm8-pin {
1639 pwm8_pin_pull_down: pwm8-pin-pull-down {
1646 pwm9_pin: pwm9-pin {
1651 pwm9_pin_pull_down: pwm9-pin-pull-down {
1658 pwm10_pin: pwm10-pin {
1663 pwm10_pin_pull_down: pwm10-pin-pull-down {
1670 pwm11_pin: pwm11-pin {
1675 pwm11_pin_pull_down: pwm11-pin-pull-down {
1682 rtc_32k: rtc-32k {
1689 sdmmc_clk: sdmmc-clk {
1694 sdmmc_cmd: sdmmc-cmd {
1699 sdmmc_det: sdmmc-det {
1704 sdmmc_pwren: sdmmc-pwren {
1709 sdmmc_bus1: sdmmc-bus1 {
1714 sdmmc_bus4: sdmmc-bus4 {
1724 sdio_clk: sdio-clk {
1729 sdio_cmd: sdio-cmd {
1734 sdio_pwren: sdio-pwren {
1739 sdio_wrpt: sdio-wrpt {
1744 sdio_intn: sdio-intn {
1749 sdio_bus1: sdio-bus1 {
1754 sdio_bus4: sdio-bus4 {
1764 spdif_in: spdif-in {
1771 spdif_out: spdif-out {
1778 spi0_clk: spi0-clk {
1783 spi0_csn0: spi0-csn0 {
1788 spi0_miso: spi0-miso {
1793 spi0_mosi: spi0-mosi {
1800 spi1_clk: spi1-clk {
1805 spi1_csn0: spi1-csn0 {
1810 spi1_miso: spi1-miso {
1815 spi1_mosi: spi1-mosi {
1821 spi1-m1 {
1822 spi1m1_miso: spi1m1-miso {
1827 spi1m1_mosi: spi1m1-mosi {
1832 spi1m1_clk: spi1m1-clk {
1837 spi1m1_csn0: spi1m1-csn0 {
1844 spi2_clk: spi2-clk {
1849 spi2_csn0: spi2-csn0 {
1854 spi2_miso: spi2-miso {
1859 spi2_mosi: spi2-mosi {
1866 tsadc_otp_pin: tsadc-otp-pin {
1871 tsadc_otp_out: tsadc-otp-out {
1878 uart0_xfer: uart0-xfer {
1884 uart0_cts: uart0-cts {
1889 uart0_rts: uart0-rts {
1894 uart0_rts_pin: uart0-rts-pin {
1901 uart1_xfer: uart1-xfer {
1907 uart1_cts: uart1-cts {
1912 uart1_rts: uart1-rts {
1918 uart2-m0 {
1919 uart2m0_xfer: uart2m0-xfer {
1926 uart2-m1 {
1927 uart2m1_xfer: uart2m1-xfer {
1935 uart3_xfer: uart3-xfer {
1942 uart3-m1 {
1943 uart3m1_xfer: uart3m1-xfer {
1951 uart4_xfer: uart4-xfer {
1957 uart4_cts: uart4-cts {
1962 uart4_rts: uart4-rts {
1967 uart4_rts_pin: uart4-rts-pin {