Lines Matching +full:0 +full:xff3a0000
44 #size-cells = <0>;
46 cpu0: cpu@0 {
49 reg = <0x0 0x0>;
62 reg = <0x0 0x1>;
72 reg = <0x0 0x2>;
82 reg = <0x0 0x3>;
95 arm,psci-suspend-param = <0x0010000>;
109 cpu0_opp_table: opp-table-0 {
149 #clock-cells = <0>;
167 #clock-cells = <0>;
174 reg = <0x0 0xff000000 0x0 0x08000>;
183 offset = <0x500>;
194 reg = <0x0 0xff008000 0x0 0x4000>;
200 reg = <0x100 0x10>;
206 #clock-cells = <0>;
215 #phy-cells = <0>;
222 #phy-cells = <0>;
230 reg = <0x0 0xff00b000 0x0 0x1000>;
237 reg = <0x0 0xff00c000 0x0 0x1000>;
244 reg = <0x0 0xff040000 0x0 0x1000>;
249 pinctrl-0 = <&i2c0_xfer>;
251 #size-cells = <0>;
257 reg = <0x0 0xff050000 0x0 0x1000>;
262 pinctrl-0 = <&i2c1_xfer>;
264 #size-cells = <0>;
270 reg = <0x0 0xff060000 0x0 0x1000>;
275 pinctrl-0 = <&i2c2_xfer>;
277 #size-cells = <0>;
283 reg = <0x0 0xff070000 0x0 0x1000>;
288 pinctrl-0 = <&i2c3m0_xfer>;
290 #size-cells = <0>;
296 reg = <0x0 0xff080000 0x0 0x100>;
304 reg = <0x0 0xff0a0000 0x0 0x100>;
311 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
317 reg = <0x0 0xff0b0000 0x0 0x100>;
324 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
330 reg = <0x0 0xff0c0000 0x0 0x100>;
337 pinctrl-0 = <&uart2m0_xfer>;
343 reg = <0x0 0xff0d0000 0x0 0x100>;
350 pinctrl-0 = <&uart3_xfer>;
356 reg = <0x0 0xff0e0000 0x0 0x100>;
363 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
369 reg = <0x0 0xff120000 0x0 0x1000>;
372 #size-cells = <0>;
375 dmas = <&dmac0 0>, <&dmac0 1>;
378 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>;
384 reg = <0x0 0xff130000 0x0 0x1000>;
387 #size-cells = <0>;
393 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>;
399 reg = <0x0 0xff140000 0x0 0x1000>;
402 #size-cells = <0>;
408 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>;
414 reg = <0x0 0xff160000 0x0 0x10>;
418 pinctrl-0 = <&pwm8_pin>;
425 reg = <0x0 0xff160010 0x0 0x10>;
429 pinctrl-0 = <&pwm9_pin>;
436 reg = <0x0 0xff160020 0x0 0x10>;
440 pinctrl-0 = <&pwm10_pin>;
447 reg = <0x0 0xff160030 0x0 0x10>;
451 pinctrl-0 = <&pwm11_pin>;
458 reg = <0x0 0xff170000 0x0 0x10>;
462 pinctrl-0 = <&pwm4_pin>;
469 reg = <0x0 0xff170010 0x0 0x10>;
473 pinctrl-0 = <&pwm5_pin>;
480 reg = <0x0 0xff170020 0x0 0x10>;
484 pinctrl-0 = <&pwm6_pin>;
491 reg = <0x0 0xff170030 0x0 0x10>;
495 pinctrl-0 = <&pwm7_pin>;
502 reg = <0x0 0xff180000 0x0 0x10>;
506 pinctrl-0 = <&pwm0_pin>;
513 reg = <0x0 0xff180010 0x0 0x10>;
517 pinctrl-0 = <&pwm1_pin>;
524 reg = <0x0 0xff180020 0x0 0x10>;
528 pinctrl-0 = <&pwm2_pin>;
535 reg = <0x0 0xff180030 0x0 0x10>;
539 pinctrl-0 = <&pwm3_pin>;
546 reg = <0x0 0xff1a0000 0x0 0x20>;
554 reg = <0x0 0xff1e0000 0x0 0x100>;
566 reg = <0x0 0xff210000 0x0 0x4000>;
576 reg = <0x07 0x10>;
580 reg = <0x17 0x1>;
584 reg = <0x18 0x1>;
590 reg = <0x0 0xff2c0000 0x0 0x4000>;
591 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
601 reg = <0x0 0xff2d0000 0x0 0x4000>;
617 reg = <0x0 0xff320000 0x0 0x1000>;
638 reg = <0x0 0xff330000 0x0 0x1000>;
654 reg = <0x0 0xff350000 0x0 0x1000>;
663 pinctrl-0 = <&i2s_2ch_0_sclk
672 reg = <0x0 0xff360000 0x0 0x1000>;
685 reg = <0x0 0xff3a0000 0x0 0x1000>;
692 pinctrl-0 = <&spdif_out>;
699 reg = <0x0 0xff400000 0x0 0x40000>;
714 reg = <0x0 0xff440000 0x0 0x10000>;
724 reg = <0x0 0xff450000 0x0 0x10000>;
734 reg = <0x0 0xff480000 0x0 0x4000>;
740 fifo-depth = <0x100>;
743 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
749 reg = <0x0 0xff490000 0x0 0x4000>;
755 fifo-depth = <0x100>;
762 reg = <0x0 0xff4a0000 0x0 0x4000>;
768 fifo-depth = <0x100>;
771 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
778 reg = <0x0 0xff4b0000 0x0 0x4000>;
784 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
792 reg = <0x0 0xff4e0000 0x0 0x10000>;
805 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
814 reg = <0x0 0xff4c0000 0x0 0x4000>;
818 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
825 reg = <0x0 0xff500000 0x0 0x1000>;
837 reg = <0x0 0xff560000 0x0 0x10000>;
845 #sound-dai-cells = <0>;
851 reg = <0x0 0xff581000 0x0 0x1000>,
852 <0x0 0xff582000 0x0 0x2000>,
853 <0x0 0xff584000 0x0 0x2000>,
854 <0x0 0xff586000 0x0 0x2000>;
858 #address-cells = <0>;
863 reg = <0x0 0xfff80000 0x0 0x40000>;
864 ranges = <0 0x0 0xfff80000 0x40000>;
869 ddr-sram@0 {
870 reg = <0x0 0x8000>;
875 reg = <0x8000 0x38000>;
888 reg = <0x0 0xff220000 0x0 0x100>;
899 reg = <0x0 0xff230000 0x0 0x100>;
910 reg = <0x0 0xff240000 0x0 0x100>;
921 reg = <0x0 0xff250000 0x0 0x100>;
932 reg = <0x0 0xff260000 0x0 0x100>;
1216 <0 RK_PB3 1 &pcfg_pull_none_smt>,
1217 <0 RK_PB4 1 &pcfg_pull_none_smt>;
1232 <0 RK_PB7 2 &pcfg_pull_none_smt>,
1233 <0 RK_PC0 2 &pcfg_pull_none_smt>;
1254 i2s_2ch_0_mclk: i2s-2ch-0-mclk {
1259 i2s_2ch_0_sclk: i2s-2ch-0-sclk {
1264 i2s_2ch_0_lrck: i2s-2ch-0-lrck {
1269 i2s_2ch_0_sdo: i2s-2ch-0-sdo {
1274 i2s_2ch_0_sdi: i2s-2ch-0-sdi {
1281 i2s_8ch_0_mclk: i2s-8ch-0-mclk {
1286 i2s_8ch_0_sclktx: i2s-8ch-0-sclktx {
1291 i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx {
1296 i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx {
1301 i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx {
1306 i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 {
1311 i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 {
1316 i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 {
1321 i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 {
1326 i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 {
1331 i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 {
1336 i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 {
1341 i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 {
1540 <0 RK_PB5 1 &pcfg_pull_none>;
1545 <0 RK_PB5 1 &pcfg_pull_down>;
1552 <0 RK_PB6 1 &pcfg_pull_none>;
1557 <0 RK_PB6 1 &pcfg_pull_down>;
1564 <0 RK_PB7 1 &pcfg_pull_none>;
1569 <0 RK_PB7 1 &pcfg_pull_down>;
1576 <0 RK_PC0 1 &pcfg_pull_none>;
1581 <0 RK_PC0 1 &pcfg_pull_down>;
1588 <0 RK_PA1 2 &pcfg_pull_none>;
1593 <0 RK_PA1 2 &pcfg_pull_down>;
1600 <0 RK_PC1 2 &pcfg_pull_none>;
1605 <0 RK_PC1 2 &pcfg_pull_down>;
1612 <0 RK_PC2 2 &pcfg_pull_none>;
1617 <0 RK_PC2 2 &pcfg_pull_down>;
1684 <0 RK_PC3 1 &pcfg_pull_none>;
1701 <0 RK_PA3 1 &pcfg_pull_up_4ma>;
1736 <0 RK_PA2 1 &pcfg_pull_none_8ma>;
1741 <0 RK_PA1 1 &pcfg_pull_none_8ma>;
1746 <0 RK_PA0 1 &pcfg_pull_none_8ma>;
1766 <0 RK_PC2 1 &pcfg_pull_none>;
1773 <0 RK_PC1 1 &pcfg_pull_none>;
1868 <0 RK_PB2 0 &pcfg_pull_none>;
1873 <0 RK_PB2 1 &pcfg_pull_none>;
1896 <2 RK_PA3 0 &pcfg_pull_none>;
1945 <0 RK_PC2 3 &pcfg_pull_up>,
1946 <0 RK_PC1 3 &pcfg_pull_up>;
1969 <4 RK_PA7 0 &pcfg_pull_none>;