Lines Matching +full:spi1 +full:- +full:default +full:- +full:pins
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/px30-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/px30-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
34 spi1 = &spi1;
38 #address-cells = <2>;
39 #size-cells = <0>;
43 compatible = "arm,cortex-a35";
45 enable-method = "psci";
47 #cooling-cells = <2>;
48 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
49 dynamic-power-coefficient = <90>;
50 operating-points-v2 = <&cpu0_opp_table>;
55 compatible = "arm,cortex-a35";
57 enable-method = "psci";
59 #cooling-cells = <2>;
60 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
61 dynamic-power-coefficient = <90>;
62 operating-points-v2 = <&cpu0_opp_table>;
67 compatible = "arm,cortex-a35";
69 enable-method = "psci";
71 #cooling-cells = <2>;
72 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
73 dynamic-power-coefficient = <90>;
74 operating-points-v2 = <&cpu0_opp_table>;
79 compatible = "arm,cortex-a35";
81 enable-method = "psci";
83 #cooling-cells = <2>;
84 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
85 dynamic-power-coefficient = <90>;
86 operating-points-v2 = <&cpu0_opp_table>;
89 idle-states {
90 entry-method = "psci";
92 CPU_SLEEP: cpu-sleep {
93 compatible = "arm,idle-state";
94 local-timer-stop;
95 arm,psci-suspend-param = <0x0010000>;
96 entry-latency-us = <120>;
97 exit-latency-us = <250>;
98 min-residency-us = <900>;
101 CLUSTER_SLEEP: cluster-sleep {
102 compatible = "arm,idle-state";
103 local-timer-stop;
104 arm,psci-suspend-param = <0x1010000>;
105 entry-latency-us = <400>;
106 exit-latency-us = <500>;
107 min-residency-us = <2000>;
112 cpu0_opp_table: opp-table-0 {
113 compatible = "operating-points-v2";
114 opp-shared;
116 opp-600000000 {
117 opp-hz = /bits/ 64 <600000000>;
118 opp-microvolt = <950000 950000 1350000>;
119 clock-latency-ns = <40000>;
120 opp-suspend;
122 opp-816000000 {
123 opp-hz = /bits/ 64 <816000000>;
124 opp-microvolt = <1050000 1050000 1350000>;
125 clock-latency-ns = <40000>;
127 opp-1008000000 {
128 opp-hz = /bits/ 64 <1008000000>;
129 opp-microvolt = <1175000 1175000 1350000>;
130 clock-latency-ns = <40000>;
132 opp-1200000000 {
133 opp-hz = /bits/ 64 <1200000000>;
134 opp-microvolt = <1300000 1300000 1350000>;
135 clock-latency-ns = <40000>;
137 opp-1296000000 {
138 opp-hz = /bits/ 64 <1296000000>;
139 opp-microvolt = <1350000 1350000 1350000>;
140 clock-latency-ns = <40000>;
144 arm-pmu {
145 compatible = "arm,cortex-a35-pmu";
150 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
153 display_subsystem: display-subsystem {
154 compatible = "rockchip,display-subsystem";
159 gmac_clkin: external-gmac-clock {
160 compatible = "fixed-clock";
161 clock-frequency = <50000000>;
162 clock-output-names = "gmac_clkin";
163 #clock-cells = <0>;
167 compatible = "arm,psci-1.0";
172 compatible = "arm,armv8-timer";
179 thermal_zones: thermal-zones {
180 soc_thermal: soc-thermal {
181 polling-delay-passive = <20>;
182 polling-delay = <1000>;
183 sustainable-power = <750>;
184 thermal-sensors = <&tsadc 0>;
187 threshold: trip-point-0 {
193 target: trip-point-1 {
199 soc_crit: soc-crit {
206 cooling-maps {
209 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
215 gpu_thermal: gpu-thermal {
216 polling-delay-passive = <100>; /* milliseconds */
217 polling-delay = <1000>; /* milliseconds */
218 thermal-sensors = <&tsadc 1>;
221 gpu_threshold: gpu-threshold {
227 gpu_target: gpu-target {
233 gpu_crit: gpu-crit {
240 cooling-maps {
243 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
250 compatible = "fixed-clock";
251 #clock-cells = <0>;
252 clock-frequency = <24000000>;
253 clock-output-names = "xin24m";
256 pmu: power-management@ff000000 {
257 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
260 power: power-controller {
261 compatible = "rockchip,px30-power-controller";
262 #power-domain-cells = <1>;
263 #address-cells = <1>;
264 #size-cells = <0>;
267 power-domain@PX30_PD_USB {
273 #power-domain-cells = <0>;
275 power-domain@PX30_PD_SDCARD {
280 #power-domain-cells = <0>;
282 power-domain@PX30_PD_GMAC {
289 #power-domain-cells = <0>;
291 power-domain@PX30_PD_MMC_NAND {
303 #power-domain-cells = <0>;
305 power-domain@PX30_PD_VPU {
311 #power-domain-cells = <0>;
313 power-domain@PX30_PD_VO {
328 #power-domain-cells = <0>;
330 power-domain@PX30_PD_VI {
340 #power-domain-cells = <0>;
342 power-domain@PX30_PD_GPU {
346 #power-domain-cells = <0>;
352 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
355 pmu_io_domains: io-domains {
356 compatible = "rockchip,px30-pmu-io-voltage-domain";
360 reboot-mode {
361 compatible = "syscon-reboot-mode";
363 mode-bootloader = <BOOT_BL_DOWNLOAD>;
364 mode-fastboot = <BOOT_FASTBOOT>;
365 mode-loader = <BOOT_BL_DOWNLOAD>;
366 mode-normal = <BOOT_NORMAL>;
367 mode-recovery = <BOOT_RECOVERY>;
372 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
376 clock-names = "baudclk", "apb_pclk";
378 dma-names = "tx", "rx";
379 reg-shift = <2>;
380 reg-io-width = <4>;
381 pinctrl-names = "default";
382 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
387 compatible = "rockchip,px30-i2s-tdm";
391 clock-names = "mclk_tx", "mclk_rx", "hclk";
393 dma-names = "tx", "rx";
396 reset-names = "tx-m", "rx-m";
397 pinctrl-names = "default";
398 pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx
404 #sound-dai-cells = <0>;
409 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
413 clock-names = "i2s_clk", "i2s_hclk";
415 dma-names = "tx", "rx";
416 pinctrl-names = "default";
417 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
419 #sound-dai-cells = <0>;
424 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
428 clock-names = "i2s_clk", "i2s_hclk";
430 dma-names = "tx", "rx";
431 pinctrl-names = "default";
432 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
434 #sound-dai-cells = <0>;
438 gic: interrupt-controller@ff131000 {
439 compatible = "arm,gic-400";
440 #interrupt-cells = <3>;
441 #address-cells = <0>;
442 interrupt-controller;
452 compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
455 io_domains: io-domains {
456 compatible = "rockchip,px30-io-voltage-domain";
461 compatible = "rockchip,px30-lvds";
463 phy-names = "dphy";
469 #address-cells = <1>;
470 #size-cells = <0>;
474 #address-cells = <1>;
475 #size-cells = <0>;
479 remote-endpoint = <&vopb_out_lvds>;
484 remote-endpoint = <&vopl_out_lvds>;
496 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
500 clock-names = "baudclk", "apb_pclk";
502 dma-names = "tx", "rx";
503 reg-shift = <2>;
504 reg-io-width = <4>;
505 pinctrl-names = "default";
506 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
511 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
515 clock-names = "baudclk", "apb_pclk";
517 dma-names = "tx", "rx";
518 reg-shift = <2>;
519 reg-io-width = <4>;
520 pinctrl-names = "default";
521 pinctrl-0 = <&uart2m0_xfer>;
526 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
530 clock-names = "baudclk", "apb_pclk";
532 dma-names = "tx", "rx";
533 reg-shift = <2>;
534 reg-io-width = <4>;
535 pinctrl-names = "default";
536 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
541 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
545 clock-names = "baudclk", "apb_pclk";
547 dma-names = "tx", "rx";
548 reg-shift = <2>;
549 reg-io-width = <4>;
550 pinctrl-names = "default";
551 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
556 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
560 clock-names = "baudclk", "apb_pclk";
562 dma-names = "tx", "rx";
563 reg-shift = <2>;
564 reg-io-width = <4>;
565 pinctrl-names = "default";
566 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
571 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
574 clock-names = "i2c", "pclk";
576 pinctrl-names = "default";
577 pinctrl-0 = <&i2c0_xfer>;
578 #address-cells = <1>;
579 #size-cells = <0>;
584 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
587 clock-names = "i2c", "pclk";
589 pinctrl-names = "default";
590 pinctrl-0 = <&i2c1_xfer>;
591 #address-cells = <1>;
592 #size-cells = <0>;
597 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
600 clock-names = "i2c", "pclk";
602 pinctrl-names = "default";
603 pinctrl-0 = <&i2c2_xfer>;
604 #address-cells = <1>;
605 #size-cells = <0>;
610 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
613 clock-names = "i2c", "pclk";
615 pinctrl-names = "default";
616 pinctrl-0 = <&i2c3_xfer>;
617 #address-cells = <1>;
618 #size-cells = <0>;
623 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
627 clock-names = "spiclk", "apb_pclk";
629 dma-names = "tx", "rx";
630 num-cs = <2>;
631 pinctrl-names = "default";
632 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
633 #address-cells = <1>;
634 #size-cells = <0>;
638 spi1: spi@ff1d8000 { label
639 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
643 clock-names = "spiclk", "apb_pclk";
645 dma-names = "tx", "rx";
646 num-cs = <2>;
647 pinctrl-names = "default";
648 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
649 #address-cells = <1>;
650 #size-cells = <0>;
655 compatible = "rockchip,px30-wdt", "snps,dw-wdt";
663 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
666 clock-names = "pwm", "pclk";
667 pinctrl-names = "default";
668 pinctrl-0 = <&pwm0_pin>;
669 #pwm-cells = <3>;
674 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
677 clock-names = "pwm", "pclk";
678 pinctrl-names = "default";
679 pinctrl-0 = <&pwm1_pin>;
680 #pwm-cells = <3>;
685 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
688 clock-names = "pwm", "pclk";
689 pinctrl-names = "default";
690 pinctrl-0 = <&pwm2_pin>;
691 #pwm-cells = <3>;
696 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
699 clock-names = "pwm", "pclk";
700 pinctrl-names = "default";
701 pinctrl-0 = <&pwm3_pin>;
702 #pwm-cells = <3>;
707 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
710 clock-names = "pwm", "pclk";
711 pinctrl-names = "default";
712 pinctrl-0 = <&pwm4_pin>;
713 #pwm-cells = <3>;
718 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
721 clock-names = "pwm", "pclk";
722 pinctrl-names = "default";
723 pinctrl-0 = <&pwm5_pin>;
724 #pwm-cells = <3>;
729 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
732 clock-names = "pwm", "pclk";
733 pinctrl-names = "default";
734 pinctrl-0 = <&pwm6_pin>;
735 #pwm-cells = <3>;
740 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
743 clock-names = "pwm", "pclk";
744 pinctrl-names = "default";
745 pinctrl-0 = <&pwm7_pin>;
746 #pwm-cells = <3>;
751 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
755 clock-names = "pclk", "timer";
758 dmac: dma-controller@ff240000 {
763 arm,pl330-periph-burst;
765 clock-names = "apb_pclk";
766 #dma-cells = <1>;
770 compatible = "rockchip,px30-tsadc";
773 assigned-clocks = <&cru SCLK_TSADC>;
774 assigned-clock-rates = <50000>;
776 clock-names = "tsadc", "apb_pclk";
778 reset-names = "tsadc-apb";
780 rockchip,hw-tshut-temp = <120000>;
781 pinctrl-names = "init", "default", "sleep";
782 pinctrl-0 = <&tsadc_otp_pin>;
783 pinctrl-1 = <&tsadc_otp_out>;
784 pinctrl-2 = <&tsadc_otp_pin>;
785 #thermal-sensor-cells = <1>;
790 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
793 #io-channel-cells = <1>;
795 clock-names = "saradc", "apb_pclk";
797 reset-names = "saradc-apb";
802 compatible = "rockchip,px30-otp";
806 clock-names = "otp", "apb_pclk", "phy";
808 reset-names = "phy";
809 #address-cells = <1>;
810 #size-cells = <1>;
816 cpu_leakage: cpu-leakage@17 {
825 cru: clock-controller@ff2b0000 {
826 compatible = "rockchip,px30-cru";
829 clock-names = "xin24m", "gpll";
831 #clock-cells = <1>;
832 #reset-cells = <1>;
834 assigned-clocks = <&cru PLL_NPLL>,
839 assigned-clock-rates = <1188000000>,
845 pmucru: clock-controller@ff2bc000 {
846 compatible = "rockchip,px30-pmucru";
849 clock-names = "xin24m";
851 #clock-cells = <1>;
852 #reset-cells = <1>;
854 assigned-clocks =
857 assigned-clock-rates =
863 compatible = "rockchip,px30-usb2phy-grf", "syscon",
864 "simple-mfd";
866 #address-cells = <1>;
867 #size-cells = <1>;
870 compatible = "rockchip,px30-usb2phy";
873 clock-names = "phyclk";
874 #clock-cells = <0>;
875 assigned-clocks = <&cru USB480M>;
876 assigned-clock-parents = <&u2phy>;
877 clock-output-names = "usb480m_phy";
880 u2phy_host: host-port {
881 #phy-cells = <0>;
883 interrupt-names = "linestate";
887 u2phy_otg: otg-port {
888 #phy-cells = <0>;
892 interrupt-names = "otg-bvalid", "otg-id",
900 compatible = "rockchip,px30-dsi-dphy";
903 clock-names = "ref", "pclk";
905 reset-names = "apb";
906 #phy-cells = <0>;
907 power-domains = <&power PX30_PD_VO>;
912 compatible = "rockchip,px30-csi-dphy";
915 clock-names = "pclk";
916 #phy-cells = <0>;
917 power-domains = <&power PX30_PD_VI>;
919 reset-names = "apb";
925 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
930 clock-names = "otg";
932 g-np-tx-fifo-size = <16>;
933 g-rx-fifo-size = <280>;
934 g-tx-fifo-size = <256 128 128 64 32 16>;
936 phy-names = "usb2-phy";
937 power-domains = <&power PX30_PD_USB>;
942 compatible = "generic-ehci";
947 phy-names = "usb";
948 power-domains = <&power PX30_PD_USB>;
953 compatible = "generic-ohci";
958 phy-names = "usb";
959 power-domains = <&power PX30_PD_USB>;
964 compatible = "rockchip,px30-gmac";
967 interrupt-names = "macirq";
972 clock-names = "stmmaceth", "mac_clk_rx",
977 phy-mode = "rmii";
978 pinctrl-names = "default";
979 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
980 power-domains = <&power PX30_PD_GMAC>;
982 reset-names = "stmmaceth";
986 compatible = "snps,dwmac-mdio";
987 #address-cells = <1>;
988 #size-cells = <0>;
993 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
998 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
999 bus-width = <4>;
1000 fifo-depth = <0x100>;
1001 max-frequency = <150000000>;
1002 pinctrl-names = "default";
1003 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1004 power-domains = <&power PX30_PD_SDCARD>;
1009 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1014 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1015 bus-width = <4>;
1016 fifo-depth = <0x100>;
1017 max-frequency = <150000000>;
1018 pinctrl-names = "default";
1019 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
1020 power-domains = <&power PX30_PD_MMC_NAND>;
1025 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1030 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1031 bus-width = <8>;
1032 fifo-depth = <0x100>;
1033 max-frequency = <150000000>;
1034 pinctrl-names = "default";
1035 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
1036 power-domains = <&power PX30_PD_MMC_NAND>;
1045 clock-names = "clk_sfc", "hclk_sfc";
1046 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
1047 pinctrl-names = "default";
1048 power-domains = <&power PX30_PD_MMC_NAND>;
1052 nfc: nand-controller@ff3b0000 {
1053 compatible = "rockchip,px30-nfc";
1057 clock-names = "ahb", "nfc";
1058 assigned-clocks = <&cru SCLK_NANDC>;
1059 assigned-clock-rates = <150000000>;
1060 pinctrl-names = "default";
1061 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
1063 power-domains = <&power PX30_PD_MMC_NAND>;
1067 gpu_opp_table: opp-table-1 {
1068 compatible = "operating-points-v2";
1070 opp-200000000 {
1071 opp-hz = /bits/ 64 <200000000>;
1072 opp-microvolt = <950000>;
1074 opp-300000000 {
1075 opp-hz = /bits/ 64 <300000000>;
1076 opp-microvolt = <975000>;
1078 opp-400000000 {
1079 opp-hz = /bits/ 64 <400000000>;
1080 opp-microvolt = <1050000>;
1082 opp-480000000 {
1083 opp-hz = /bits/ 64 <480000000>;
1084 opp-microvolt = <1125000>;
1089 compatible = "rockchip,px30-mali", "arm,mali-bifrost";
1094 interrupt-names = "job", "mmu", "gpu";
1096 #cooling-cells = <2>;
1097 power-domains = <&power PX30_PD_GPU>;
1098 operating-points-v2 = <&gpu_opp_table>;
1102 vpu: video-codec@ff442000 {
1103 compatible = "rockchip,px30-vpu";
1107 interrupt-names = "vepu", "vdpu";
1109 clock-names = "aclk", "hclk";
1111 power-domains = <&power PX30_PD_VPU>;
1119 clock-names = "aclk", "iface";
1120 #iommu-cells = <0>;
1121 power-domains = <&power PX30_PD_VPU>;
1125 compatible = "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi";
1129 clock-names = "pclk";
1131 phy-names = "dphy";
1132 power-domains = <&power PX30_PD_VO>;
1134 reset-names = "apb";
1139 #address-cells = <1>;
1140 #size-cells = <0>;
1144 #address-cells = <1>;
1145 #size-cells = <0>;
1149 remote-endpoint = <&vopb_out_dsi>;
1154 remote-endpoint = <&vopl_out_dsi>;
1165 compatible = "rockchip,px30-vop-big";
1170 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1172 reset-names = "axi", "ahb", "dclk";
1174 power-domains = <&power PX30_PD_VO>;
1178 #address-cells = <1>;
1179 #size-cells = <0>;
1183 remote-endpoint = <&dsi_in_vopb>;
1188 remote-endpoint = <&lvds_vopb_in>;
1198 clock-names = "aclk", "iface";
1199 power-domains = <&power PX30_PD_VO>;
1200 #iommu-cells = <0>;
1205 compatible = "rockchip,px30-vop-lit";
1210 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1212 reset-names = "axi", "ahb", "dclk";
1214 power-domains = <&power PX30_PD_VO>;
1218 #address-cells = <1>;
1219 #size-cells = <0>;
1223 remote-endpoint = <&dsi_in_vopl>;
1228 remote-endpoint = <&lvds_vopl_in>;
1238 clock-names = "aclk", "iface";
1239 power-domains = <&power PX30_PD_VO>;
1240 #iommu-cells = <0>;
1245 compatible = "rockchip,px30-cif-isp"; /*rk3326-rkisp1*/
1250 interrupt-names = "isp", "mi", "mipi";
1255 clock-names = "isp", "aclk", "hclk", "pclk";
1258 phy-names = "dphy";
1259 power-domains = <&power PX30_PD_VI>;
1263 #address-cells = <1>;
1264 #size-cells = <0>;
1277 clock-names = "aclk", "iface";
1278 power-domains = <&power PX30_PD_VI>;
1279 rockchip,disable-mmu-reset;
1280 #iommu-cells = <0>;
1284 compatible = "rockchip,px30-qos", "syscon";
1289 compatible = "rockchip,px30-qos", "syscon";
1294 compatible = "rockchip,px30-qos", "syscon";
1299 compatible = "rockchip,px30-qos", "syscon";
1304 compatible = "rockchip,px30-qos", "syscon";
1309 compatible = "rockchip,px30-qos", "syscon";
1314 compatible = "rockchip,px30-qos", "syscon";
1319 compatible = "rockchip,px30-qos", "syscon";
1324 compatible = "rockchip,px30-qos", "syscon";
1329 compatible = "rockchip,px30-qos", "syscon";
1334 compatible = "rockchip,px30-qos", "syscon";
1339 compatible = "rockchip,px30-qos", "syscon";
1344 compatible = "rockchip,px30-qos", "syscon";
1349 compatible = "rockchip,px30-qos", "syscon";
1354 compatible = "rockchip,px30-qos", "syscon";
1359 compatible = "rockchip,px30-qos", "syscon";
1364 compatible = "rockchip,px30-qos", "syscon";
1369 compatible = "rockchip,px30-qos", "syscon";
1374 compatible = "rockchip,px30-qos", "syscon";
1379 compatible = "rockchip,px30-qos", "syscon";
1384 compatible = "rockchip,px30-pinctrl";
1387 #address-cells = <2>;
1388 #size-cells = <2>;
1392 compatible = "rockchip,gpio-bank";
1396 gpio-controller;
1397 #gpio-cells = <2>;
1399 interrupt-controller;
1400 #interrupt-cells = <2>;
1404 compatible = "rockchip,gpio-bank";
1408 gpio-controller;
1409 #gpio-cells = <2>;
1411 interrupt-controller;
1412 #interrupt-cells = <2>;
1416 compatible = "rockchip,gpio-bank";
1420 gpio-controller;
1421 #gpio-cells = <2>;
1423 interrupt-controller;
1424 #interrupt-cells = <2>;
1428 compatible = "rockchip,gpio-bank";
1432 gpio-controller;
1433 #gpio-cells = <2>;
1435 interrupt-controller;
1436 #interrupt-cells = <2>;
1439 pcfg_pull_up: pcfg-pull-up {
1440 bias-pull-up;
1443 pcfg_pull_down: pcfg-pull-down {
1444 bias-pull-down;
1447 pcfg_pull_none: pcfg-pull-none {
1448 bias-disable;
1451 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1452 bias-disable;
1453 drive-strength = <2>;
1456 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1457 bias-pull-up;
1458 drive-strength = <2>;
1461 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1462 bias-pull-up;
1463 drive-strength = <4>;
1466 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1467 bias-disable;
1468 drive-strength = <4>;
1471 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1472 bias-pull-down;
1473 drive-strength = <4>;
1476 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1477 bias-disable;
1478 drive-strength = <8>;
1481 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1482 bias-pull-up;
1483 drive-strength = <8>;
1486 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1487 bias-disable;
1488 drive-strength = <12>;
1491 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1492 bias-pull-up;
1493 drive-strength = <12>;
1496 pcfg_pull_none_smt: pcfg-pull-none-smt {
1497 bias-disable;
1498 input-schmitt-enable;
1501 pcfg_output_high: pcfg-output-high {
1502 output-high;
1505 pcfg_output_low: pcfg-output-low {
1506 output-low;
1509 pcfg_input_high: pcfg-input-high {
1510 bias-pull-up;
1511 input-enable;
1514 pcfg_input: pcfg-input {
1515 input-enable;
1519 i2c0_xfer: i2c0-xfer {
1520 rockchip,pins =
1527 i2c1_xfer: i2c1-xfer {
1528 rockchip,pins =
1535 i2c2_xfer: i2c2-xfer {
1536 rockchip,pins =
1543 i2c3_xfer: i2c3-xfer {
1544 rockchip,pins =
1551 tsadc_otp_pin: tsadc-otp-pin {
1552 rockchip,pins =
1556 tsadc_otp_out: tsadc-otp-out {
1557 rockchip,pins =
1563 uart0_xfer: uart0-xfer {
1564 rockchip,pins =
1569 uart0_cts: uart0-cts {
1570 rockchip,pins =
1574 uart0_rts: uart0-rts {
1575 rockchip,pins =
1581 uart1_xfer: uart1-xfer {
1582 rockchip,pins =
1587 uart1_cts: uart1-cts {
1588 rockchip,pins =
1592 uart1_rts: uart1-rts {
1593 rockchip,pins =
1598 uart2-m0 {
1599 uart2m0_xfer: uart2m0-xfer {
1600 rockchip,pins =
1606 uart2-m1 {
1607 uart2m1_xfer: uart2m1-xfer {
1608 rockchip,pins =
1614 uart3-m0 {
1615 uart3m0_xfer: uart3m0-xfer {
1616 rockchip,pins =
1621 uart3m0_cts: uart3m0-cts {
1622 rockchip,pins =
1626 uart3m0_rts: uart3m0-rts {
1627 rockchip,pins =
1632 uart3-m1 {
1633 uart3m1_xfer: uart3m1-xfer {
1634 rockchip,pins =
1639 uart3m1_cts: uart3m1-cts {
1640 rockchip,pins =
1644 uart3m1_rts: uart3m1-rts {
1645 rockchip,pins =
1651 uart4_xfer: uart4-xfer {
1652 rockchip,pins =
1657 uart4_cts: uart4-cts {
1658 rockchip,pins =
1662 uart4_rts: uart4-rts {
1663 rockchip,pins =
1669 uart5_xfer: uart5-xfer {
1670 rockchip,pins =
1675 uart5_cts: uart5-cts {
1676 rockchip,pins =
1680 uart5_rts: uart5-rts {
1681 rockchip,pins =
1687 spi0_clk: spi0-clk {
1688 rockchip,pins =
1692 spi0_csn: spi0-csn {
1693 rockchip,pins =
1697 spi0_miso: spi0-miso {
1698 rockchip,pins =
1702 spi0_mosi: spi0-mosi {
1703 rockchip,pins =
1707 spi0_clk_hs: spi0-clk-hs {
1708 rockchip,pins =
1712 spi0_miso_hs: spi0-miso-hs {
1713 rockchip,pins =
1717 spi0_mosi_hs: spi0-mosi-hs {
1718 rockchip,pins =
1723 spi1 {
1724 spi1_clk: spi1-clk {
1725 rockchip,pins =
1729 spi1_csn0: spi1-csn0 {
1730 rockchip,pins =
1734 spi1_csn1: spi1-csn1 {
1735 rockchip,pins =
1739 spi1_miso: spi1-miso {
1740 rockchip,pins =
1744 spi1_mosi: spi1-mosi {
1745 rockchip,pins =
1749 spi1_clk_hs: spi1-clk-hs {
1750 rockchip,pins =
1754 spi1_miso_hs: spi1-miso-hs {
1755 rockchip,pins =
1759 spi1_mosi_hs: spi1-mosi-hs {
1760 rockchip,pins =
1766 pdm_clk0m0: pdm-clk0m0 {
1767 rockchip,pins =
1771 pdm_clk0m1: pdm-clk0m1 {
1772 rockchip,pins =
1776 pdm_clk1: pdm-clk1 {
1777 rockchip,pins =
1781 pdm_sdi0m0: pdm-sdi0m0 {
1782 rockchip,pins =
1786 pdm_sdi0m1: pdm-sdi0m1 {
1787 rockchip,pins =
1791 pdm_sdi1: pdm-sdi1 {
1792 rockchip,pins =
1796 pdm_sdi2: pdm-sdi2 {
1797 rockchip,pins =
1801 pdm_sdi3: pdm-sdi3 {
1802 rockchip,pins =
1806 pdm_clk0m0_sleep: pdm-clk0m0-sleep {
1807 rockchip,pins =
1811 pdm_clk0m_sleep1: pdm-clk0m1-sleep {
1812 rockchip,pins =
1816 pdm_clk1_sleep: pdm-clk1-sleep {
1817 rockchip,pins =
1821 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
1822 rockchip,pins =
1826 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
1827 rockchip,pins =
1831 pdm_sdi1_sleep: pdm-sdi1-sleep {
1832 rockchip,pins =
1836 pdm_sdi2_sleep: pdm-sdi2-sleep {
1837 rockchip,pins =
1841 pdm_sdi3_sleep: pdm-sdi3-sleep {
1842 rockchip,pins =
1848 i2s0_8ch_mclk: i2s0-8ch-mclk {
1849 rockchip,pins =
1853 i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1854 rockchip,pins =
1858 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1859 rockchip,pins =
1863 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1864 rockchip,pins =
1868 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1869 rockchip,pins =
1873 i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1874 rockchip,pins =
1878 i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1879 rockchip,pins =
1883 i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1884 rockchip,pins =
1888 i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1889 rockchip,pins =
1893 i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1894 rockchip,pins =
1898 i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1899 rockchip,pins =
1903 i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1904 rockchip,pins =
1908 i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1909 rockchip,pins =
1915 i2s1_2ch_mclk: i2s1-2ch-mclk {
1916 rockchip,pins =
1920 i2s1_2ch_sclk: i2s1-2ch-sclk {
1921 rockchip,pins =
1925 i2s1_2ch_lrck: i2s1-2ch-lrck {
1926 rockchip,pins =
1930 i2s1_2ch_sdi: i2s1-2ch-sdi {
1931 rockchip,pins =
1935 i2s1_2ch_sdo: i2s1-2ch-sdo {
1936 rockchip,pins =
1942 i2s2_2ch_mclk: i2s2-2ch-mclk {
1943 rockchip,pins =
1947 i2s2_2ch_sclk: i2s2-2ch-sclk {
1948 rockchip,pins =
1952 i2s2_2ch_lrck: i2s2-2ch-lrck {
1953 rockchip,pins =
1957 i2s2_2ch_sdi: i2s2-2ch-sdi {
1958 rockchip,pins =
1962 i2s2_2ch_sdo: i2s2-2ch-sdo {
1963 rockchip,pins =
1969 sdmmc_clk: sdmmc-clk {
1970 rockchip,pins =
1974 sdmmc_cmd: sdmmc-cmd {
1975 rockchip,pins =
1979 sdmmc_det: sdmmc-det {
1980 rockchip,pins =
1984 sdmmc_bus1: sdmmc-bus1 {
1985 rockchip,pins =
1989 sdmmc_bus4: sdmmc-bus4 {
1990 rockchip,pins =
1999 sdio_clk: sdio-clk {
2000 rockchip,pins =
2004 sdio_cmd: sdio-cmd {
2005 rockchip,pins =
2009 sdio_bus4: sdio-bus4 {
2010 rockchip,pins =
2019 emmc_clk: emmc-clk {
2020 rockchip,pins =
2024 emmc_cmd: emmc-cmd {
2025 rockchip,pins =
2029 emmc_rstnout: emmc-rstnout {
2030 rockchip,pins =
2034 emmc_bus1: emmc-bus1 {
2035 rockchip,pins =
2039 emmc_bus4: emmc-bus4 {
2040 rockchip,pins =
2047 emmc_bus8: emmc-bus8 {
2048 rockchip,pins =
2061 flash_cs0: flash-cs0 {
2062 rockchip,pins =
2066 flash_rdy: flash-rdy {
2067 rockchip,pins =
2071 flash_dqs: flash-dqs {
2072 rockchip,pins =
2076 flash_ale: flash-ale {
2077 rockchip,pins =
2081 flash_cle: flash-cle {
2082 rockchip,pins =
2086 flash_wrn: flash-wrn {
2087 rockchip,pins =
2091 flash_csl: flash-csl {
2092 rockchip,pins =
2096 flash_rdn: flash-rdn {
2097 rockchip,pins =
2101 flash_bus8: flash-bus8 {
2102 rockchip,pins =
2115 sfc_bus4: sfc-bus4 {
2116 rockchip,pins =
2123 sfc_bus2: sfc-bus2 {
2124 rockchip,pins =
2129 sfc_cs0: sfc-cs0 {
2130 rockchip,pins =
2134 sfc_clk: sfc-clk {
2135 rockchip,pins =
2141 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
2142 rockchip,pins =
2146 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
2147 rockchip,pins =
2151 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
2152 rockchip,pins =
2156 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
2157 rockchip,pins =
2161 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
2162 rockchip,pins =
2189 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
2190 rockchip,pins =
2211 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
2212 rockchip,pins =
2231 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
2232 rockchip,pins =
2252 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
2253 rockchip,pins =
2267 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
2268 rockchip,pins =
2282 pwm0_pin: pwm0-pin {
2283 rockchip,pins =
2289 pwm1_pin: pwm1-pin {
2290 rockchip,pins =
2296 pwm2_pin: pwm2-pin {
2297 rockchip,pins =
2303 pwm3_pin: pwm3-pin {
2304 rockchip,pins =
2310 pwm4_pin: pwm4-pin {
2311 rockchip,pins =
2317 pwm5_pin: pwm5-pin {
2318 rockchip,pins =
2324 pwm6_pin: pwm6-pin {
2325 rockchip,pins =
2331 pwm7_pin: pwm7-pin {
2332 rockchip,pins =
2338 rmii_pins: rmii-pins {
2339 rockchip,pins =
2351 mac_refclk_12ma: mac-refclk-12ma {
2352 rockchip,pins =
2356 mac_refclk: mac-refclk {
2357 rockchip,pins =
2362 cif-m0 {
2363 cif_clkout_m0: cif-clkout-m0 {
2364 rockchip,pins =
2368 dvp_d2d9_m0: dvp-d2d9-m0 {
2369 rockchip,pins =
2384 dvp_d0d1_m0: dvp-d0d1-m0 {
2385 rockchip,pins =
2390 dvp_d10d11_m0:d10-d11-m0 {
2391 rockchip,pins =
2397 cif-m1 {
2398 cif_clkout_m1: cif-clkout-m1 {
2399 rockchip,pins =
2403 dvp_d2d9_m1: dvp-d2d9-m1 {
2404 rockchip,pins =
2419 dvp_d0d1_m1: dvp-d0d1-m1 {
2420 rockchip,pins =
2425 dvp_d10d11_m1:d10-d11-m1 {
2426 rockchip,pins =
2433 isp_prelight: isp-prelight {
2434 rockchip,pins =