Lines Matching +full:0 +full:xff2bc000
39 #size-cells = <0>;
41 cpu0: cpu@0 {
44 reg = <0x0 0x0>;
56 reg = <0x0 0x1>;
68 reg = <0x0 0x2>;
80 reg = <0x0 0x3>;
95 arm,psci-suspend-param = <0x0010000>;
104 arm,psci-suspend-param = <0x1010000>;
112 cpu0_opp_table: opp-table-0 {
163 #clock-cells = <0>;
184 thermal-sensors = <&tsadc 0>;
187 threshold: trip-point-0 {
251 #clock-cells = <0>;
258 reg = <0x0 0xff000000 0x0 0x1000>;
264 #size-cells = <0>;
273 #power-domain-cells = <0>;
280 #power-domain-cells = <0>;
289 #power-domain-cells = <0>;
303 #power-domain-cells = <0>;
311 #power-domain-cells = <0>;
328 #power-domain-cells = <0>;
340 #power-domain-cells = <0>;
346 #power-domain-cells = <0>;
353 reg = <0x0 0xff010000 0x0 0x1000>;
362 offset = <0x200>;
373 reg = <0x0 0xff030000 0x0 0x100>;
377 dmas = <&dmac 0>, <&dmac 1>;
382 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
388 reg = <0x0 0xff060000 0x0 0x1000>;
398 pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx
404 #sound-dai-cells = <0>;
410 reg = <0x0 0xff070000 0x0 0x1000>;
417 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
419 #sound-dai-cells = <0>;
425 reg = <0x0 0xff080000 0x0 0x1000>;
432 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
434 #sound-dai-cells = <0>;
441 #address-cells = <0>;
443 reg = <0x0 0xff131000 0 0x1000>,
444 <0x0 0xff132000 0 0x2000>,
445 <0x0 0xff134000 0 0x2000>,
446 <0x0 0xff136000 0 0x2000>;
453 reg = <0x0 0xff140000 0x0 0x1000>;
470 #size-cells = <0>;
472 lvds_in: port@0 {
473 reg = <0>;
475 #size-cells = <0>;
477 lvds_vopb_in: endpoint@0 {
478 reg = <0>;
497 reg = <0x0 0xff158000 0x0 0x100>;
506 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
512 reg = <0x0 0xff160000 0x0 0x100>;
521 pinctrl-0 = <&uart2m0_xfer>;
527 reg = <0x0 0xff168000 0x0 0x100>;
536 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
542 reg = <0x0 0xff170000 0x0 0x100>;
551 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
557 reg = <0x0 0xff178000 0x0 0x100>;
566 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
572 reg = <0x0 0xff180000 0x0 0x1000>;
577 pinctrl-0 = <&i2c0_xfer>;
579 #size-cells = <0>;
585 reg = <0x0 0xff190000 0x0 0x1000>;
590 pinctrl-0 = <&i2c1_xfer>;
592 #size-cells = <0>;
598 reg = <0x0 0xff1a0000 0x0 0x1000>;
603 pinctrl-0 = <&i2c2_xfer>;
605 #size-cells = <0>;
611 reg = <0x0 0xff1b0000 0x0 0x1000>;
616 pinctrl-0 = <&i2c3_xfer>;
618 #size-cells = <0>;
624 reg = <0x0 0xff1d0000 0x0 0x1000>;
632 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
634 #size-cells = <0>;
640 reg = <0x0 0xff1d8000 0x0 0x1000>;
648 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
650 #size-cells = <0>;
656 reg = <0x0 0xff1e0000 0x0 0x100>;
664 reg = <0x0 0xff200000 0x0 0x10>;
668 pinctrl-0 = <&pwm0_pin>;
675 reg = <0x0 0xff200010 0x0 0x10>;
679 pinctrl-0 = <&pwm1_pin>;
686 reg = <0x0 0xff200020 0x0 0x10>;
690 pinctrl-0 = <&pwm2_pin>;
697 reg = <0x0 0xff200030 0x0 0x10>;
701 pinctrl-0 = <&pwm3_pin>;
708 reg = <0x0 0xff208000 0x0 0x10>;
712 pinctrl-0 = <&pwm4_pin>;
719 reg = <0x0 0xff208010 0x0 0x10>;
723 pinctrl-0 = <&pwm5_pin>;
730 reg = <0x0 0xff208020 0x0 0x10>;
734 pinctrl-0 = <&pwm6_pin>;
741 reg = <0x0 0xff208030 0x0 0x10>;
745 pinctrl-0 = <&pwm7_pin>;
752 reg = <0x0 0xff210000 0x0 0x1000>;
760 reg = <0x0 0xff240000 0x0 0x4000>;
771 reg = <0x0 0xff280000 0x0 0x100>;
782 pinctrl-0 = <&tsadc_otp_pin>;
791 reg = <0x0 0xff288000 0x0 0x100>;
803 reg = <0x0 0xff290000 0x0 0x4000>;
814 reg = <0x07 0x10>;
817 reg = <0x17 0x1>;
820 reg = <0x1e 0x1>;
827 reg = <0x0 0xff2b0000 0x0 0x1000>;
847 reg = <0x0 0xff2bc000 0x0 0x1000>;
865 reg = <0x0 0xff2c0000 0x0 0x10000>;
871 reg = <0x100 0x20>;
874 #clock-cells = <0>;
881 #phy-cells = <0>;
888 #phy-cells = <0>;
901 reg = <0x0 0xff2e0000 0x0 0x10000>;
906 #phy-cells = <0>;
913 reg = <0x0 0xff2f0000 0x0 0x4000>;
916 #phy-cells = <0>;
927 reg = <0x0 0xff300000 0x0 0x40000>;
943 reg = <0x0 0xff340000 0x0 0x10000>;
954 reg = <0x0 0xff350000 0x0 0x10000>;
965 reg = <0x0 0xff360000 0x0 0x10000>;
979 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
988 #size-cells = <0>;
994 reg = <0x0 0xff370000 0x0 0x4000>;
1000 fifo-depth = <0x100>;
1003 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1010 reg = <0x0 0xff380000 0x0 0x4000>;
1016 fifo-depth = <0x100>;
1019 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
1026 reg = <0x0 0xff390000 0x0 0x4000>;
1032 fifo-depth = <0x100>;
1035 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
1042 reg = <0x0 0xff3a0000 0x0 0x4000>;
1046 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
1054 reg = <0x0 0xff3b0000 0x0 0x4000>;
1061 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
1090 reg = <0x0 0xff400000 0x0 0x4000>;
1104 reg = <0x0 0xff442000 0x0 0x800>;
1116 reg = <0x0 0xff442800 0x0 0x100>;
1120 #iommu-cells = <0>;
1126 reg = <0x0 0xff450000 0x0 0x10000>;
1140 #size-cells = <0>;
1142 dsi_in: port@0 {
1143 reg = <0>;
1145 #size-cells = <0>;
1147 dsi_in_vopb: endpoint@0 {
1148 reg = <0>;
1166 reg = <0x0 0xff460000 0x0 0xefc>;
1179 #size-cells = <0>;
1181 vopb_out_dsi: endpoint@0 {
1182 reg = <0>;
1195 reg = <0x0 0xff460f00 0x0 0x100>;
1200 #iommu-cells = <0>;
1206 reg = <0x0 0xff470000 0x0 0xefc>;
1219 #size-cells = <0>;
1221 vopl_out_dsi: endpoint@0 {
1222 reg = <0>;
1235 reg = <0x0 0xff470f00 0x0 0x100>;
1240 #iommu-cells = <0>;
1246 reg = <0x0 0xff4a0000 0x0 0x8000>;
1264 #size-cells = <0>;
1266 isp_in: port@0 {
1267 reg = <0>;
1274 reg = <0x0 0xff4a8000 0x0 0x100>;
1280 #iommu-cells = <0>;
1285 reg = <0x0 0xff518000 0x0 0x20>;
1290 reg = <0x0 0xff520000 0x0 0x20>;
1295 reg = <0x0 0xff52c000 0x0 0x20>;
1300 reg = <0x0 0xff538000 0x0 0x20>;
1305 reg = <0x0 0xff538080 0x0 0x20>;
1310 reg = <0x0 0xff538100 0x0 0x20>;
1315 reg = <0x0 0xff538180 0x0 0x20>;
1320 reg = <0x0 0xff540000 0x0 0x20>;
1325 reg = <0x0 0xff540080 0x0 0x20>;
1330 reg = <0x0 0xff548000 0x0 0x20>;
1335 reg = <0x0 0xff548080 0x0 0x20>;
1340 reg = <0x0 0xff548100 0x0 0x20>;
1345 reg = <0x0 0xff548180 0x0 0x20>;
1350 reg = <0x0 0xff548200 0x0 0x20>;
1355 reg = <0x0 0xff550000 0x0 0x20>;
1360 reg = <0x0 0xff550080 0x0 0x20>;
1365 reg = <0x0 0xff550100 0x0 0x20>;
1370 reg = <0x0 0xff550180 0x0 0x20>;
1375 reg = <0x0 0xff558000 0x0 0x20>;
1380 reg = <0x0 0xff558080 0x0 0x20>;
1393 reg = <0x0 0xff040000 0x0 0x100>;
1405 reg = <0x0 0xff250000 0x0 0x100>;
1417 reg = <0x0 0xff260000 0x0 0x100>;
1429 reg = <0x0 0xff270000 0x0 0x100>;
1521 <0 RK_PB0 1 &pcfg_pull_none_smt>,
1522 <0 RK_PB1 1 &pcfg_pull_none_smt>;
1529 <0 RK_PC2 1 &pcfg_pull_none_smt>,
1530 <0 RK_PC3 1 &pcfg_pull_none_smt>;
1553 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1558 <0 RK_PA6 1 &pcfg_pull_none>;
1565 <0 RK_PB2 1 &pcfg_pull_up>,
1566 <0 RK_PB3 1 &pcfg_pull_up>;
1571 <0 RK_PB4 1 &pcfg_pull_none>;
1576 <0 RK_PB5 1 &pcfg_pull_none>;
1617 <0 RK_PC0 2 &pcfg_pull_up>,
1618 <0 RK_PC1 2 &pcfg_pull_up>;
1623 <0 RK_PC2 2 &pcfg_pull_none>;
1628 <0 RK_PC3 2 &pcfg_pull_none>;
1981 <0 RK_PA3 1 &pcfg_pull_up_8ma>;
2284 <0 RK_PB7 1 &pcfg_pull_none>;
2291 <0 RK_PC0 1 &pcfg_pull_none>;
2305 <0 RK_PC1 1 &pcfg_pull_none>;