Lines Matching +full:0 +full:xff160000
39 #size-cells = <0>;
41 cpu0: cpu@0 {
44 reg = <0x0 0x0>;
56 reg = <0x0 0x1>;
68 reg = <0x0 0x2>;
80 reg = <0x0 0x3>;
95 arm,psci-suspend-param = <0x0010000>;
104 arm,psci-suspend-param = <0x1010000>;
112 cpu0_opp_table: opp-table-0 {
163 #clock-cells = <0>;
184 thermal-sensors = <&tsadc 0>;
187 threshold: trip-point-0 {
251 #clock-cells = <0>;
258 reg = <0x0 0xff000000 0x0 0x1000>;
264 #size-cells = <0>;
273 #power-domain-cells = <0>;
280 #power-domain-cells = <0>;
289 #power-domain-cells = <0>;
303 #power-domain-cells = <0>;
311 #power-domain-cells = <0>;
328 #power-domain-cells = <0>;
340 #power-domain-cells = <0>;
346 #power-domain-cells = <0>;
353 reg = <0x0 0xff010000 0x0 0x1000>;
364 offset = <0x200>;
375 reg = <0x0 0xff030000 0x0 0x100>;
379 dmas = <&dmac 0>, <&dmac 1>;
384 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
390 reg = <0x0 0xff060000 0x0 0x1000>;
400 pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx
406 #sound-dai-cells = <0>;
412 reg = <0x0 0xff070000 0x0 0x1000>;
419 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
421 #sound-dai-cells = <0>;
427 reg = <0x0 0xff080000 0x0 0x1000>;
434 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
436 #sound-dai-cells = <0>;
443 #address-cells = <0>;
445 reg = <0x0 0xff131000 0 0x1000>,
446 <0x0 0xff132000 0 0x2000>,
447 <0x0 0xff134000 0 0x2000>,
448 <0x0 0xff136000 0 0x2000>;
455 reg = <0x0 0xff140000 0x0 0x1000>;
474 #size-cells = <0>;
476 lvds_in: port@0 {
477 reg = <0>;
479 #size-cells = <0>;
481 lvds_vopb_in: endpoint@0 {
482 reg = <0>;
501 reg = <0x0 0xff158000 0x0 0x100>;
510 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
516 reg = <0x0 0xff160000 0x0 0x100>;
525 pinctrl-0 = <&uart2m0_xfer>;
531 reg = <0x0 0xff168000 0x0 0x100>;
540 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
546 reg = <0x0 0xff170000 0x0 0x100>;
555 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
561 reg = <0x0 0xff178000 0x0 0x100>;
570 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
576 reg = <0x0 0xff180000 0x0 0x1000>;
581 pinctrl-0 = <&i2c0_xfer>;
583 #size-cells = <0>;
589 reg = <0x0 0xff190000 0x0 0x1000>;
594 pinctrl-0 = <&i2c1_xfer>;
596 #size-cells = <0>;
602 reg = <0x0 0xff1a0000 0x0 0x1000>;
607 pinctrl-0 = <&i2c2_xfer>;
609 #size-cells = <0>;
615 reg = <0x0 0xff1b0000 0x0 0x1000>;
620 pinctrl-0 = <&i2c3_xfer>;
622 #size-cells = <0>;
628 reg = <0x0 0xff1d0000 0x0 0x1000>;
636 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
638 #size-cells = <0>;
644 reg = <0x0 0xff1d8000 0x0 0x1000>;
652 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
654 #size-cells = <0>;
660 reg = <0x0 0xff1e0000 0x0 0x100>;
668 reg = <0x0 0xff200000 0x0 0x10>;
672 pinctrl-0 = <&pwm0_pin>;
679 reg = <0x0 0xff200010 0x0 0x10>;
683 pinctrl-0 = <&pwm1_pin>;
690 reg = <0x0 0xff200020 0x0 0x10>;
694 pinctrl-0 = <&pwm2_pin>;
701 reg = <0x0 0xff200030 0x0 0x10>;
705 pinctrl-0 = <&pwm3_pin>;
712 reg = <0x0 0xff208000 0x0 0x10>;
716 pinctrl-0 = <&pwm4_pin>;
723 reg = <0x0 0xff208010 0x0 0x10>;
727 pinctrl-0 = <&pwm5_pin>;
734 reg = <0x0 0xff208020 0x0 0x10>;
738 pinctrl-0 = <&pwm6_pin>;
745 reg = <0x0 0xff208030 0x0 0x10>;
749 pinctrl-0 = <&pwm7_pin>;
756 reg = <0x0 0xff210000 0x0 0x1000>;
764 reg = <0x0 0xff240000 0x0 0x4000>;
775 reg = <0x0 0xff280000 0x0 0x100>;
786 pinctrl-0 = <&tsadc_otp_pin>;
795 reg = <0x0 0xff288000 0x0 0x100>;
807 reg = <0x0 0xff290000 0x0 0x4000>;
818 reg = <0x07 0x10>;
821 reg = <0x17 0x1>;
824 reg = <0x1e 0x1>;
831 reg = <0x0 0xff2b0000 0x0 0x1000>;
851 reg = <0x0 0xff2bc000 0x0 0x1000>;
869 reg = <0x0 0xff2c0000 0x0 0x10000>;
875 reg = <0x100 0x20>;
878 #clock-cells = <0>;
885 #phy-cells = <0>;
892 #phy-cells = <0>;
905 reg = <0x0 0xff2e0000 0x0 0x10000>;
910 #phy-cells = <0>;
917 reg = <0x0 0xff2f0000 0x0 0x4000>;
920 #phy-cells = <0>;
931 reg = <0x0 0xff300000 0x0 0x40000>;
947 reg = <0x0 0xff340000 0x0 0x10000>;
958 reg = <0x0 0xff350000 0x0 0x10000>;
969 reg = <0x0 0xff360000 0x0 0x10000>;
983 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
992 reg = <0x0 0xff370000 0x0 0x4000>;
998 fifo-depth = <0x100>;
1001 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1008 reg = <0x0 0xff380000 0x0 0x4000>;
1014 fifo-depth = <0x100>;
1017 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
1024 reg = <0x0 0xff390000 0x0 0x4000>;
1030 fifo-depth = <0x100>;
1033 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
1040 reg = <0x0 0xff3a0000 0x0 0x4000>;
1044 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
1052 reg = <0x0 0xff3b0000 0x0 0x4000>;
1059 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
1088 reg = <0x0 0xff400000 0x0 0x4000>;
1102 reg = <0x0 0xff442000 0x0 0x800>;
1114 reg = <0x0 0xff442800 0x0 0x100>;
1118 #iommu-cells = <0>;
1124 reg = <0x0 0xff450000 0x0 0x10000>;
1135 #size-cells = <0>;
1140 #size-cells = <0>;
1142 dsi_in: port@0 {
1143 reg = <0>;
1145 #size-cells = <0>;
1147 dsi_in_vopb: endpoint@0 {
1148 reg = <0>;
1166 reg = <0x0 0xff460000 0x0 0xefc>;
1179 #size-cells = <0>;
1181 vopb_out_dsi: endpoint@0 {
1182 reg = <0>;
1195 reg = <0x0 0xff460f00 0x0 0x100>;
1200 #iommu-cells = <0>;
1206 reg = <0x0 0xff470000 0x0 0xefc>;
1219 #size-cells = <0>;
1221 vopl_out_dsi: endpoint@0 {
1222 reg = <0>;
1235 reg = <0x0 0xff470f00 0x0 0x100>;
1240 #iommu-cells = <0>;
1246 reg = <0x0 0xff4a0000 0x0 0x8000>;
1264 #size-cells = <0>;
1266 port@0 {
1267 reg = <0>;
1269 #size-cells = <0>;
1276 reg = <0x0 0xff4a8000 0x0 0x100>;
1282 #iommu-cells = <0>;
1287 reg = <0x0 0xff518000 0x0 0x20>;
1292 reg = <0x0 0xff520000 0x0 0x20>;
1297 reg = <0x0 0xff52c000 0x0 0x20>;
1302 reg = <0x0 0xff538000 0x0 0x20>;
1307 reg = <0x0 0xff538080 0x0 0x20>;
1312 reg = <0x0 0xff538100 0x0 0x20>;
1317 reg = <0x0 0xff538180 0x0 0x20>;
1322 reg = <0x0 0xff540000 0x0 0x20>;
1327 reg = <0x0 0xff540080 0x0 0x20>;
1332 reg = <0x0 0xff548000 0x0 0x20>;
1337 reg = <0x0 0xff548080 0x0 0x20>;
1342 reg = <0x0 0xff548100 0x0 0x20>;
1347 reg = <0x0 0xff548180 0x0 0x20>;
1352 reg = <0x0 0xff548200 0x0 0x20>;
1357 reg = <0x0 0xff550000 0x0 0x20>;
1362 reg = <0x0 0xff550080 0x0 0x20>;
1367 reg = <0x0 0xff550100 0x0 0x20>;
1372 reg = <0x0 0xff550180 0x0 0x20>;
1377 reg = <0x0 0xff558000 0x0 0x20>;
1382 reg = <0x0 0xff558080 0x0 0x20>;
1395 reg = <0x0 0xff040000 0x0 0x100>;
1407 reg = <0x0 0xff250000 0x0 0x100>;
1419 reg = <0x0 0xff260000 0x0 0x100>;
1431 reg = <0x0 0xff270000 0x0 0x100>;
1523 <0 RK_PB0 1 &pcfg_pull_none_smt>,
1524 <0 RK_PB1 1 &pcfg_pull_none_smt>;
1531 <0 RK_PC2 1 &pcfg_pull_none_smt>,
1532 <0 RK_PC3 1 &pcfg_pull_none_smt>;
1555 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1560 <0 RK_PA6 1 &pcfg_pull_none>;
1567 <0 RK_PB2 1 &pcfg_pull_up>,
1568 <0 RK_PB3 1 &pcfg_pull_up>;
1573 <0 RK_PB4 1 &pcfg_pull_none>;
1578 <0 RK_PB5 1 &pcfg_pull_none>;
1619 <0 RK_PC0 2 &pcfg_pull_up>,
1620 <0 RK_PC1 2 &pcfg_pull_up>;
1625 <0 RK_PC2 2 &pcfg_pull_none>;
1630 <0 RK_PC3 2 &pcfg_pull_none>;
1983 <0 RK_PA3 1 &pcfg_pull_up_8ma>;
2286 <0 RK_PB7 1 &pcfg_pull_none>;
2293 <0 RK_PC0 1 &pcfg_pull_none>;
2307 <0 RK_PC1 1 &pcfg_pull_none>;