Lines Matching +full:mux +full:- +full:ssi0
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the R9A08G045S33 SMARC Carrier-II's SoM board.
8 #include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
12 #include "rzg3s-smarc-switches.h"
15 compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045";
35 compatible = "regulator-fixed";
36 regulator-name = "SDHI0 Vcc";
37 regulator-min-microvolt = <3300000>;
38 regulator-max-microvolt = <3300000>;
40 enable-active-high;
44 compatible = "regulator-gpio";
45 regulator-name = "SDHI0 VccQ";
46 regulator-min-microvolt = <1800000>;
47 regulator-max-microvolt = <3300000>;
49 gpios-states = <1>;
54 compatible = "regulator-fixed";
55 regulator-name = "fixed-1.8V";
56 regulator-min-microvolt = <1800000>;
57 regulator-max-microvolt = <1800000>;
58 regulator-boot-on;
59 regulator-always-on;
63 compatible = "regulator-fixed";
64 regulator-name = "fixed-3.3V";
65 regulator-min-microvolt = <3300000>;
66 regulator-max-microvolt = <3300000>;
67 regulator-boot-on;
68 regulator-always-on;
72 compatible = "regulator-fixed";
73 regulator-name = "SDHI2 Vcc";
74 regulator-min-microvolt = <3300000>;
75 regulator-max-microvolt = <3300000>;
77 enable-active-high;
80 x3_clk: x3-clock {
81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <24000000>;
93 pinctrl-0 = <ð0_pins>;
94 pinctrl-names = "default";
95 phy-handle = <&phy0>;
96 phy-mode = "rgmii-id";
99 phy0: ethernet-phy@7 {
101 interrupts-extended = <&pinctrl RZG2L_GPIO(12, 0) IRQ_TYPE_EDGE_FALLING>;
102 rxc-skew-psec = <0>;
103 txc-skew-psec = <0>;
104 rxdv-skew-psec = <0>;
105 txen-skew-psec = <0>;
106 rxd0-skew-psec = <0>;
107 rxd1-skew-psec = <0>;
108 rxd2-skew-psec = <0>;
109 rxd3-skew-psec = <0>;
110 txd0-skew-psec = <0>;
111 txd1-skew-psec = <0>;
112 txd2-skew-psec = <0>;
113 txd3-skew-psec = <0>;
118 pinctrl-0 = <ð1_pins>;
119 pinctrl-names = "default";
120 phy-handle = <&phy1>;
121 phy-mode = "rgmii-id";
124 phy1: ethernet-phy@7 {
126 interrupts-extended = <&pinctrl RZG2L_GPIO(12, 1) IRQ_TYPE_EDGE_FALLING>;
127 rxc-skew-psec = <0>;
128 txc-skew-psec = <0>;
129 rxdv-skew-psec = <0>;
130 txen-skew-psec = <0>;
131 rxd0-skew-psec = <0>;
132 rxd1-skew-psec = <0>;
133 rxd2-skew-psec = <0>;
134 rxd3-skew-psec = <0>;
135 txd0-skew-psec = <0>;
136 txd1-skew-psec = <0>;
137 txd2-skew-psec = <0>;
138 txd3-skew-psec = <0>;
144 clock-frequency = <24000000>;
150 versa3: clock-generator@68 {
154 #clock-cells = <1>;
155 assigned-clocks = <&versa3 0>,
161 assigned-clock-rates = <24000000>,
178 pinctrl-0 = <&sdhi0_pins>;
179 pinctrl-1 = <&sdhi0_uhs_pins>;
180 pinctrl-names = "default", "state_uhs";
181 vmmc-supply = <&vcc_sdhi0>;
182 vqmmc-supply = <&vccq_sdhi0>;
183 bus-width = <4>;
184 sd-uhs-sdr50;
185 sd-uhs-sdr104;
186 max-frequency = <125000000>;
192 pinctrl-0 = <&sdhi0_emmc_pins>;
193 pinctrl-1 = <&sdhi0_emmc_pins>;
194 pinctrl-names = "default", "state_uhs";
195 vmmc-supply = <&vcc_sdhi0>;
196 vqmmc-supply = <®_1p8v>;
197 bus-width = <8>;
198 mmc-hs200-1_8v;
199 non-removable;
200 fixed-emmc-driver-type = <1>;
201 max-frequency = <125000000>;
208 pinctrl-0 = <&sdhi2_pins>;
209 pinctrl-names = "default";
210 vmmc-supply = <&vcc_sdhi2>;
211 bus-width = <4>;
212 max-frequency = <50000000>;
219 eth0-phy-irq-hog {
220 gpio-hog;
223 line-name = "eth0-phy-irq";
230 power-source = <1800>;
231 output-enable;
232 input-enable;
233 drive-strength-microamp = <5200>;
238 power-source = <1800>;
239 output-enable;
240 drive-strength-microamp = <5200>;
243 mux {
257 power-source = <1800>;
262 eth1-phy-irq-hog {
263 gpio-hog;
266 line-name = "eth1-phy-irq";
273 power-source = <1800>;
274 output-enable;
275 input-enable;
276 drive-strength-microamp = <5200>;
281 power-source = <1800>;
282 output-enable;
283 drive-strength-microamp = <5200>;
286 mux {
300 power-source = <1800>;
307 power-source = <3300>;
312 power-source = <3300>;
320 sdhi0_uhs_pins: sd0-uhs {
323 power-source = <1800>;
328 power-source = <1800>;
336 sdhi0_emmc_pins: sd0-emmc {
340 power-source = <1800>;
346 input-enable;
351 input-enable;
354 mux {
371 assigned-clocks = <&vbattb VBATTB_MUX>;
372 assigned-clock-parents = <&vbattb VBATTB_XC>;
373 quartz-load-femtofarads = <12500>;
378 clock-frequency = <32768>;
382 timeout-sec = <60>;