Lines Matching +full:i2s +full:- +full:data +full:- +full:lanes
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
17 osc1: cec-clock {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
20 clock-frequency = <12000000>;
23 hdmi-out {
24 compatible = "hdmi-connector";
29 remote-endpoint = <&adv7535_out>;
35 compatible = "audio-graph-card";
36 label = "HDMI-Audio";
42 sound-dai = <&ssi0>;
51 data-lanes = <1 2 3 4>;
52 remote-endpoint = <&adv7535_in>;
67 interrupts-extended = <&pinctrl RZG2L_GPIO(2, 1) IRQ_TYPE_EDGE_FALLING>;
69 clock-names = "cec";
70 avdd-supply = <®_1p8v>;
71 dvdd-supply = <®_1p8v>;
72 pvdd-supply = <®_1p8v>;
73 a2vdd-supply = <®_1p8v>;
74 v3p3-supply = <®_3p3v>;
75 v1p2-supply = <®_1p8v>;
77 adi,dsi-lanes = <4>;
80 #address-cells = <1>;
81 #size-cells = <0>;
86 remote-endpoint = <&dsi0_out>;
93 remote-endpoint = <&hdmi_con_out>;
100 remote-endpoint = <&i2s2_cpu_endpoint>;
108 pinctrl-0 = <&i2c3_pins>;
109 pinctrl-names = "default";
110 clock-frequency = <400000>;
116 #sound-dai-cells = <0>;
120 versa3: clock-generator@68 {
123 #clock-cells = <1>;
132 assigned-clocks = <&versa3 0>, <&versa3 1>,
135 assigned-clock-rates = <24000000>, <11289600>,
143 pinctrl-0 = <&mtu3_pins>;
144 pinctrl-names = "default";
163 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
164 * SW2 should be at position 2->3 so that SER0_TX line is activated
165 * SW3 should be at position 2->3 so that SER0_RX line is activated
166 * SW4 should be at position 2->3 so that SER0_RTS# line is activated
170 pinctrl-0 = <&scif2_pins>;
171 pinctrl-names = "default";
173 uart-has-rtscts;
179 pinctrl-0 = <&ssi0_pins>;
180 pinctrl-names = "default";
186 pinctrl-0 = <&ssi1_pins>;
187 pinctrl-names = "default";
193 remote-endpoint = <&codec_endpoint>;
194 dai-format = "i2s";
196 bitclock-master = <&i2s2_cpu_endpoint>;
197 frame-master = <&i2s2_cpu_endpoint>;