Lines Matching +full:dcb +full:- +full:algorithm
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&gic>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a55";
25 next-level-cache = <&L3_CA55>;
26 enable-method = "psci";
30 compatible = "arm,cortex-a55";
33 next-level-cache = <&L3_CA55>;
34 enable-method = "psci";
38 compatible = "arm,cortex-a55";
41 next-level-cache = <&L3_CA55>;
42 enable-method = "psci";
46 compatible = "arm,cortex-a55";
49 next-level-cache = <&L3_CA55>;
50 enable-method = "psci";
53 L3_CA55: cache-controller-0 {
55 cache-unified;
56 cache-size = <0x100000>;
57 cache-level = <3>;
62 compatible = "fixed-clock";
63 #clock-cells = <0>;
65 clock-frequency = <0>;
69 compatible = "arm,cortex-a55-pmu";
74 compatible = "arm,psci-1.0", "arm,psci-0.2";
79 compatible = "simple-bus";
80 #address-cells = <2>;
81 #size-cells = <2>;
85 compatible = "renesas,r9a09g077-rsci";
91 interrupt-names = "eri", "rxi", "txi", "tei";
93 clock-names = "operation", "bus";
94 power-domains = <&cpg>;
99 compatible = "renesas,r9a09g077-rsci";
105 interrupt-names = "eri", "rxi", "txi", "tei";
107 clock-names = "operation", "bus";
108 power-domains = <&cpg>;
113 compatible = "renesas,r9a09g077-rsci";
119 interrupt-names = "eri", "rxi", "txi", "tei";
121 clock-names = "operation", "bus";
122 power-domains = <&cpg>;
127 compatible = "renesas,r9a09g077-rsci";
133 interrupt-names = "eri", "rxi", "txi", "tei";
135 clock-names = "operation", "bus";
136 power-domains = <&cpg>;
141 compatible = "renesas,r9a09g077-rsci";
147 interrupt-names = "eri", "rxi", "txi", "tei";
149 clock-names = "operation", "bus";
150 power-domains = <&cpg>;
155 compatible = "renesas,r9a09g077-rsci";
161 interrupt-names = "eri", "rxi", "txi", "tei";
163 clock-names = "operation", "bus";
164 power-domains = <&cpg>;
169 compatible = "renesas,r9a09g077-wdt";
173 clock-names = "pclk";
174 power-domains = <&cpg>;
179 compatible = "renesas,r9a09g077-wdt";
183 clock-names = "pclk";
184 power-domains = <&cpg>;
189 compatible = "renesas,r9a09g077-wdt";
193 clock-names = "pclk";
194 power-domains = <&cpg>;
199 compatible = "renesas,r9a09g077-wdt";
203 clock-names = "pclk";
204 power-domains = <&cpg>;
209 compatible = "renesas,r9a09g077-wdt";
213 clock-names = "pclk";
214 power-domains = <&cpg>;
219 compatible = "renesas,r9a09g077-wdt";
223 clock-names = "pclk";
224 power-domains = <&cpg>;
229 compatible = "renesas,riic-r9a09g077";
235 interrupt-names = "eei", "rxi", "txi", "tei";
237 power-domains = <&cpg>;
238 #address-cells = <1>;
239 #size-cells = <0>;
244 compatible = "renesas,riic-r9a09g077";
250 interrupt-names = "eei", "rxi", "txi", "tei";
252 power-domains = <&cpg>;
253 #address-cells = <1>;
254 #size-cells = <0>;
259 compatible = "renesas,riic-r9a09g077";
265 interrupt-names = "eei", "rxi", "txi", "tei";
267 power-domains = <&cpg>;
268 #address-cells = <1>;
269 #size-cells = <0>;
274 compatible = "renesas,r9a09g077-gbeth", "snps,dwmac-5.20";
295 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
296 "rx-queue-0", "rx-queue-1", "rx-queue-2",
297 "rx-queue-3", "rx-queue-4", "rx-queue-5",
298 "rx-queue-6", "rx-queue-7", "tx-queue-0",
299 "tx-queue-1", "tx-queue-2", "tx-queue-3",
300 "tx-queue-4", "tx-queue-5", "tx-queue-6",
301 "tx-queue-7";
305 clock-names = "stmmaceth", "pclk", "tx";
307 reset-names = "stmmaceth", "ahb";
308 power-domains = <&cpg>;
309 snps,multicast-filter-bins = <256>;
310 snps,perfect-filter-entries = <32>;
311 rx-fifo-depth = <8192>;
312 tx-fifo-depth = <8192>;
313 snps,fixed-burst;
314 snps,no-pbl-x8;
316 snps,axi-config = <&stmmac_axi_setup>;
317 snps,mtl-rx-config = <&mtl_rx_setup0>;
318 snps,mtl-tx-config = <&mtl_tx_setup0>;
324 compatible = "snps,dwmac-mdio";
325 #address-cells = <1>;
326 #size-cells = <0>;
329 mtl_rx_setup0: rx-queues-config {
330 snps,rx-queues-to-use = <8>;
331 snps,rx-sched-sp;
334 snps,dcb-algorithm;
336 snps,map-to-dma-channel = <0>;
340 snps,dcb-algorithm;
342 snps,map-to-dma-channel = <1>;
346 snps,dcb-algorithm;
348 snps,map-to-dma-channel = <2>;
352 snps,dcb-algorithm;
354 snps,map-to-dma-channel = <3>;
358 snps,dcb-algorithm;
360 snps,map-to-dma-channel = <4>;
364 snps,dcb-algorithm;
366 snps,map-to-dma-channel = <5>;
370 snps,dcb-algorithm;
372 snps,map-to-dma-channel = <6>;
376 snps,dcb-algorithm;
378 snps,map-to-dma-channel = <7>;
382 mtl_tx_setup0: tx-queues-config {
383 snps,tx-queues-to-use = <8>;
386 snps,dcb-algorithm;
390 snps,dcb-algorithm;
394 snps,dcb-algorithm;
398 snps,dcb-algorithm;
402 snps,dcb-algorithm;
406 snps,dcb-algorithm;
410 snps,dcb-algorithm;
414 snps,dcb-algorithm;
420 compatible = "renesas,r9a09g077-gbeth", "snps,dwmac-5.20";
441 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
442 "rx-queue-0", "rx-queue-1", "rx-queue-2",
443 "rx-queue-3", "rx-queue-4", "rx-queue-5",
444 "rx-queue-6", "rx-queue-7", "tx-queue-0",
445 "tx-queue-1", "tx-queue-2", "tx-queue-3",
446 "tx-queue-4", "tx-queue-5", "tx-queue-6",
447 "tx-queue-7";
451 clock-names = "stmmaceth", "pclk", "tx";
453 reset-names = "stmmaceth", "ahb";
454 power-domains = <&cpg>;
455 snps,multicast-filter-bins = <256>;
456 snps,perfect-filter-entries = <32>;
457 rx-fifo-depth = <8192>;
458 tx-fifo-depth = <8192>;
459 snps,fixed-burst;
460 snps,no-pbl-x8;
462 snps,axi-config = <&stmmac_axi_setup>;
463 snps,mtl-rx-config = <&mtl_rx_setup1>;
464 snps,mtl-tx-config = <&mtl_tx_setup1>;
470 compatible = "snps,dwmac-mdio";
471 #address-cells = <1>;
472 #size-cells = <0>;
475 mtl_rx_setup1: rx-queues-config {
476 snps,rx-queues-to-use = <8>;
477 snps,rx-sched-sp;
480 snps,dcb-algorithm;
482 snps,map-to-dma-channel = <0>;
486 snps,dcb-algorithm;
488 snps,map-to-dma-channel = <1>;
492 snps,dcb-algorithm;
494 snps,map-to-dma-channel = <2>;
498 snps,dcb-algorithm;
500 snps,map-to-dma-channel = <3>;
504 snps,dcb-algorithm;
506 snps,map-to-dma-channel = <4>;
510 snps,dcb-algorithm;
512 snps,map-to-dma-channel = <5>;
516 snps,dcb-algorithm;
518 snps,map-to-dma-channel = <6>;
522 snps,dcb-algorithm;
524 snps,map-to-dma-channel = <7>;
528 mtl_tx_setup1: tx-queues-config {
529 snps,tx-queues-to-use = <8>;
532 snps,dcb-algorithm;
536 snps,dcb-algorithm;
540 snps,dcb-algorithm;
544 snps,dcb-algorithm;
548 snps,dcb-algorithm;
552 snps,dcb-algorithm;
556 snps,dcb-algorithm;
560 snps,dcb-algorithm;
566 compatible = "renesas,r9a09g077-gbeth", "snps,dwmac-5.20";
587 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
588 "rx-queue-0", "rx-queue-1", "rx-queue-2",
589 "rx-queue-3", "rx-queue-4", "rx-queue-5",
590 "rx-queue-6", "rx-queue-7", "tx-queue-0",
591 "tx-queue-1", "tx-queue-2", "tx-queue-3",
592 "tx-queue-4", "tx-queue-5", "tx-queue-6",
593 "tx-queue-7";
597 clock-names = "stmmaceth", "pclk", "tx";
599 reset-names = "stmmaceth", "ahb";
600 power-domains = <&cpg>;
601 snps,multicast-filter-bins = <256>;
602 snps,perfect-filter-entries = <32>;
603 rx-fifo-depth = <8192>;
604 tx-fifo-depth = <8192>;
605 snps,fixed-burst;
606 snps,no-pbl-x8;
608 snps,axi-config = <&stmmac_axi_setup>;
609 snps,mtl-rx-config = <&mtl_rx_setup2>;
610 snps,mtl-tx-config = <&mtl_tx_setup2>;
616 compatible = "snps,dwmac-mdio";
617 #address-cells = <1>;
618 #size-cells = <0>;
621 mtl_rx_setup2: rx-queues-config {
622 snps,rx-queues-to-use = <8>;
623 snps,rx-sched-sp;
626 snps,dcb-algorithm;
628 snps,map-to-dma-channel = <0>;
632 snps,dcb-algorithm;
634 snps,map-to-dma-channel = <1>;
638 snps,dcb-algorithm;
640 snps,map-to-dma-channel = <2>;
644 snps,dcb-algorithm;
646 snps,map-to-dma-channel = <3>;
650 snps,dcb-algorithm;
652 snps,map-to-dma-channel = <4>;
656 snps,dcb-algorithm;
658 snps,map-to-dma-channel = <5>;
662 snps,dcb-algorithm;
664 snps,map-to-dma-channel = <6>;
668 snps,dcb-algorithm;
670 snps,map-to-dma-channel = <7>;
674 mtl_tx_setup2: tx-queues-config {
675 snps,tx-queues-to-use = <8>;
678 snps,dcb-algorithm;
682 snps,dcb-algorithm;
686 snps,dcb-algorithm;
690 snps,dcb-algorithm;
694 snps,dcb-algorithm;
698 snps,dcb-algorithm;
702 snps,dcb-algorithm;
706 snps,dcb-algorithm;
712 compatible = "renesas,r9a09g077-miic";
718 clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk";
720 reset-names = "rst", "crst";
721 power-domains = <&cpg>;
724 #address-cells = <1>;
725 #size-cells = <0>;
727 mii_conv0: mii-conv@0 {
732 mii_conv1: mii-conv@1 {
737 mii_conv2: mii-conv@2 {
742 mii_conv3: mii-conv@3 {
748 cpg: clock-controller@80280000 {
749 compatible = "renesas,r9a09g077-cpg-mssr";
753 clock-names = "extal";
754 #clock-cells = <2>;
755 #reset-cells = <1>;
756 #power-domain-cells = <0>;
760 compatible = "renesas,r9a09g077-pinctrl";
764 reg-names = "nsr", "srs", "srn";
766 gpio-controller;
767 #gpio-cells = <2>;
768 gpio-ranges = <&pinctrl 0 0 288>;
769 power-domains = <&cpg>;
772 gic: interrupt-controller@83000000 {
773 compatible = "arm,gic-v3";
776 #interrupt-cells = <3>;
777 #address-cells = <0>;
778 interrupt-controller;
783 compatible = "renesas,r9a09g077-adc";
792 interrupt-names = "adi", "gbadi", "gcadi",
796 clock-names = "adclk", "pclk";
797 power-domains = <&cpg>;
798 #address-cells = <1>;
799 #size-cells = <0>;
800 #io-channel-cells = <1>;
805 compatible = "renesas,r9a09g077-adc";
814 interrupt-names = "adi", "gbadi", "gcadi",
818 clock-names = "adclk", "pclk";
819 power-domains = <&cpg>;
820 #address-cells = <1>;
821 #size-cells = <0>;
822 #io-channel-cells = <1>;
827 compatible = "renesas,r9a09g077-adc";
836 interrupt-names = "adi", "gbadi", "gcadi",
840 clock-names = "adclk", "pclk";
841 power-domains = <&cpg>;
842 #address-cells = <1>;
843 #size-cells = <0>;
844 #io-channel-cells = <1>;
849 compatible = "generic-ohci";
854 phy-names = "usb";
855 power-domains = <&cpg>;
860 compatible = "generic-ehci";
865 phy-names = "usb";
867 power-domains = <&cpg>;
871 usb2_phy: usb-phy@92040200 {
872 compatible = "renesas,usb2-phy-r9a09g077";
877 #phy-cells = <1>;
878 power-domains = <&cpg>;
883 compatible = "renesas,usbhs-r9a09g077";
890 phy-names = "usb";
891 power-domains = <&cpg>;
896 compatible = "renesas,sdhi-r9a09g077",
897 "renesas,sdhi-r9a09g057";
903 clock-names = "aclk", "clkh";
904 power-domains = <&cpg>;
907 sdhi0_vqmmc: vqmmc-regulator {
908 regulator-name = "SDHI0-VQMMC";
909 regulator-min-microvolt = <1800000>;
910 regulator-max-microvolt = <3300000>;
916 compatible = "renesas,sdhi-r9a09g077",
917 "renesas,sdhi-r9a09g057";
923 clock-names = "aclk", "clkh";
924 power-domains = <&cpg>;
927 sdhi1_vqmmc: vqmmc-regulator {
928 regulator-name = "SDHI1-VQMMC";
929 regulator-min-microvolt = <1800000>;
930 regulator-max-microvolt = <3300000>;
936 stmmac_axi_setup: stmmac-axi-config {
944 compatible = "arm,armv8-timer";
950 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";