Lines Matching +full:0 +full:x10420000
18 #clock-cells = <0>;
20 clock-frequency = <0>;
30 cluster0_opp: opp-table-0 {
58 #size-cells = <0>;
60 cpu0: cpu@0 {
62 reg = <0>;
72 reg = <0x100>;
82 reg = <0x200>;
92 reg = <0x300>;
100 L3_CA55: cache-controller-0 {
103 cache-size = <0x100000>;
115 #clock-cells = <0>;
117 clock-frequency = <0>;
122 #clock-cells = <0>;
124 clock-frequency = <0>;
136 reg = <0 0x10400000 0 0x10000>;
138 #address-cells = <0>;
140 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
213 "int-ca55-0", "int-ca55-1",
218 clocks = <&cpg CPG_MOD 0x5>;
220 resets = <&cpg 0x36>;
225 reg = <0 0x10410000 0 0x10000>;
229 gpio-ranges = <&pinctrl 0 0 96>;
234 resets = <&cpg 0xa5>, <&cpg 0xa6>;
239 reg = <0 0x10420000 0 0x10000>;
244 #power-domain-cells = <0>;
249 reg = <0 0x10430000 0 0x10000>;
251 resets = <&cpg 0x30>;
257 reg = <0x0 0x11800000 0x0 0x1000>;
259 clocks = <&cpg CPG_MOD 0x43>;
260 resets = <&cpg 0x6d>;
267 reg = <0x0 0x11801000 0x0 0x1000>;
269 clocks = <&cpg CPG_MOD 0x44>;
270 resets = <&cpg 0x6e>;
277 reg = <0x0 0x14000000 0x0 0x1000>;
279 clocks = <&cpg CPG_MOD 0x45>;
280 resets = <&cpg 0x6f>;
287 reg = <0x0 0x14001000 0x0 0x1000>;
289 clocks = <&cpg CPG_MOD 0x46>;
290 resets = <&cpg 0x70>;
297 reg = <0x0 0x12c00000 0x0 0x1000>;
299 clocks = <&cpg CPG_MOD 0x47>;
300 resets = <&cpg 0x71>;
307 reg = <0x0 0x12c01000 0x0 0x1000>;
309 clocks = <&cpg CPG_MOD 0x48>;
310 resets = <&cpg 0x72>;
317 reg = <0x0 0x12c02000 0x0 0x1000>;
319 clocks = <&cpg CPG_MOD 0x49>;
320 resets = <&cpg 0x73>;
327 reg = <0x0 0x12c03000 0x0 0x1000>;
329 clocks = <&cpg CPG_MOD 0x4a>;
330 resets = <&cpg 0x74>;
337 reg = <0 0x11c00400 0 0x400>;
338 clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>;
340 resets = <&cpg 0x75>;
347 reg = <0 0x14400000 0 0x400>;
348 clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>;
350 resets = <&cpg 0x76>;
357 reg = <0 0x13000000 0 0x400>;
358 clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>;
360 resets = <&cpg 0x77>;
367 reg = <0 0x13000400 0 0x400>;
368 clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>;
370 resets = <&cpg 0x78>;
377 reg = <0 0x11c01400 0 0x400>;
389 clocks = <&cpg CPG_MOD 0x8f>;
392 resets = <&cpg 0x95>;
398 reg = <0 0x14400400 0 0x400>;
409 clocks = <&cpg CPG_MOD 0x94>;
410 resets = <&cpg 0x98>;
413 #size-cells = <0>;
419 reg = <0 0x14400800 0 0x400>;
430 clocks = <&cpg CPG_MOD 0x95>;
431 resets = <&cpg 0x99>;
434 #size-cells = <0>;
440 reg = <0 0x14400c00 0 0x400>;
451 clocks = <&cpg CPG_MOD 0x96>;
452 resets = <&cpg 0x9a>;
455 #size-cells = <0>;
461 reg = <0 0x14401000 0 0x400>;
472 clocks = <&cpg CPG_MOD 0x97>;
473 resets = <&cpg 0x9b>;
476 #size-cells = <0>;
482 reg = <0 0x14401400 0 0x400>;
493 clocks = <&cpg CPG_MOD 0x98>;
494 resets = <&cpg 0x9c>;
497 #size-cells = <0>;
503 reg = <0 0x14401800 0 0x400>;
514 clocks = <&cpg CPG_MOD 0x99>;
515 resets = <&cpg 0x9d>;
518 #size-cells = <0>;
524 reg = <0 0x14401c00 0 0x400>;
535 clocks = <&cpg CPG_MOD 0x9a>;
536 resets = <&cpg 0x9e>;
539 #size-cells = <0>;
545 reg = <0 0x14402000 0 0x400>;
556 clocks = <&cpg CPG_MOD 0x9b>;
557 resets = <&cpg 0x9f>;
560 #size-cells = <0>;
566 reg = <0 0x11c01000 0 0x400>;
577 clocks = <&cpg CPG_MOD 0x93>;
578 resets = <&cpg 0xa0>;
581 #size-cells = <0>;
587 reg = <0x0 0x14900000 0 0x20000>,
588 <0x0 0x14940000 0 0x80000>;
590 #address-cells = <0>;
597 reg = <0x0 0x15c00000 0 0x10000>;
600 clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>,
601 <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>;
603 resets = <&cpg 0xa7>;
610 reg = <0x0 0x15c10000 0 0x10000>;
613 clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>,
614 <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>;
616 resets = <&cpg 0xa8>;
623 reg = <0x0 0x15c20000 0 0x10000>;
626 clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>,
627 <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>;
629 resets = <&cpg 0xa9>;