Lines Matching +full:- +full:cpg
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a09g011-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
21 clock-frequency = <0>;
25 #address-cells = <1>;
26 #size-cells = <0>;
28 cpu-map {
37 compatible = "arm,cortex-a53";
40 next-level-cache = <&L2_CA53>;
41 clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>;
44 L2_CA53: cache-controller-0 {
46 cache-unified;
47 cache-level = <2>;
52 compatible = "simple-bus";
53 interrupt-parent = <&gic>;
54 #address-cells = <2>;
55 #size-cells = <2>;
58 gic: interrupt-controller@82010000 {
59 compatible = "arm,gic-400";
60 #interrupt-cells = <3>;
61 #address-cells = <0>;
62 interrupt-controller;
68 clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>;
69 clock-names = "clk";
73 compatible = "renesas,sdhi-r9a09g011",
74 "renesas,rzg2l-sdhi";
78 clocks = <&cpg CPG_MOD R9A09G011_SDI0_IMCLK>,
79 <&cpg CPG_MOD R9A09G011_SDI0_CLK_HS>,
80 <&cpg CPG_MOD R9A09G011_SDI0_IMCLK2>,
81 <&cpg CPG_MOD R9A09G011_SDI0_ACLK>;
82 clock-names = "core", "clkh", "cd", "aclk";
83 resets = <&cpg R9A09G011_SDI0_IXRST>;
84 power-domains = <&cpg>;
89 compatible = "renesas,sdhi-r9a09g011",
90 "renesas,rzg2l-sdhi";
94 clocks = <&cpg CPG_MOD R9A09G011_SDI1_IMCLK>,
95 <&cpg CPG_MOD R9A09G011_SDI1_CLK_HS>,
96 <&cpg CPG_MOD R9A09G011_SDI1_IMCLK2>,
97 <&cpg CPG_MOD R9A09G011_SDI1_ACLK>;
98 clock-names = "core", "clkh", "cd", "aclk";
99 resets = <&cpg R9A09G011_SDI1_IXRST>;
100 power-domains = <&cpg>;
105 compatible = "renesas,sdhi-r9a09g011",
106 "renesas,rzg2l-sdhi";
110 clocks = <&cpg CPG_MOD R9A09G011_EMM_IMCLK>,
111 <&cpg CPG_MOD R9A09G011_EMM_CLK_HS>,
112 <&cpg CPG_MOD R9A09G011_EMM_IMCLK2>,
113 <&cpg CPG_MOD R9A09G011_EMM_ACLK>;
114 clock-names = "core", "clkh", "cd", "aclk";
115 resets = <&cpg R9A09G011_EMM_IXRST>;
116 power-domains = <&cpg>;
121 compatible = "renesas,r9a09g011-usb3drd",
122 "renesas,rzv2m-usb3drd";
127 interrupt-names = "drd", "bc", "gpi";
128 clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_P>,
129 <&cpg CPG_MOD R9A09G011_USB_PCLK>;
130 clock-names = "axi", "reg";
131 resets = <&cpg R9A09G011_USB_DRD_RESET>;
132 power-domains = <&cpg>;
134 #address-cells = <2>;
135 #size-cells = <2>;
139 compatible = "renesas,r9a09g011-xhci",
140 "renesas,rzv2m-xhci";
143 clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_H>,
144 <&cpg CPG_MOD R9A09G011_USB_PCLK>;
145 clock-names = "axi", "reg";
146 resets = <&cpg R9A09G011_USB_ARESETN_H>;
147 power-domains = <&cpg>;
152 compatible = "renesas,r9a09g011-usb3-peri",
153 "renesas,rzv2m-usb3-peri";
156 clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_P>,
157 <&cpg CPG_MOD R9A09G011_USB_PCLK>;
158 clock-names = "axi", "reg";
159 resets = <&cpg R9A09G011_USB_ARESETN_P>;
160 power-domains = <&cpg>;
166 compatible = "renesas,etheravb-r9a09g011", "renesas,etheravb-rzv2m";
197 interrupt-names = "ch0", "ch1", "ch2", "ch3",
205 clocks = <&cpg CPG_MOD R9A09G011_ETH0_CLK_AXI>,
206 <&cpg CPG_MOD R9A09G011_ETH0_CLK_CHI>,
207 <&cpg CPG_MOD R9A09G011_ETH0_GPTP_EXT>;
208 clock-names = "axi", "chi", "gptp";
209 resets = <&cpg R9A09G011_ETH0_RST_HW_N>;
210 power-domains = <&cpg>;
211 #address-cells = <1>;
212 #size-cells = <0>;
216 cpg: clock-controller@a3500000 { label
217 compatible = "renesas,r9a09g011-cpg";
220 clock-names = "extal";
221 #clock-cells = <2>;
222 #reset-cells = <1>;
223 #power-domain-cells = <0>;
227 compatible = "renesas,r9a09g011-pwc", "renesas,rzv2m-pwc";
229 gpio-controller;
230 #gpio-cells = <2>;
234 sys: system-controller@a3f03000 {
235 compatible = "renesas,r9a09g011-sys";
240 compatible = "renesas,rzv2m-csi";
243 clocks = <&cpg CPG_MOD R9A09G011_CSI0_CLK>,
244 <&cpg CPG_MOD R9A09G011_CPERI_GRPG_PCLK>;
245 clock-names = "csiclk", "pclk";
246 resets = <&cpg R9A09G011_CSI_GPG_PRESETN>;
247 power-domains = <&cpg>;
248 #address-cells = <1>;
249 #size-cells = <0>;
254 compatible = "renesas,rzv2m-csi";
257 clocks = <&cpg CPG_MOD R9A09G011_CSI4_CLK>,
258 <&cpg CPG_MOD R9A09G011_CPERI_GRPH_PCLK>;
259 clock-names = "csiclk", "pclk";
260 resets = <&cpg R9A09G011_CSI_GPH_PRESETN>;
261 power-domains = <&cpg>;
262 #address-cells = <1>;
263 #size-cells = <0>;
268 #address-cells = <1>;
269 #size-cells = <0>;
270 compatible = "renesas,r9a09g011-i2c", "renesas,rzv2m-i2c";
274 interrupt-names = "tia", "tis";
275 clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK0>;
276 resets = <&cpg R9A09G011_IIC_GPA_PRESETN>;
277 power-domains = <&cpg>;
282 #address-cells = <1>;
283 #size-cells = <0>;
284 compatible = "renesas,r9a09g011-i2c", "renesas,rzv2m-i2c";
288 interrupt-names = "tia", "tis";
289 clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK1>;
290 resets = <&cpg R9A09G011_IIC_GPB_PRESETN>;
291 power-domains = <&cpg>;
296 compatible = "renesas,r9a09g011-uart", "renesas,em-uart";
299 clocks = <&cpg CPG_MOD R9A09G011_URT0_CLK>,
300 <&cpg CPG_MOD R9A09G011_URT_PCLK>;
301 clock-names = "sclk", "pclk";
306 compatible = "renesas,r9a09g011-wdt",
307 "renesas,rzv2m-wdt";
309 clocks = <&cpg CPG_MOD R9A09G011_WDT0_PCLK>,
310 <&cpg CPG_MOD R9A09G011_WDT0_CLK>;
311 clock-names = "pclk", "oscclk";
313 resets = <&cpg R9A09G011_WDT0_PRESETN>;
314 power-domains = <&cpg>;
319 compatible = "renesas,r9a09g011-pinctrl";
321 gpio-controller;
322 #gpio-cells = <2>;
323 gpio-ranges = <&pinctrl 0 0 352>;
363 clocks = <&cpg CPG_MOD R9A09G011_PFC_PCLK>;
364 power-domains = <&cpg>;
365 resets = <&cpg R9A09G011_PFC_PRESETN>;
370 compatible = "arm,armv8-timer";
371 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
375 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";