Lines Matching +full:r9a09g057 +full:- +full:cpg
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a08g045-cpg.h>
10 #include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
17 audio_clk1: audio1-clk {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
21 clock-frequency = <0>;
24 audio_clk2: audio2-clk {
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
28 clock-frequency = <0>;
31 cluster0_opp: opp-table-0 {
32 compatible = "operating-points-v2";
33 opp-shared;
35 opp-137500000 {
36 opp-hz = /bits/ 64 <137500000>;
37 opp-microvolt = <940000>;
38 clock-latency-ns = <300000>;
40 opp-275000000 {
41 opp-hz = /bits/ 64 <275000000>;
42 opp-microvolt = <940000>;
43 clock-latency-ns = <300000>;
45 opp-550000000 {
46 opp-hz = /bits/ 64 <550000000>;
47 opp-microvolt = <940000>;
48 clock-latency-ns = <300000>;
50 opp-1100000000 {
51 opp-hz = /bits/ 64 <1100000000>;
52 opp-microvolt = <940000>;
53 clock-latency-ns = <300000>;
54 opp-suspend;
59 #address-cells = <1>;
60 #size-cells = <0>;
63 compatible = "arm,cortex-a55";
66 #cooling-cells = <2>;
67 next-level-cache = <&L3_CA55>;
68 enable-method = "psci";
69 clocks = <&cpg CPG_CORE R9A08G045_CLK_I>;
70 operating-points-v2 = <&cluster0_opp>;
73 L3_CA55: cache-controller-0 {
75 cache-level = <3>;
76 cache-unified;
77 cache-size = <0x40000>;
81 extal_clk: extal-clk {
82 compatible = "fixed-clock";
83 #clock-cells = <0>;
85 clock-frequency = <0>;
89 compatible = "arm,psci-1.0", "arm,psci-0.2";
94 compatible = "simple-bus";
95 interrupt-parent = <&gic>;
96 #address-cells = <2>;
97 #size-cells = <2>;
101 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
109 interrupt-names = "eri", "rxi", "txi",
111 clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>;
112 clock-names = "fck";
113 power-domains = <&cpg>;
114 resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>;
119 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
127 interrupt-names = "eri", "rxi", "txi",
129 clocks = <&cpg CPG_MOD R9A08G045_SCIF1_CLK_PCK>;
130 clock-names = "fck";
131 power-domains = <&cpg>;
132 resets = <&cpg R9A08G045_SCIF1_RST_SYSTEM_N>;
137 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
145 interrupt-names = "eri", "rxi", "txi",
147 clocks = <&cpg CPG_MOD R9A08G045_SCIF2_CLK_PCK>;
148 clock-names = "fck";
149 power-domains = <&cpg>;
150 resets = <&cpg R9A08G045_SCIF2_RST_SYSTEM_N>;
155 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
163 interrupt-names = "eri", "rxi", "txi",
165 clocks = <&cpg CPG_MOD R9A08G045_SCIF3_CLK_PCK>;
166 clock-names = "fck";
167 power-domains = <&cpg>;
168 resets = <&cpg R9A08G045_SCIF3_RST_SYSTEM_N>;
173 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
181 interrupt-names = "eri", "rxi", "txi",
183 clocks = <&cpg CPG_MOD R9A08G045_SCIF4_CLK_PCK>;
184 clock-names = "fck";
185 power-domains = <&cpg>;
186 resets = <&cpg R9A08G045_SCIF4_RST_SYSTEM_N>;
191 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
199 interrupt-names = "eri", "rxi", "txi",
201 clocks = <&cpg CPG_MOD R9A08G045_SCIF5_CLK_PCK>;
202 clock-names = "fck";
203 power-domains = <&cpg>;
204 resets = <&cpg R9A08G045_SCIF5_RST_SYSTEM_N>;
209 compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3";
214 interrupt-names = "alarm", "period", "carry";
215 clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb VBATTB_VBATTCLK>;
216 clock-names = "bus", "counter";
217 power-domains = <&cpg>;
218 resets = <&cpg R9A08G045_VBAT_BRESETN>;
223 compatible = "renesas,r9a08g045-adc";
226 clocks = <&cpg CPG_MOD R9A08G045_ADC_ADCLK>,
227 <&cpg CPG_MOD R9A08G045_ADC_PCLK>;
228 clock-names = "adclk", "pclk";
229 resets = <&cpg R9A08G045_ADC_PRESETN>,
230 <&cpg R9A08G045_ADC_ADRST_N>;
231 reset-names = "presetn", "adrst-n";
232 power-domains = <&cpg>;
233 #address-cells = <1>;
234 #size-cells = <0>;
235 #io-channel-cells = <1>;
275 vbattb: clock-controller@1005c000 {
276 compatible = "renesas,r9a08g045-vbattb";
279 clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
280 clock-names = "bclk", "rtx";
281 #clock-cells = <1>;
282 power-domains = <&cpg>;
283 resets = <&cpg R9A08G045_VBAT_BRESETN>;
288 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
298 interrupt-names = "tei", "ri", "ti", "spi", "sti",
300 clocks = <&cpg CPG_MOD R9A08G045_I2C0_PCLK>;
301 clock-frequency = <100000>;
302 resets = <&cpg R9A08G045_I2C0_MRST>;
303 power-domains = <&cpg>;
304 #address-cells = <1>;
305 #size-cells = <0>;
310 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
320 interrupt-names = "tei", "ri", "ti", "spi", "sti",
322 clocks = <&cpg CPG_MOD R9A08G045_I2C1_PCLK>;
323 clock-frequency = <100000>;
324 resets = <&cpg R9A08G045_I2C1_MRST>;
325 power-domains = <&cpg>;
326 #address-cells = <1>;
327 #size-cells = <0>;
332 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
342 interrupt-names = "tei", "ri", "ti", "spi", "sti",
344 clocks = <&cpg CPG_MOD R9A08G045_I2C2_PCLK>;
345 clock-frequency = <100000>;
346 resets = <&cpg R9A08G045_I2C2_MRST>;
347 power-domains = <&cpg>;
348 #address-cells = <1>;
349 #size-cells = <0>;
354 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
364 interrupt-names = "tei", "ri", "ti", "spi", "sti",
366 clocks = <&cpg CPG_MOD R9A08G045_I2C3_PCLK>;
367 clock-frequency = <100000>;
368 resets = <&cpg R9A08G045_I2C3_MRST>;
369 power-domains = <&cpg>;
370 #address-cells = <1>;
371 #size-cells = <0>;
376 compatible = "renesas,r9a08g045-ssi",
377 "renesas,rz-ssi";
382 interrupt-names = "int_req", "dma_rx", "dma_tx";
383 clocks = <&cpg CPG_MOD R9A08G045_SSI0_PCLK2>,
384 <&cpg CPG_MOD R9A08G045_SSI0_PCLK_SFR>,
386 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
387 resets = <&cpg R9A08G045_SSI0_RST_M2_REG>;
389 dma-names = "tx", "rx";
390 power-domains = <&cpg>;
391 #sound-dai-cells = <0>;
396 compatible = "renesas,r9a08g045-ssi",
397 "renesas,rz-ssi";
402 interrupt-names = "int_req", "dma_rx", "dma_tx";
403 clocks = <&cpg CPG_MOD R9A08G045_SSI1_PCLK2>,
404 <&cpg CPG_MOD R9A08G045_SSI1_PCLK_SFR>,
406 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
407 resets = <&cpg R9A08G045_SSI1_RST_M2_REG>;
409 dma-names = "tx", "rx";
410 power-domains = <&cpg>;
411 #sound-dai-cells = <0>;
416 compatible = "renesas,r9a08g045-ssi",
417 "renesas,rz-ssi";
422 interrupt-names = "int_req", "dma_rx", "dma_tx";
423 clocks = <&cpg CPG_MOD R9A08G045_SSI2_PCLK2>,
424 <&cpg CPG_MOD R9A08G045_SSI2_PCLK_SFR>,
426 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
427 resets = <&cpg R9A08G045_SSI2_RST_M2_REG>;
429 dma-names = "tx", "rx";
430 power-domains = <&cpg>;
431 #sound-dai-cells = <0>;
436 compatible = "renesas,r9a08g045-ssi",
437 "renesas,rz-ssi";
442 interrupt-names = "int_req", "dma_rx", "dma_tx";
443 clocks = <&cpg CPG_MOD R9A08G045_SSI3_PCLK2>,
444 <&cpg CPG_MOD R9A08G045_SSI3_PCLK_SFR>,
446 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
447 resets = <&cpg R9A08G045_SSI3_RST_M2_REG>;
449 dma-names = "tx", "rx";
450 power-domains = <&cpg>;
451 #sound-dai-cells = <0>;
455 cpg: clock-controller@11010000 { label
456 compatible = "renesas,r9a08g045-cpg";
459 clock-names = "extal";
460 #clock-cells = <2>;
461 #reset-cells = <1>;
462 #power-domain-cells = <0>;
465 sysc: system-controller@11020000 {
466 compatible = "renesas,r9a08g045-sysc";
472 interrupt-names = "lpm_int", "ca55stbydone_int",
477 compatible = "renesas,r9a08g045-pinctrl";
479 gpio-controller;
480 #gpio-cells = <2>;
481 interrupt-controller;
482 #interrupt-cells = <2>;
483 interrupt-parent = <&irqc>;
484 gpio-ranges = <&pinctrl 0 0 152>;
485 clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>;
486 power-domains = <&cpg>;
487 resets = <&cpg R9A08G045_GPIO_RSTN>,
488 <&cpg R9A08G045_GPIO_PORT_RESETN>,
489 <&cpg R9A08G045_GPIO_SPARE_RESETN>;
492 irqc: interrupt-controller@11050000 {
493 compatible = "renesas,r9a08g045-irqc", "renesas,rzg2l-irqc";
494 #interrupt-cells = <2>;
495 #address-cells = <0>;
496 interrupt-controller;
543 interrupt-names = "nmi",
554 "bus-err", "ec7tie1-0", "ec7tie2-0",
555 "ec7tiovf-0";
556 clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>,
557 <&cpg CPG_MOD R9A08G045_IA55_PCLK>;
558 clock-names = "clk", "pclk";
559 power-domains = <&cpg>;
560 resets = <&cpg R9A08G045_IA55_RESETN>;
563 dmac: dma-controller@11820000 {
564 compatible = "renesas,r9a08g045-dmac",
565 "renesas,rz-dmac";
585 interrupt-names = "error",
590 clocks = <&cpg CPG_MOD R9A08G045_DMAC_ACLK>,
591 <&cpg CPG_MOD R9A08G045_DMAC_PCLK>;
592 clock-names = "main", "register";
593 power-domains = <&cpg>;
594 resets = <&cpg R9A08G045_DMAC_ARESETN>,
595 <&cpg R9A08G045_DMAC_RST_ASYNC>;
596 reset-names = "arst", "rst_async";
597 #dma-cells = <1>;
598 dma-channels = <16>;
602 compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi";
606 clocks = <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK>,
607 <&cpg CPG_MOD R9A08G045_SDHI0_CLK_HS>,
608 <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK2>,
609 <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>;
610 clock-names = "core", "clkh", "cd", "aclk";
611 resets = <&cpg R9A08G045_SDHI0_IXRST>;
612 power-domains = <&cpg>;
617 compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi";
621 clocks = <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK>,
622 <&cpg CPG_MOD R9A08G045_SDHI1_CLK_HS>,
623 <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>,
624 <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>;
625 clock-names = "core", "clkh", "cd", "aclk";
626 resets = <&cpg R9A08G045_SDHI1_IXRST>;
627 power-domains = <&cpg>;
632 compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi";
636 clocks = <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK>,
637 <&cpg CPG_MOD R9A08G045_SDHI2_CLK_HS>,
638 <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>,
639 <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>;
640 clock-names = "core", "clkh", "cd", "aclk";
641 resets = <&cpg R9A08G045_SDHI2_IXRST>;
642 power-domains = <&cpg>;
647 compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
652 interrupt-names = "mux", "fil", "arp_ns";
653 phy-mode = "rgmii";
654 clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>,
655 <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>,
656 <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>;
657 clock-names = "axi", "chi", "refclk";
658 resets = <&cpg R9A08G045_ETH0_RST_HW_N>;
659 power-domains = <&cpg>;
660 #address-cells = <1>;
661 #size-cells = <0>;
666 compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
671 interrupt-names = "mux", "fil", "arp_ns";
672 phy-mode = "rgmii";
673 clocks = <&cpg CPG_MOD R9A08G045_ETH1_CLK_AXI>,
674 <&cpg CPG_MOD R9A08G045_ETH1_CLK_CHI>,
675 <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>;
676 clock-names = "axi", "chi", "refclk";
677 resets = <&cpg R9A08G045_ETH1_RST_HW_N>;
678 power-domains = <&cpg>;
679 #address-cells = <1>;
680 #size-cells = <0>;
684 gic: interrupt-controller@12400000 {
685 compatible = "arm,gic-v3";
686 #interrupt-cells = <3>;
687 #address-cells = <0>;
688 interrupt-controller;
695 compatible = "renesas,r9a08g045-wdt", "renesas,rzg2l-wdt";
697 clocks = <&cpg CPG_MOD R9A08G045_WDT0_PCLK>,
698 <&cpg CPG_MOD R9A08G045_WDT0_CLK>;
699 clock-names = "pclk", "oscclk";
702 interrupt-names = "wdt", "perrout";
703 resets = <&cpg R9A08G045_WDT0_PRESETN>;
704 power-domains = <&cpg>;
710 compatible = "arm,armv8-timer";
711 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
716 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
717 "hyp-virt";
720 vbattb_xtal: vbattb-xtal {
721 compatible = "fixed-clock";
722 #clock-cells = <0>;
724 clock-frequency = <0>;