Lines Matching +full:0 +full:x1005c000
19 #size-cells = <0>;
21 cpu0: cpu@0 {
23 reg = <0>;
31 L3_CA55: cache-controller-0 {
35 cache-size = <0x40000>;
41 #clock-cells = <0>;
43 clock-frequency = <0>;
60 reg = <0 0x1004b800 0 0x400>;
78 reg = <0 0x1004ec00 0 0x400>;
92 reg = <0 0x1005c000 0 0x1000>;
104 reg = <0 0x10090000 0 0x400>;
120 #size-cells = <0>;
126 reg = <0 0x10090400 0 0x400>;
142 #size-cells = <0>;
148 reg = <0 0x10090800 0 0x400>;
164 #size-cells = <0>;
170 reg = <0 0x10090c00 0 0x400>;
186 #size-cells = <0>;
192 reg = <0 0x11010000 0 0x10000>;
197 #power-domain-cells = <0>;
202 reg = <0 0x11020000 0 0x10000>;
214 reg = <0 0x11030000 0 0x10000>;
220 gpio-ranges = <&pinctrl 0 0 152>;
231 #address-cells = <0>;
233 reg = <0 0x11050000 0 0x10000>;
234 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
290 "bus-err", "ec7tie1-0", "ec7tie2-0",
291 "ec7tiovf-0";
302 reg = <0 0x11820000 0 0x10000>,
303 <0 0x11830000 0 0x10000>;
339 reg = <0x0 0x11c00000 0 0x10000>;
354 reg = <0x0 0x11c10000 0 0x10000>;
369 reg = <0x0 0x11c20000 0 0x10000>;
384 reg = <0 0x11c30000 0 0x10000>;
397 #size-cells = <0>;
403 reg = <0 0x11c40000 0 0x10000>;
416 #size-cells = <0>;
423 #address-cells = <0>;
425 reg = <0x0 0x12400000 0 0x20000>,
426 <0x0 0x12440000 0 0x40000>;
432 reg = <0 0x12800800 0 0x400>;
458 #clock-cells = <0>;
460 clock-frequency = <0>;