Lines Matching +full:- +full:cpg
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a08g045-cpg.h>
10 #include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a55";
25 #cooling-cells = <2>;
26 next-level-cache = <&L3_CA55>;
27 enable-method = "psci";
28 clocks = <&cpg CPG_CORE R9A08G045_CLK_I>;
31 L3_CA55: cache-controller-0 {
33 cache-level = <3>;
34 cache-unified;
35 cache-size = <0x40000>;
39 extal_clk: extal-clk {
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
43 clock-frequency = <0>;
47 compatible = "arm,psci-1.0", "arm,psci-0.2";
52 compatible = "simple-bus";
53 interrupt-parent = <&gic>;
54 #address-cells = <2>;
55 #size-cells = <2>;
59 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
67 interrupt-names = "eri", "rxi", "txi",
69 clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>;
70 clock-names = "fck";
71 power-domains = <&cpg>;
72 resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>;
77 compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3";
82 interrupt-names = "alarm", "period", "carry";
83 clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb VBATTB_VBATTCLK>;
84 clock-names = "bus", "counter";
85 power-domains = <&cpg>;
86 resets = <&cpg R9A08G045_VBAT_BRESETN>;
90 vbattb: clock-controller@1005c000 {
91 compatible = "renesas,r9a08g045-vbattb";
94 clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
95 clock-names = "bclk", "rtx";
96 #clock-cells = <1>;
97 power-domains = <&cpg>;
98 resets = <&cpg R9A08G045_VBAT_BRESETN>;
103 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
113 interrupt-names = "tei", "ri", "ti", "spi", "sti",
115 clocks = <&cpg CPG_MOD R9A08G045_I2C0_PCLK>;
116 clock-frequency = <100000>;
117 resets = <&cpg R9A08G045_I2C0_MRST>;
118 power-domains = <&cpg>;
119 #address-cells = <1>;
120 #size-cells = <0>;
125 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
135 interrupt-names = "tei", "ri", "ti", "spi", "sti",
137 clocks = <&cpg CPG_MOD R9A08G045_I2C1_PCLK>;
138 clock-frequency = <100000>;
139 resets = <&cpg R9A08G045_I2C1_MRST>;
140 power-domains = <&cpg>;
141 #address-cells = <1>;
142 #size-cells = <0>;
147 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
157 interrupt-names = "tei", "ri", "ti", "spi", "sti",
159 clocks = <&cpg CPG_MOD R9A08G045_I2C2_PCLK>;
160 clock-frequency = <100000>;
161 resets = <&cpg R9A08G045_I2C2_MRST>;
162 power-domains = <&cpg>;
163 #address-cells = <1>;
164 #size-cells = <0>;
169 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
179 interrupt-names = "tei", "ri", "ti", "spi", "sti",
181 clocks = <&cpg CPG_MOD R9A08G045_I2C3_PCLK>;
182 clock-frequency = <100000>;
183 resets = <&cpg R9A08G045_I2C3_MRST>;
184 power-domains = <&cpg>;
185 #address-cells = <1>;
186 #size-cells = <0>;
190 cpg: clock-controller@11010000 { label
191 compatible = "renesas,r9a08g045-cpg";
194 clock-names = "extal";
195 #clock-cells = <2>;
196 #reset-cells = <1>;
197 #power-domain-cells = <0>;
200 sysc: system-controller@11020000 {
201 compatible = "renesas,r9a08g045-sysc";
207 interrupt-names = "lpm_int", "ca55stbydone_int",
213 compatible = "renesas,r9a08g045-pinctrl";
215 gpio-controller;
216 #gpio-cells = <2>;
217 interrupt-controller;
218 #interrupt-cells = <2>;
219 interrupt-parent = <&irqc>;
220 gpio-ranges = <&pinctrl 0 0 152>;
221 clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>;
222 power-domains = <&cpg>;
223 resets = <&cpg R9A08G045_GPIO_RSTN>,
224 <&cpg R9A08G045_GPIO_PORT_RESETN>,
225 <&cpg R9A08G045_GPIO_SPARE_RESETN>;
228 irqc: interrupt-controller@11050000 {
229 compatible = "renesas,r9a08g045-irqc", "renesas,rzg2l-irqc";
230 #interrupt-cells = <2>;
231 #address-cells = <0>;
232 interrupt-controller;
279 interrupt-names = "nmi",
290 "bus-err", "ec7tie1-0", "ec7tie2-0",
291 "ec7tiovf-0";
292 clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>,
293 <&cpg CPG_MOD R9A08G045_IA55_PCLK>;
294 clock-names = "clk", "pclk";
295 power-domains = <&cpg>;
296 resets = <&cpg R9A08G045_IA55_RESETN>;
299 dmac: dma-controller@11820000 {
300 compatible = "renesas,r9a08g045-dmac",
301 "renesas,rz-dmac";
321 interrupt-names = "error",
326 clocks = <&cpg CPG_MOD R9A08G045_DMAC_ACLK>,
327 <&cpg CPG_MOD R9A08G045_DMAC_PCLK>;
328 clock-names = "main", "register";
329 power-domains = <&cpg>;
330 resets = <&cpg R9A08G045_DMAC_ARESETN>,
331 <&cpg R9A08G045_DMAC_RST_ASYNC>;
332 reset-names = "arst", "rst_async";
333 #dma-cells = <1>;
334 dma-channels = <16>;
338 compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi";
342 clocks = <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK>,
343 <&cpg CPG_MOD R9A08G045_SDHI0_CLK_HS>,
344 <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK2>,
345 <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>;
346 clock-names = "core", "clkh", "cd", "aclk";
347 resets = <&cpg R9A08G045_SDHI0_IXRST>;
348 power-domains = <&cpg>;
353 compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi";
357 clocks = <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK>,
358 <&cpg CPG_MOD R9A08G045_SDHI1_CLK_HS>,
359 <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>,
360 <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>;
361 clock-names = "core", "clkh", "cd", "aclk";
362 resets = <&cpg R9A08G045_SDHI1_IXRST>;
363 power-domains = <&cpg>;
368 compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi";
372 clocks = <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK>,
373 <&cpg CPG_MOD R9A08G045_SDHI2_CLK_HS>,
374 <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>,
375 <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>;
376 clock-names = "core", "clkh", "cd", "aclk";
377 resets = <&cpg R9A08G045_SDHI2_IXRST>;
378 power-domains = <&cpg>;
383 compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
388 interrupt-names = "mux", "fil", "arp_ns";
389 phy-mode = "rgmii";
390 clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>,
391 <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>,
392 <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>;
393 clock-names = "axi", "chi", "refclk";
394 resets = <&cpg R9A08G045_ETH0_RST_HW_N>;
395 power-domains = <&cpg>;
396 #address-cells = <1>;
397 #size-cells = <0>;
402 compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
407 interrupt-names = "mux", "fil", "arp_ns";
408 phy-mode = "rgmii";
409 clocks = <&cpg CPG_MOD R9A08G045_ETH1_CLK_AXI>,
410 <&cpg CPG_MOD R9A08G045_ETH1_CLK_CHI>,
411 <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>;
412 clock-names = "axi", "chi", "refclk";
413 resets = <&cpg R9A08G045_ETH1_RST_HW_N>;
414 power-domains = <&cpg>;
415 #address-cells = <1>;
416 #size-cells = <0>;
420 gic: interrupt-controller@12400000 {
421 compatible = "arm,gic-v3";
422 #interrupt-cells = <3>;
423 #address-cells = <0>;
424 interrupt-controller;
431 compatible = "renesas,r9a08g045-wdt", "renesas,rzg2l-wdt";
433 clocks = <&cpg CPG_MOD R9A08G045_WDT0_PCLK>,
434 <&cpg CPG_MOD R9A08G045_WDT0_CLK>;
435 clock-names = "pclk", "oscclk";
438 interrupt-names = "wdt", "perrout";
439 resets = <&cpg R9A08G045_WDT0_PRESETN>;
440 power-domains = <&cpg>;
446 compatible = "arm,armv8-timer";
447 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
452 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
453 "hyp-virt";
456 vbattb_xtal: vbattb-xtal {
457 compatible = "fixed-clock";
458 #clock-cells = <0>;
460 clock-frequency = <0>;