Lines Matching refs:cpg
9 #include <dt-bindings/clock/r9a07g054-cpg.h>
94 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
104 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
240 clocks = <&cpg CPG_MOD R9A07G054_MTU_X_MCK_MTU3>;
241 power-domains = <&cpg>;
242 resets = <&cpg R9A07G054_MTU_X_PRESET_MTU3>;
356 clocks = <&cpg CPG_MOD R9A07G054_GPT_PCLK>;
357 resets = <&cpg R9A07G054_GPT_RST_C>;
358 power-domains = <&cpg>;
370 clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>,
371 <&cpg CPG_MOD R9A07G054_SSI0_PCLK_SFR>,
374 resets = <&cpg R9A07G054_SSI0_RST_M2_REG>;
377 power-domains = <&cpg>;
390 clocks = <&cpg CPG_MOD R9A07G054_SSI1_PCLK2>,
391 <&cpg CPG_MOD R9A07G054_SSI1_PCLK_SFR>,
394 resets = <&cpg R9A07G054_SSI1_RST_M2_REG>;
397 power-domains = <&cpg>;
409 clocks = <&cpg CPG_MOD R9A07G054_SSI2_PCLK2>,
410 <&cpg CPG_MOD R9A07G054_SSI2_PCLK_SFR>,
413 resets = <&cpg R9A07G054_SSI2_RST_M2_REG>;
416 power-domains = <&cpg>;
429 clocks = <&cpg CPG_MOD R9A07G054_SSI3_PCLK2>,
430 <&cpg CPG_MOD R9A07G054_SSI3_PCLK_SFR>,
433 resets = <&cpg R9A07G054_SSI3_RST_M2_REG>;
436 power-domains = <&cpg>;
448 clocks = <&cpg CPG_MOD R9A07G054_RSPI0_CLKB>;
449 resets = <&cpg R9A07G054_RSPI0_RST>;
452 power-domains = <&cpg>;
466 clocks = <&cpg CPG_MOD R9A07G054_RSPI1_CLKB>;
467 resets = <&cpg R9A07G054_RSPI1_RST>;
470 power-domains = <&cpg>;
484 clocks = <&cpg CPG_MOD R9A07G054_RSPI2_CLKB>;
485 resets = <&cpg R9A07G054_RSPI2_RST>;
488 power-domains = <&cpg>;
507 clocks = <&cpg CPG_MOD R9A07G054_SCIF0_CLK_PCK>;
509 power-domains = <&cpg>;
510 resets = <&cpg R9A07G054_SCIF0_RST_SYSTEM_N>;
526 clocks = <&cpg CPG_MOD R9A07G054_SCIF1_CLK_PCK>;
528 power-domains = <&cpg>;
529 resets = <&cpg R9A07G054_SCIF1_RST_SYSTEM_N>;
545 clocks = <&cpg CPG_MOD R9A07G054_SCIF2_CLK_PCK>;
547 power-domains = <&cpg>;
548 resets = <&cpg R9A07G054_SCIF2_RST_SYSTEM_N>;
564 clocks = <&cpg CPG_MOD R9A07G054_SCIF3_CLK_PCK>;
566 power-domains = <&cpg>;
567 resets = <&cpg R9A07G054_SCIF3_RST_SYSTEM_N>;
583 clocks = <&cpg CPG_MOD R9A07G054_SCIF4_CLK_PCK>;
585 power-domains = <&cpg>;
586 resets = <&cpg R9A07G054_SCIF4_RST_SYSTEM_N>;
598 clocks = <&cpg CPG_MOD R9A07G054_SCI0_CLKP>;
600 power-domains = <&cpg>;
601 resets = <&cpg R9A07G054_SCI0_RST>;
613 clocks = <&cpg CPG_MOD R9A07G054_SCI1_CLKP>;
615 power-domains = <&cpg>;
616 resets = <&cpg R9A07G054_SCI1_RST>;
634 clocks = <&cpg CPG_MOD R9A07G054_CANFD_PCLK>,
635 <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>,
638 assigned-clocks = <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>;
640 resets = <&cpg R9A07G054_CANFD_RSTP_N>,
641 <&cpg R9A07G054_CANFD_RSTC_N>;
643 power-domains = <&cpg>;
669 clocks = <&cpg CPG_MOD R9A07G054_I2C0_PCLK>;
671 resets = <&cpg R9A07G054_I2C0_MRST>;
672 power-domains = <&cpg>;
691 clocks = <&cpg CPG_MOD R9A07G054_I2C1_PCLK>;
693 resets = <&cpg R9A07G054_I2C1_MRST>;
694 power-domains = <&cpg>;
713 clocks = <&cpg CPG_MOD R9A07G054_I2C2_PCLK>;
715 resets = <&cpg R9A07G054_I2C2_MRST>;
716 power-domains = <&cpg>;
735 clocks = <&cpg CPG_MOD R9A07G054_I2C3_PCLK>;
737 resets = <&cpg R9A07G054_I2C3_MRST>;
738 power-domains = <&cpg>;
746 clocks = <&cpg CPG_MOD R9A07G054_ADC_ADCLK>,
747 <&cpg CPG_MOD R9A07G054_ADC_PCLK>;
749 resets = <&cpg R9A07G054_ADC_PRESETN>,
750 <&cpg R9A07G054_ADC_ADRST_N>;
752 power-domains = <&cpg>;
788 clocks = <&cpg CPG_MOD R9A07G054_TSU_PCLK>;
789 resets = <&cpg R9A07G054_TSU_PRESETN>;
790 power-domains = <&cpg>;
802 clocks = <&cpg CPG_MOD R9A07G054_SPI_CLK2>,
803 <&cpg CPG_MOD R9A07G054_SPI_CLK>;
804 resets = <&cpg R9A07G054_SPI_RST>;
805 power-domains = <&cpg>;
814 clocks = <&cpg CPG_MOD R9A07G054_CRU_VCLK>,
815 <&cpg CPG_MOD R9A07G054_CRU_PCLK>,
816 <&cpg CPG_MOD R9A07G054_CRU_ACLK>;
822 resets = <&cpg R9A07G054_CRU_PRESETN>,
823 <&cpg R9A07G054_CRU_ARESETN>;
825 power-domains = <&cpg>;
859 clocks = <&cpg CPG_MOD R9A07G054_CRU_SYSCLK>,
860 <&cpg CPG_MOD R9A07G054_CRU_VCLK>,
861 <&cpg CPG_MOD R9A07G054_CRU_PCLK>;
863 resets = <&cpg R9A07G054_CRU_PRESETN>,
864 <&cpg R9A07G054_CRU_CMN_RSTB>;
866 power-domains = <&cpg>;
903 clocks = <&cpg CPG_MOD R9A07G054_MIPI_DSI_PLLCLK>,
904 <&cpg CPG_MOD R9A07G054_MIPI_DSI_SYSCLK>,
905 <&cpg CPG_MOD R9A07G054_MIPI_DSI_ACLK>,
906 <&cpg CPG_MOD R9A07G054_MIPI_DSI_PCLK>,
907 <&cpg CPG_MOD R9A07G054_MIPI_DSI_VCLK>,
908 <&cpg CPG_MOD R9A07G054_MIPI_DSI_LPCLK>;
910 resets = <&cpg R9A07G054_MIPI_DSI_CMN_RSTB>,
911 <&cpg R9A07G054_MIPI_DSI_ARESET_N>,
912 <&cpg R9A07G054_MIPI_DSI_PRESET_N>;
914 power-domains = <&cpg>;
939 clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>,
940 <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>,
941 <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>;
943 power-domains = <&cpg>;
944 resets = <&cpg R9A07G054_LCDC_RESET_N>;
952 clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>,
953 <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>,
954 <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>;
956 power-domains = <&cpg>;
957 resets = <&cpg R9A07G054_LCDC_RESET_N>;
965 clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>,
966 <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>,
967 <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>;
969 power-domains = <&cpg>;
970 resets = <&cpg R9A07G054_LCDC_RESET_N>;
991 cpg: clock-controller@11010000 { label
992 compatible = "renesas,r9a07g054-cpg";
1023 clocks = <&cpg CPG_MOD R9A07G054_GPIO_HCLK>;
1024 power-domains = <&cpg>;
1025 resets = <&cpg R9A07G054_GPIO_RSTN>,
1026 <&cpg R9A07G054_GPIO_PORT_RESETN>,
1027 <&cpg R9A07G054_GPIO_SPARE_RESETN>;
1098 clocks = <&cpg CPG_MOD R9A07G054_IA55_CLK>,
1099 <&cpg CPG_MOD R9A07G054_IA55_PCLK>;
1101 power-domains = <&cpg>;
1102 resets = <&cpg R9A07G054_IA55_RESETN>;
1132 clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>,
1133 <&cpg CPG_MOD R9A07G054_DMAC_PCLK>;
1135 power-domains = <&cpg>;
1136 resets = <&cpg R9A07G054_DMAC_ARESETN>,
1137 <&cpg R9A07G054_DMAC_RST_ASYNC>;
1152 clocks = <&cpg CPG_MOD R9A07G054_GPU_CLK>,
1153 <&cpg CPG_MOD R9A07G054_GPU_AXI_CLK>,
1154 <&cpg CPG_MOD R9A07G054_GPU_ACE_CLK>;
1156 power-domains = <&cpg>;
1157 resets = <&cpg R9A07G054_GPU_RESETN>,
1158 <&cpg R9A07G054_GPU_AXI_RESETN>,
1159 <&cpg R9A07G054_GPU_ACE_RESETN>;
1180 clocks = <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK>,
1181 <&cpg CPG_MOD R9A07G054_SDHI0_CLK_HS>,
1182 <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>,
1183 <&cpg CPG_MOD R9A07G054_SDHI0_ACLK>;
1185 resets = <&cpg R9A07G054_SDHI0_IXRST>;
1186 power-domains = <&cpg>;
1196 clocks = <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK>,
1197 <&cpg CPG_MOD R9A07G054_SDHI1_CLK_HS>,
1198 <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>,
1199 <&cpg CPG_MOD R9A07G054_SDHI1_ACLK>;
1201 resets = <&cpg R9A07G054_SDHI1_IXRST>;
1202 power-domains = <&cpg>;
1215 clocks = <&cpg CPG_MOD R9A07G054_ETH0_CLK_AXI>,
1216 <&cpg CPG_MOD R9A07G054_ETH0_CLK_CHI>,
1217 <&cpg CPG_CORE R9A07G054_CLK_HP>;
1219 resets = <&cpg R9A07G054_ETH0_RST_HW_N>;
1220 power-domains = <&cpg>;
1235 clocks = <&cpg CPG_MOD R9A07G054_ETH1_CLK_AXI>,
1236 <&cpg CPG_MOD R9A07G054_ETH1_CLK_CHI>,
1237 <&cpg CPG_CORE R9A07G054_CLK_HP>;
1239 resets = <&cpg R9A07G054_ETH1_RST_HW_N>;
1240 power-domains = <&cpg>;
1250 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>;
1251 resets = <&cpg R9A07G054_USB_PRESETN>;
1252 power-domains = <&cpg>;
1265 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1266 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
1268 <&cpg R9A07G054_USB_U2H0_HRESETN>;
1271 power-domains = <&cpg>;
1279 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1280 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
1282 <&cpg R9A07G054_USB_U2H1_HRESETN>;
1285 power-domains = <&cpg>;
1293 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1294 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
1296 <&cpg R9A07G054_USB_U2H0_HRESETN>;
1300 power-domains = <&cpg>;
1308 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1309 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
1311 <&cpg R9A07G054_USB_U2H1_HRESETN>;
1315 power-domains = <&cpg>;
1324 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1325 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
1328 power-domains = <&cpg>;
1337 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1338 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
1341 power-domains = <&cpg>;
1353 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1354 <&cpg CPG_MOD R9A07G054_USB_U2P_EXR_CPUCLK>;
1356 <&cpg R9A07G054_USB_U2P_EXL_SYSRST>;
1360 power-domains = <&cpg>;
1368 clocks = <&cpg CPG_MOD R9A07G054_WDT0_PCLK>,
1369 <&cpg CPG_MOD R9A07G054_WDT0_CLK>;
1374 resets = <&cpg R9A07G054_WDT0_PRESETN>;
1375 power-domains = <&cpg>;
1383 clocks = <&cpg CPG_MOD R9A07G054_WDT1_PCLK>,
1384 <&cpg CPG_MOD R9A07G054_WDT1_CLK>;
1389 resets = <&cpg R9A07G054_WDT1_PRESETN>;
1390 power-domains = <&cpg>;
1399 clocks = <&cpg CPG_MOD R9A07G054_OSTM0_PCLK>;
1400 resets = <&cpg R9A07G054_OSTM0_PRESETZ>;
1401 power-domains = <&cpg>;
1410 clocks = <&cpg CPG_MOD R9A07G054_OSTM1_PCLK>;
1411 resets = <&cpg R9A07G054_OSTM1_PRESETZ>;
1412 power-domains = <&cpg>;
1421 clocks = <&cpg CPG_MOD R9A07G054_OSTM2_PCLK>;
1422 resets = <&cpg R9A07G054_OSTM2_PRESETZ>;
1423 power-domains = <&cpg>;