Lines Matching +full:0 +full:x11c50000
18 #clock-cells = <0>;
20 clock-frequency = <0>;
25 #clock-cells = <0>;
27 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
40 #clock-cells = <0>;
42 clock-frequency = <0>;
45 cluster0_opp: opp-table-0 {
74 #size-cells = <0>;
87 cpu0: cpu@0 {
89 reg = <0>;
100 reg = <0x100>;
108 L3_CA55: cache-controller-0 {
111 cache-size = <0x40000>;
180 reg = <0 0x10001200 0 0xb00>;
250 reg = <0 0x10048000 0 0x800>;
365 reg = <0 0x10049c00 0 0x400>;
375 dmas = <&dmac 0x2655>, <&dmac 0x2656>;
378 #sound-dai-cells = <0>;
385 reg = <0 0x1004a000 0 0x400>;
395 dmas = <&dmac 0x2659>, <&dmac 0x265a>;
398 #sound-dai-cells = <0>;
405 reg = <0 0x1004a400 0 0x400>;
414 dmas = <&dmac 0x265f>;
417 #sound-dai-cells = <0>;
424 reg = <0 0x1004a800 0 0x400>;
434 dmas = <&dmac 0x2661>, <&dmac 0x2662>;
437 #sound-dai-cells = <0>;
443 reg = <0 0x1004ac00 0 0x400>;
450 dmas = <&dmac 0x2e95>, <&dmac 0x2e96>;
455 #size-cells = <0>;
461 reg = <0 0x1004b000 0 0x400>;
468 dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>;
473 #size-cells = <0>;
479 reg = <0 0x1004b400 0 0x400>;
486 dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>;
491 #size-cells = <0>;
498 reg = <0 0x1004b800 0 0x400>;
517 reg = <0 0x1004bc00 0 0x400>;
536 reg = <0 0x1004c000 0 0x400>;
555 reg = <0 0x1004c400 0 0x400>;
574 reg = <0 0x1004c800 0 0x400>;
592 reg = <0 0x1004d000 0 0x400>;
607 reg = <0 0x1004d400 0 0x400>;
622 reg = <0 0x10050000 0 0x8000>;
656 #size-cells = <0>;
658 reg = <0 0x10058000 0 0x400>;
678 #size-cells = <0>;
680 reg = <0 0x10058400 0 0x400>;
700 #size-cells = <0>;
702 reg = <0 0x10058800 0 0x400>;
722 #size-cells = <0>;
724 reg = <0 0x10058c00 0 0x400>;
744 reg = <0 0x10059000 0 0x400>;
756 #size-cells = <0>;
758 channel@0 {
759 reg = <0>;
787 reg = <0 0x10059400 0 0x400>;
797 reg = <0 0x10060000 0 0x10000>,
798 <0 0x20000000 0 0x10000000>,
799 <0 0x10070000 0 0x10000>;
807 #size-cells = <0>;
813 reg = <0 0x10830000 0 0x400>;
830 #size-cells = <0>;
832 port@0 {
834 #size-cells = <0>;
836 reg = <0>;
837 cruparallel: endpoint@0 {
838 reg = <0>;
844 #size-cells = <0>;
847 crucsi2: endpoint@0 {
848 reg = <0>;
857 reg = <0 0x10830400 0 0xfc00>;
871 #size-cells = <0>;
873 port@0 {
874 reg = <0>;
879 #size-cells = <0>;
882 csi2cru: endpoint@0 {
883 reg = <0>;
893 reg = <0 0x10850000 0 0x20000>;
919 #size-cells = <0>;
921 port@0 {
922 reg = <0>;
937 reg = <0 0x10870000 0 0x10000>;
951 reg = <0 0x10880000 0 0x10000>;
963 reg = <0 0x10890000 0 0x10000>;
971 renesas,vsps = <&vspd 0>;
976 #size-cells = <0>;
978 port@0 {
979 reg = <0>;
993 reg = <0 0x11010000 0 0x10000>;
998 #power-domain-cells = <0>;
1003 reg = <0 0x11020000 0 0x10000>;
1016 reg = <0 0x11030000 0 0x10000>;
1022 gpio-ranges = <&pinctrl 0 0 392>;
1034 #address-cells = <0>;
1036 reg = <0 0x110a0000 0 0x10000>;
1037 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
1095 "bus-err", "ec7tie1-0", "ec7tie2-0",
1096 "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
1108 reg = <0 0x11820000 0 0x10000>,
1109 <0 0x11830000 0 0x10000>;
1146 reg = <0x0 0x11840000 0x0 0x10000>;
1167 #address-cells = <0>;
1169 reg = <0x0 0x11900000 0 0x20000>,
1170 <0x0 0x11940000 0 0x40000>;
1177 reg = <0x0 0x11c00000 0 0x10000>;
1193 reg = <0x0 0x11c10000 0 0x10000>;
1209 reg = <0 0x11c20000 0 0x10000>;
1222 #size-cells = <0>;
1229 reg = <0 0x11c30000 0 0x10000>;
1242 #size-cells = <0>;
1249 reg = <0 0x11c40000 0 0x10000>;
1263 reg = <0 0x11c50000 0 0x100>;
1267 resets = <&phyrst 0>,
1277 reg = <0 0x11c70000 0 0x100>;
1291 reg = <0 0x11c50100 0 0x100>;
1295 resets = <&phyrst 0>,
1306 reg = <0 0x11c70100 0 0x100>;
1322 reg = <0 0x11c50200 0 0x700>;
1326 resets = <&phyrst 0>;
1335 reg = <0 0x11c70200 0 0x700>;
1348 reg = <0 0x11c60000 0 0x10000>;
1355 resets = <&phyrst 0>,
1367 reg = <0 0x12800800 0 0x400>;
1382 reg = <0 0x12800C00 0 0x400>;
1397 reg = <0x0 0x12801000 0x0 0x400>;
1408 reg = <0x0 0x12801400 0x0 0x400>;
1419 reg = <0x0 0x12801800 0x0 0x400>;
1432 thermal-sensors = <&tsu 0>;
1438 cooling-device = <&cpu0 0 2>;