Lines Matching +full:0 +full:x10059400
18 #clock-cells = <0>;
20 clock-frequency = <0>;
25 #clock-cells = <0>;
27 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
40 #clock-cells = <0>;
42 clock-frequency = <0>;
45 cluster0_opp: opp-table-0 {
74 #size-cells = <0>;
87 cpu0: cpu@0 {
89 reg = <0>;
100 reg = <0x100>;
108 L3_CA55: cache-controller-0 {
111 cache-size = <0x40000>;
180 reg = <0 0x10001200 0 0xb00>;
250 reg = <0 0x10049c00 0 0x400>;
260 dmas = <&dmac 0x2655>, <&dmac 0x2656>;
263 #sound-dai-cells = <0>;
270 reg = <0 0x1004a000 0 0x400>;
280 dmas = <&dmac 0x2659>, <&dmac 0x265a>;
283 #sound-dai-cells = <0>;
290 reg = <0 0x1004a400 0 0x400>;
299 dmas = <&dmac 0x265f>;
302 #sound-dai-cells = <0>;
309 reg = <0 0x1004a800 0 0x400>;
319 dmas = <&dmac 0x2661>, <&dmac 0x2662>;
322 #sound-dai-cells = <0>;
328 reg = <0 0x1004ac00 0 0x400>;
335 dmas = <&dmac 0x2e95>, <&dmac 0x2e96>;
340 #size-cells = <0>;
346 reg = <0 0x1004b000 0 0x400>;
353 dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>;
358 #size-cells = <0>;
364 reg = <0 0x1004b400 0 0x400>;
371 dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>;
376 #size-cells = <0>;
383 reg = <0 0x1004b800 0 0x400>;
402 reg = <0 0x1004bc00 0 0x400>;
421 reg = <0 0x1004c000 0 0x400>;
440 reg = <0 0x1004c400 0 0x400>;
459 reg = <0 0x1004c800 0 0x400>;
477 reg = <0 0x1004d000 0 0x400>;
492 reg = <0 0x1004d400 0 0x400>;
507 reg = <0 0x10050000 0 0x8000>;
541 #size-cells = <0>;
543 reg = <0 0x10058000 0 0x400>;
563 #size-cells = <0>;
565 reg = <0 0x10058400 0 0x400>;
585 #size-cells = <0>;
587 reg = <0 0x10058800 0 0x400>;
607 #size-cells = <0>;
609 reg = <0 0x10058c00 0 0x400>;
629 reg = <0 0x10059000 0 0x400>;
641 #size-cells = <0>;
643 channel@0 {
644 reg = <0>;
672 reg = <0 0x10059400 0 0x400>;
682 reg = <0 0x10060000 0 0x10000>,
683 <0 0x20000000 0 0x10000000>,
684 <0 0x10070000 0 0x10000>;
692 #size-cells = <0>;
698 reg = <0 0x10830000 0 0x400>;
715 #size-cells = <0>;
717 port@0 {
719 #size-cells = <0>;
721 reg = <0>;
722 cruparallel: endpoint@0 {
723 reg = <0>;
729 #size-cells = <0>;
732 crucsi2: endpoint@0 {
733 reg = <0>;
742 reg = <0 0x10830400 0 0xfc00>;
756 #size-cells = <0>;
758 port@0 {
759 reg = <0>;
764 #size-cells = <0>;
767 csi2cru: endpoint@0 {
768 reg = <0>;
778 reg = <0 0x10850000 0 0x20000>;
804 #size-cells = <0>;
806 port@0 {
807 reg = <0>;
822 reg = <0 0x10870000 0 0x10000>;
836 reg = <0 0x10880000 0 0x10000>;
848 reg = <0 0x10890000 0 0x10000>;
856 renesas,vsps = <&vspd 0>;
861 #size-cells = <0>;
863 port@0 {
864 reg = <0>;
878 reg = <0 0x11010000 0 0x10000>;
883 #power-domain-cells = <0>;
888 reg = <0 0x11020000 0 0x10000>;
901 reg = <0 0x11030000 0 0x10000>;
907 gpio-ranges = <&pinctrl 0 0 392>;
919 #address-cells = <0>;
921 reg = <0 0x110a0000 0 0x10000>;
922 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
980 "bus-err", "ec7tie1-0", "ec7tie2-0",
981 "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
993 reg = <0 0x11820000 0 0x10000>,
994 <0 0x11830000 0 0x10000>;
1031 reg = <0x0 0x11840000 0x0 0x10000>;
1052 #address-cells = <0>;
1054 reg = <0x0 0x11900000 0 0x20000>,
1055 <0x0 0x11940000 0 0x40000>;
1062 reg = <0x0 0x11c00000 0 0x10000>;
1078 reg = <0x0 0x11c10000 0 0x10000>;
1094 reg = <0 0x11c20000 0 0x10000>;
1107 #size-cells = <0>;
1114 reg = <0 0x11c30000 0 0x10000>;
1127 #size-cells = <0>;
1134 reg = <0 0x11c40000 0 0x10000>;
1148 reg = <0 0x11c50000 0 0x100>;
1152 resets = <&phyrst 0>,
1162 reg = <0 0x11c70000 0 0x100>;
1176 reg = <0 0x11c50100 0 0x100>;
1180 resets = <&phyrst 0>,
1191 reg = <0 0x11c70100 0 0x100>;
1207 reg = <0 0x11c50200 0 0x700>;
1211 resets = <&phyrst 0>;
1220 reg = <0 0x11c70200 0 0x700>;
1233 reg = <0 0x11c60000 0 0x10000>;
1240 resets = <&phyrst 0>,
1252 reg = <0 0x12800800 0 0x400>;
1267 reg = <0 0x12800C00 0 0x400>;
1282 reg = <0x0 0x12801000 0x0 0x400>;
1293 reg = <0x0 0x12801400 0x0 0x400>;
1304 reg = <0x0 0x12801800 0x0 0x400>;
1317 thermal-sensors = <&tsu 0>;
1323 cooling-device = <&cpu0 0 2>;