Lines Matching +full:0 +full:x11c50000
18 #clock-cells = <0>;
20 clock-frequency = <0>;
25 #clock-cells = <0>;
27 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
40 #clock-cells = <0>;
42 clock-frequency = <0>;
45 cluster0_opp: opp-table-0 {
74 #size-cells = <0>;
87 cpu0: cpu@0 {
89 reg = <0>;
100 reg = <0x100>;
108 L3_CA55: cache-controller-0 {
111 cache-size = <0x40000>;
180 reg = <0 0x10001200 0 0xb00>;
250 reg = <0 0x10048000 0 0x800>;
365 reg = <0 0x10049c00 0 0x400>;
375 dmas = <&dmac 0x2655>, <&dmac 0x2656>;
378 #sound-dai-cells = <0>;
385 reg = <0 0x1004a000 0 0x400>;
395 dmas = <&dmac 0x2659>, <&dmac 0x265a>;
398 #sound-dai-cells = <0>;
405 reg = <0 0x1004a400 0 0x400>;
414 dmas = <&dmac 0x265f>;
417 #sound-dai-cells = <0>;
424 reg = <0 0x1004a800 0 0x400>;
434 dmas = <&dmac 0x2661>, <&dmac 0x2662>;
437 #sound-dai-cells = <0>;
443 reg = <0 0x1004ac00 0 0x400>;
450 dmas = <&dmac 0x2e95>, <&dmac 0x2e96>;
455 #size-cells = <0>;
461 reg = <0 0x1004b000 0 0x400>;
468 dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>;
473 #size-cells = <0>;
479 reg = <0 0x1004b400 0 0x400>;
486 dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>;
491 #size-cells = <0>;
497 reg = <0 0x1004b800 0 0x400>;
515 reg = <0 0x1004bc00 0 0x400>;
533 reg = <0 0x1004c000 0 0x400>;
551 reg = <0 0x1004c400 0 0x400>;
569 reg = <0 0x1004c800 0 0x400>;
587 reg = <0 0x1004d000 0 0x400>;
602 reg = <0 0x1004d400 0 0x400>;
617 reg = <0 0x10050000 0 0x8000>;
651 #size-cells = <0>;
653 reg = <0 0x10058000 0 0x400>;
673 #size-cells = <0>;
675 reg = <0 0x10058400 0 0x400>;
695 #size-cells = <0>;
697 reg = <0 0x10058800 0 0x400>;
717 #size-cells = <0>;
719 reg = <0 0x10058c00 0 0x400>;
739 reg = <0 0x10059000 0 0x400>;
751 #size-cells = <0>;
753 channel@0 {
754 reg = <0>;
782 reg = <0 0x10059400 0 0x400>;
792 reg = <0 0x10060000 0 0x10000>,
793 <0 0x20000000 0 0x10000000>,
794 <0 0x10070000 0 0x10000>;
802 #size-cells = <0>;
808 reg = <0 0x10830000 0 0x400>;
825 #size-cells = <0>;
827 port@0 {
829 #size-cells = <0>;
831 reg = <0>;
832 cruparallel: endpoint@0 {
833 reg = <0>;
839 #size-cells = <0>;
842 crucsi2: endpoint@0 {
843 reg = <0>;
852 reg = <0 0x10830400 0 0xfc00>;
866 #size-cells = <0>;
868 port@0 {
869 reg = <0>;
874 #size-cells = <0>;
877 csi2cru: endpoint@0 {
878 reg = <0>;
888 reg = <0 0x10850000 0 0x20000>;
914 #size-cells = <0>;
916 port@0 {
917 reg = <0>;
931 reg = <0 0x10870000 0 0x10000>;
945 reg = <0 0x10880000 0 0x10000>;
956 reg = <0 0x10890000 0 0x10000>;
964 renesas,vsps = <&vspd 0>;
969 #size-cells = <0>;
971 port@0 {
972 reg = <0>;
986 reg = <0 0x11010000 0 0x10000>;
991 #power-domain-cells = <0>;
996 reg = <0 0x11020000 0 0x10000>;
1008 reg = <0 0x11030000 0 0x10000>;
1014 gpio-ranges = <&pinctrl 0 0 392>;
1026 #address-cells = <0>;
1028 reg = <0 0x110a0000 0 0x10000>;
1029 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
1087 "bus-err", "ec7tie1-0", "ec7tie2-0",
1088 "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
1100 reg = <0 0x11820000 0 0x10000>,
1101 <0 0x11830000 0 0x10000>;
1138 reg = <0x0 0x11840000 0x0 0x10000>;
1159 #address-cells = <0>;
1161 reg = <0x0 0x11900000 0 0x20000>,
1162 <0x0 0x11940000 0 0x40000>;
1169 reg = <0x0 0x11c00000 0 0x10000>;
1185 reg = <0x0 0x11c10000 0 0x10000>;
1201 reg = <0 0x11c20000 0 0x10000>;
1214 #size-cells = <0>;
1221 reg = <0 0x11c30000 0 0x10000>;
1234 #size-cells = <0>;
1241 reg = <0 0x11c40000 0 0x10000>;
1255 reg = <0 0x11c50000 0 0x100>;
1259 resets = <&phyrst 0>,
1269 reg = <0 0x11c70000 0 0x100>;
1283 reg = <0 0x11c50100 0 0x100>;
1287 resets = <&phyrst 0>,
1298 reg = <0 0x11c70100 0 0x100>;
1314 reg = <0 0x11c50200 0 0x700>;
1318 resets = <&phyrst 0>;
1327 reg = <0 0x11c70200 0 0x700>;
1340 reg = <0 0x11c60000 0 0x10000>;
1347 resets = <&phyrst 0>,
1359 reg = <0 0x12800800 0 0x400>;
1374 reg = <0 0x12800C00 0 0x400>;
1389 reg = <0x0 0x12801000 0x0 0x400>;
1400 reg = <0x0 0x12801400 0x0 0x400>;
1411 reg = <0x0 0x12801800 0x0 0x400>;
1424 thermal-sensors = <&tsu 0>;
1430 cooling-device = <&cpu0 0 2>;