Lines Matching +full:0 +full:x10059400
18 #clock-cells = <0>;
20 clock-frequency = <0>;
25 #clock-cells = <0>;
27 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
40 #clock-cells = <0>;
42 clock-frequency = <0>;
45 cluster0_opp: opp-table-0 {
74 #size-cells = <0>;
87 cpu0: cpu@0 {
89 reg = <0>;
100 reg = <0x100>;
108 L3_CA55: cache-controller-0 {
111 cache-size = <0x40000>;
180 reg = <0 0x10001200 0 0xb00>;
250 reg = <0 0x10049c00 0 0x400>;
260 dmas = <&dmac 0x2655>, <&dmac 0x2656>;
263 #sound-dai-cells = <0>;
270 reg = <0 0x1004a000 0 0x400>;
280 dmas = <&dmac 0x2659>, <&dmac 0x265a>;
283 #sound-dai-cells = <0>;
290 reg = <0 0x1004a400 0 0x400>;
299 dmas = <&dmac 0x265f>;
302 #sound-dai-cells = <0>;
309 reg = <0 0x1004a800 0 0x400>;
319 dmas = <&dmac 0x2661>, <&dmac 0x2662>;
322 #sound-dai-cells = <0>;
328 reg = <0 0x1004ac00 0 0x400>;
335 dmas = <&dmac 0x2e95>, <&dmac 0x2e96>;
340 #size-cells = <0>;
346 reg = <0 0x1004b000 0 0x400>;
353 dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>;
358 #size-cells = <0>;
364 reg = <0 0x1004b400 0 0x400>;
371 dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>;
376 #size-cells = <0>;
382 reg = <0 0x1004b800 0 0x400>;
400 reg = <0 0x1004bc00 0 0x400>;
418 reg = <0 0x1004c000 0 0x400>;
436 reg = <0 0x1004c400 0 0x400>;
454 reg = <0 0x1004c800 0 0x400>;
472 reg = <0 0x1004d000 0 0x400>;
487 reg = <0 0x1004d400 0 0x400>;
502 reg = <0 0x10050000 0 0x8000>;
536 #size-cells = <0>;
538 reg = <0 0x10058000 0 0x400>;
558 #size-cells = <0>;
560 reg = <0 0x10058400 0 0x400>;
580 #size-cells = <0>;
582 reg = <0 0x10058800 0 0x400>;
602 #size-cells = <0>;
604 reg = <0 0x10058c00 0 0x400>;
624 reg = <0 0x10059000 0 0x400>;
636 #size-cells = <0>;
638 channel@0 {
639 reg = <0>;
667 reg = <0 0x10059400 0 0x400>;
677 reg = <0 0x10060000 0 0x10000>,
678 <0 0x20000000 0 0x10000000>,
679 <0 0x10070000 0 0x10000>;
687 #size-cells = <0>;
693 reg = <0 0x10830000 0 0x400>;
710 #size-cells = <0>;
712 port@0 {
714 #size-cells = <0>;
716 reg = <0>;
717 cruparallel: endpoint@0 {
718 reg = <0>;
724 #size-cells = <0>;
727 crucsi2: endpoint@0 {
728 reg = <0>;
737 reg = <0 0x10830400 0 0xfc00>;
751 #size-cells = <0>;
753 port@0 {
754 reg = <0>;
759 #size-cells = <0>;
762 csi2cru: endpoint@0 {
763 reg = <0>;
773 reg = <0 0x10850000 0 0x20000>;
799 #size-cells = <0>;
801 port@0 {
802 reg = <0>;
816 reg = <0 0x10870000 0 0x10000>;
830 reg = <0 0x10880000 0 0x10000>;
841 reg = <0 0x10890000 0 0x10000>;
849 renesas,vsps = <&vspd 0>;
854 #size-cells = <0>;
856 port@0 {
857 reg = <0>;
871 reg = <0 0x11010000 0 0x10000>;
876 #power-domain-cells = <0>;
881 reg = <0 0x11020000 0 0x10000>;
893 reg = <0 0x11030000 0 0x10000>;
899 gpio-ranges = <&pinctrl 0 0 392>;
911 #address-cells = <0>;
913 reg = <0 0x110a0000 0 0x10000>;
914 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
972 "bus-err", "ec7tie1-0", "ec7tie2-0",
973 "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
985 reg = <0 0x11820000 0 0x10000>,
986 <0 0x11830000 0 0x10000>;
1023 reg = <0x0 0x11840000 0x0 0x10000>;
1044 #address-cells = <0>;
1046 reg = <0x0 0x11900000 0 0x20000>,
1047 <0x0 0x11940000 0 0x40000>;
1054 reg = <0x0 0x11c00000 0 0x10000>;
1070 reg = <0x0 0x11c10000 0 0x10000>;
1086 reg = <0 0x11c20000 0 0x10000>;
1099 #size-cells = <0>;
1106 reg = <0 0x11c30000 0 0x10000>;
1119 #size-cells = <0>;
1126 reg = <0 0x11c40000 0 0x10000>;
1140 reg = <0 0x11c50000 0 0x100>;
1144 resets = <&phyrst 0>,
1154 reg = <0 0x11c70000 0 0x100>;
1168 reg = <0 0x11c50100 0 0x100>;
1172 resets = <&phyrst 0>,
1183 reg = <0 0x11c70100 0 0x100>;
1199 reg = <0 0x11c50200 0 0x700>;
1203 resets = <&phyrst 0>;
1212 reg = <0 0x11c70200 0 0x700>;
1225 reg = <0 0x11c60000 0 0x10000>;
1232 resets = <&phyrst 0>,
1244 reg = <0 0x12800800 0 0x400>;
1259 reg = <0 0x12800C00 0 0x400>;
1274 reg = <0x0 0x12801000 0x0 0x400>;
1285 reg = <0x0 0x12801400 0x0 0x400>;
1296 reg = <0x0 0x12801800 0x0 0x400>;
1309 thermal-sensors = <&tsu 0>;
1315 cooling-device = <&cpu0 0 2>;