Lines Matching +full:cache +full:- +full:unified
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the R-Car X5H (R8A78000) SoC
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
14 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <0>;
20 cpu-map {
143 compatible = "arm,cortex-a720ae";
146 next-level-cache = <&L2_CA720_0>;
150 compatible = "arm,cortex-a720ae";
153 next-level-cache = <&L2_CA720_1>;
157 compatible = "arm,cortex-a720ae";
160 next-level-cache = <&L2_CA720_2>;
164 compatible = "arm,cortex-a720ae";
167 next-level-cache = <&L2_CA720_3>;
171 compatible = "arm,cortex-a720ae";
174 next-level-cache = <&L2_CA720_4>;
178 compatible = "arm,cortex-a720ae";
181 next-level-cache = <&L2_CA720_5>;
185 compatible = "arm,cortex-a720ae";
188 next-level-cache = <&L2_CA720_6>;
192 compatible = "arm,cortex-a720ae";
195 next-level-cache = <&L2_CA720_7>;
199 compatible = "arm,cortex-a720ae";
202 next-level-cache = <&L2_CA720_8>;
206 compatible = "arm,cortex-a720ae";
209 next-level-cache = <&L2_CA720_9>;
213 compatible = "arm,cortex-a720ae";
216 next-level-cache = <&L2_CA720_10>;
220 compatible = "arm,cortex-a720ae";
223 next-level-cache = <&L2_CA720_11>;
227 compatible = "arm,cortex-a720ae";
230 next-level-cache = <&L2_CA720_12>;
234 compatible = "arm,cortex-a720ae";
237 next-level-cache = <&L2_CA720_13>;
241 compatible = "arm,cortex-a720ae";
244 next-level-cache = <&L2_CA720_14>;
248 compatible = "arm,cortex-a720ae";
251 next-level-cache = <&L2_CA720_15>;
255 compatible = "arm,cortex-a720ae";
258 next-level-cache = <&L2_CA720_16>;
262 compatible = "arm,cortex-a720ae";
265 next-level-cache = <&L2_CA720_17>;
269 compatible = "arm,cortex-a720ae";
272 next-level-cache = <&L2_CA720_18>;
276 compatible = "arm,cortex-a720ae";
279 next-level-cache = <&L2_CA720_19>;
283 compatible = "arm,cortex-a720ae";
286 next-level-cache = <&L2_CA720_20>;
290 compatible = "arm,cortex-a720ae";
293 next-level-cache = <&L2_CA720_21>;
297 compatible = "arm,cortex-a720ae";
300 next-level-cache = <&L2_CA720_22>;
304 compatible = "arm,cortex-a720ae";
307 next-level-cache = <&L2_CA720_23>;
311 compatible = "arm,cortex-a720ae";
314 next-level-cache = <&L2_CA720_24>;
318 compatible = "arm,cortex-a720ae";
321 next-level-cache = <&L2_CA720_25>;
325 compatible = "arm,cortex-a720ae";
328 next-level-cache = <&L2_CA720_26>;
332 compatible = "arm,cortex-a720ae";
335 next-level-cache = <&L2_CA720_27>;
339 compatible = "arm,cortex-a720ae";
342 next-level-cache = <&L2_CA720_28>;
346 compatible = "arm,cortex-a720ae";
349 next-level-cache = <&L2_CA720_29>;
353 compatible = "arm,cortex-a720ae";
356 next-level-cache = <&L2_CA720_30>;
360 compatible = "arm,cortex-a720ae";
363 next-level-cache = <&L2_CA720_31>;
366 L2_CA720_0: cache-controller-200 {
367 compatible = "cache";
368 cache-unified;
369 cache-level = <2>;
370 next-level-cache = <&L3_CA720_0>;
373 L2_CA720_1: cache-controller-201 {
374 compatible = "cache";
375 cache-unified;
376 cache-level = <2>;
377 next-level-cache = <&L3_CA720_0>;
380 L2_CA720_2: cache-controller-202 {
381 compatible = "cache";
382 cache-unified;
383 cache-level = <2>;
384 next-level-cache = <&L3_CA720_0>;
387 L2_CA720_3: cache-controller-203 {
388 compatible = "cache";
389 cache-unified;
390 cache-level = <2>;
391 next-level-cache = <&L3_CA720_0>;
394 L2_CA720_4: cache-controller-204 {
395 compatible = "cache";
396 cache-unified;
397 cache-level = <2>;
398 next-level-cache = <&L3_CA720_1>;
401 L2_CA720_5: cache-controller-205 {
402 compatible = "cache";
403 cache-unified;
404 cache-level = <2>;
405 next-level-cache = <&L3_CA720_1>;
408 L2_CA720_6: cache-controller-206 {
409 compatible = "cache";
410 cache-unified;
411 cache-level = <2>;
412 next-level-cache = <&L3_CA720_1>;
415 L2_CA720_7: cache-controller-207 {
416 compatible = "cache";
417 cache-unified;
418 cache-level = <2>;
419 next-level-cache = <&L3_CA720_1>;
422 L2_CA720_8: cache-controller-208 {
423 compatible = "cache";
424 cache-unified;
425 cache-level = <2>;
426 next-level-cache = <&L3_CA720_2>;
429 L2_CA720_9: cache-controller-209 {
430 compatible = "cache";
431 cache-unified;
432 cache-level = <2>;
433 next-level-cache = <&L3_CA720_2>;
436 L2_CA720_10: cache-controller-210 {
437 compatible = "cache";
438 cache-unified;
439 cache-level = <2>;
440 next-level-cache = <&L3_CA720_2>;
443 L2_CA720_11: cache-controller-211 {
444 compatible = "cache";
445 cache-unified;
446 cache-level = <2>;
447 next-level-cache = <&L3_CA720_2>;
450 L2_CA720_12: cache-controller-212 {
451 compatible = "cache";
452 cache-unified;
453 cache-level = <2>;
454 next-level-cache = <&L3_CA720_3>;
457 L2_CA720_13: cache-controller-213 {
458 compatible = "cache";
459 cache-unified;
460 cache-level = <2>;
461 next-level-cache = <&L3_CA720_3>;
464 L2_CA720_14: cache-controller-214 {
465 compatible = "cache";
466 cache-unified;
467 cache-level = <2>;
468 next-level-cache = <&L3_CA720_3>;
471 L2_CA720_15: cache-controller-215 {
472 compatible = "cache";
473 cache-unified;
474 cache-level = <2>;
475 next-level-cache = <&L3_CA720_3>;
478 L2_CA720_16: cache-controller-216 {
479 compatible = "cache";
480 cache-unified;
481 cache-level = <2>;
482 next-level-cache = <&L3_CA720_4>;
485 L2_CA720_17: cache-controller-217 {
486 compatible = "cache";
487 cache-unified;
488 cache-level = <2>;
489 next-level-cache = <&L3_CA720_4>;
492 L2_CA720_18: cache-controller-218 {
493 compatible = "cache";
494 cache-unified;
495 cache-level = <2>;
496 next-level-cache = <&L3_CA720_4>;
499 L2_CA720_19: cache-controller-219 {
500 compatible = "cache";
501 cache-unified;
502 cache-level = <2>;
503 next-level-cache = <&L3_CA720_4>;
506 L2_CA720_20: cache-controller-220 {
507 compatible = "cache";
508 cache-unified;
509 cache-level = <2>;
510 next-level-cache = <&L3_CA720_5>;
513 L2_CA720_21: cache-controller-221 {
514 compatible = "cache";
515 cache-unified;
516 cache-level = <2>;
517 next-level-cache = <&L3_CA720_5>;
520 L2_CA720_22: cache-controller-222 {
521 compatible = "cache";
522 cache-unified;
523 cache-level = <2>;
524 next-level-cache = <&L3_CA720_5>;
527 L2_CA720_23: cache-controller-223 {
528 compatible = "cache";
529 cache-unified;
530 cache-level = <2>;
531 next-level-cache = <&L3_CA720_5>;
534 L2_CA720_24: cache-controller-224 {
535 compatible = "cache";
536 cache-unified;
537 cache-level = <2>;
538 next-level-cache = <&L3_CA720_6>;
541 L2_CA720_25: cache-controller-225 {
542 compatible = "cache";
543 cache-unified;
544 cache-level = <2>;
545 next-level-cache = <&L3_CA720_6>;
548 L2_CA720_26: cache-controller-226 {
549 compatible = "cache";
550 cache-unified;
551 cache-level = <2>;
552 next-level-cache = <&L3_CA720_6>;
555 L2_CA720_27: cache-controller-227 {
556 compatible = "cache";
557 cache-unified;
558 cache-level = <2>;
559 next-level-cache = <&L3_CA720_6>;
562 L2_CA720_28: cache-controller-228 {
563 compatible = "cache";
564 cache-unified;
565 cache-level = <2>;
566 next-level-cache = <&L3_CA720_7>;
569 L2_CA720_29: cache-controller-229 {
570 compatible = "cache";
571 cache-unified;
572 cache-level = <2>;
573 next-level-cache = <&L3_CA720_7>;
576 L2_CA720_30: cache-controller-230 {
577 compatible = "cache";
578 cache-unified;
579 cache-level = <2>;
580 next-level-cache = <&L3_CA720_7>;
583 L2_CA720_31: cache-controller-231 {
584 compatible = "cache";
585 cache-unified;
586 cache-level = <2>;
587 next-level-cache = <&L3_CA720_7>;
590 L3_CA720_0: cache-controller-30 {
591 compatible = "cache";
592 cache-unified;
593 cache-level = <3>;
596 L3_CA720_1: cache-controller-31 {
597 compatible = "cache";
598 cache-unified;
599 cache-level = <3>;
602 L3_CA720_2: cache-controller-32 {
603 compatible = "cache";
604 cache-unified;
605 cache-level = <3>;
608 L3_CA720_3: cache-controller-33 {
609 compatible = "cache";
610 cache-unified;
611 cache-level = <3>;
614 L3_CA720_4: cache-controller-34 {
615 compatible = "cache";
616 cache-unified;
617 cache-level = <3>;
620 L3_CA720_5: cache-controller-35 {
621 compatible = "cache";
622 cache-unified;
623 cache-level = <3>;
626 L3_CA720_6: cache-controller-36 {
627 compatible = "cache";
628 cache-unified;
629 cache-level = <3>;
632 L3_CA720_7: cache-controller-37 {
633 compatible = "cache";
634 cache-unified;
635 cache-level = <3>;
644 dummy_clk_sgasyncd16: dummy-clk-sgasyncd16 {
645 compatible = "fixed-clock";
646 #clock-cells = <0>;
647 clock-frequency = <66666000>;
650 dummy_clk_sgasyncd4: dummy-clk-sgasyncd4 {
651 compatible = "fixed-clock";
652 #clock-cells = <0>;
653 clock-frequency = <266660000>;
656 extal_clk: extal-clk {
657 compatible = "fixed-clock";
658 #clock-cells = <0>;
659 /* clock-frequency must be set on board */
662 extalr_clk: extalr-clk {
663 compatible = "fixed-clock";
664 #clock-cells = <0>;
665 /* clock-frequency must be set on board */
668 /* External SCIF clock - to be overridden by boards that provide it */
669 scif_clk: scif-clk {
670 compatible = "fixed-clock";
671 #clock-cells = <0>;
672 clock-frequency = <0>; /* optional */
676 compatible = "simple-bus";
677 #address-cells = <2>;
678 #size-cells = <2>;
686 /* Application Processors manage View-1 of a GIC-720AE */
687 gic: interrupt-controller@39000000 {
688 compatible = "arm,gic-v3";
689 #interrupt-cells = <3>;
690 #address-cells = <0>;
691 interrupt-controller;
698 compatible = "renesas,scif-r8a78000",
699 "renesas,rcar-gen5-scif", "renesas,scif";
703 clock-names = "fck", "brg_int", "scif_clk";
708 compatible = "renesas,scif-r8a78000",
709 "renesas,rcar-gen5-scif", "renesas,scif";
713 clock-names = "fck", "brg_int", "scif_clk";
718 compatible = "renesas,scif-r8a78000",
719 "renesas,rcar-gen5-scif", "renesas,scif";
723 clock-names = "fck", "brg_int", "scif_clk";
728 compatible = "renesas,scif-r8a78000",
729 "renesas,rcar-gen5-scif", "renesas,scif";
733 clock-names = "fck", "brg_int", "scif_clk";
738 compatible = "renesas,hscif-r8a78000",
739 "renesas,rcar-gen5-hscif", "renesas,hscif";
743 clock-names = "fck", "brg_int", "scif_clk";
748 compatible = "renesas,hscif-r8a78000",
749 "renesas,rcar-gen5-hscif", "renesas,hscif";
753 clock-names = "fck", "brg_int", "scif_clk";
758 compatible = "renesas,hscif-r8a78000",
759 "renesas,rcar-gen5-hscif", "renesas,hscif";
763 clock-names = "fck", "brg_int", "scif_clk";
768 compatible = "renesas,hscif-r8a78000",
769 "renesas,rcar-gen5-hscif", "renesas,hscif";
773 clock-names = "fck", "brg_int", "scif_clk";
779 compatible = "arm,armv8-timer";
785 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";