Lines Matching +full:0 +full:xe61be000
20 #clock-cells = <0>;
21 clock-frequency = <0>;
27 #clock-cells = <0>;
28 clock-frequency = <0>;
31 cluster0_opp: opp-table-0 {
48 #size-cells = <0>;
67 a76_0: cpu@0 {
69 reg = <0>;
81 reg = <0x100>;
93 reg = <0x200>;
105 reg = <0x300>;
118 CPU_SLEEP_0: cpu-sleep-0 {
120 arm,psci-suspend-param = <0x0010000>;
138 #clock-cells = <0>;
140 clock-frequency = <0>;
146 #clock-cells = <0>;
148 clock-frequency = <0>;
154 #clock-cells = <0>;
156 clock-frequency = <0>;
172 #clock-cells = <0>;
173 clock-frequency = <0>;
178 #clock-cells = <0>;
179 clock-frequency = <0>;
194 reg = <0 0xe6020000 0 0x0c>;
204 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
205 <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
206 <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
207 <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>;
214 reg = <0 0xe6050180 0 0x54>;
218 gpio-ranges = <&pfc 0 0 19>;
229 reg = <0 0xe6050980 0 0x54>;
233 gpio-ranges = <&pfc 0 32 30>;
244 reg = <0 0xe6058180 0 0x54>;
248 gpio-ranges = <&pfc 0 64 20>;
259 reg = <0 0xe6058980 0 0x54>;
263 gpio-ranges = <&pfc 0 96 32>;
274 reg = <0 0xe6060180 0 0x54>;
278 gpio-ranges = <&pfc 0 128 25>;
289 reg = <0 0xe6060980 0 0x54>;
293 gpio-ranges = <&pfc 0 160 21>;
304 reg = <0 0xe6061180 0 0x54>;
308 gpio-ranges = <&pfc 0 192 21>;
319 reg = <0 0xe6061980 0 0x54>;
323 gpio-ranges = <&pfc 0 224 21>;
334 reg = <0 0xe60f0000 0 0x1004>;
347 reg = <0 0xe6130000 0 0x1004>;
366 reg = <0 0xe6140000 0 0x1004>;
385 reg = <0 0xe6148000 0 0x1004>;
403 reg = <0 0xe6150000 0 0x4000>;
407 #power-domain-cells = <0>;
414 reg = <0 0xe6160000 0 0x4000>;
420 reg = <0 0xe6180000 0 0x4000>;
426 reg = <0 0xe6198000 0 0x200>,
427 <0 0xe61a0000 0 0x200>;
436 reg = <0 0xe61be000 0 0x1000>, <0 0xe61bf000 0 0x1000>;
443 reg = <0 0xe61c0000 0 0x200>;
444 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
457 reg = <0 0xe61e0000 0 0x30>;
471 reg = <0 0xe6fc0000 0 0x30>;
486 reg = <0 0xe6fd0000 0 0x30>;
501 reg = <0 0xe6fe0000 0 0x30>;
516 reg = <0 0xffc00000 0 0x30>;
532 reg = <0 0xe6500000 0 0x40>;
537 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
538 <&dmac2 0x91>, <&dmac2 0x90>;
542 #size-cells = <0>;
549 reg = <0 0xe6508000 0 0x40>;
554 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
555 <&dmac2 0x93>, <&dmac2 0x92>;
559 #size-cells = <0>;
566 reg = <0 0xe6510000 0 0x40>;
571 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
572 <&dmac2 0x95>, <&dmac2 0x94>;
576 #size-cells = <0>;
583 reg = <0 0xe66d0000 0 0x40>;
588 dmas = <&dmac1 0x97>, <&dmac1 0x96>,
589 <&dmac2 0x97>, <&dmac2 0x96>;
593 #size-cells = <0>;
600 reg = <0 0xe6540000 0 0x60>;
608 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
609 <&dmac2 0x31>, <&dmac2 0x30>;
617 reg = <0 0xe6550000 0 0x60>;
625 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
626 <&dmac2 0x33>, <&dmac2 0x32>;
634 reg = <0 0xe6560000 0 0x60>;
642 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
643 <&dmac2 0x35>, <&dmac2 0x34>;
651 reg = <0 0xe66a0000 0 0x60>;
659 dmas = <&dmac1 0x37>, <&dmac1 0x36>,
660 <&dmac2 0x37>, <&dmac2 0x36>;
668 reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,
669 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
670 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
671 <0 0xfe000000 0 0x400000>;
687 bus-range = <0x00 0xff>;
689 ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>,
690 <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>;
691 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
693 interrupt-map-mask = <0 0 0 7>;
694 interrupt-map = <0 0 0 1 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
695 <0 0 0 2 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
696 <0 0 0 3 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
697 <0 0 0 4 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>;
705 reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>,
706 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
707 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
708 <0 0xfe000000 0 0x400000>;
728 reg = <0 0xe6660000 0 0x8500>;
762 reg = <0 0xe6800000 0 0x1000>;
800 rx-internal-delay-ps = <0>;
801 tx-internal-delay-ps = <0>;
802 iommus = <&ipmmu_hc 0>;
809 reg = <0 0xe6810000 0 0x1000>;
847 rx-internal-delay-ps = <0>;
848 tx-internal-delay-ps = <0>;
856 reg = <0 0xe6820000 0 0x1000>;
894 rx-internal-delay-ps = <0>;
895 tx-internal-delay-ps = <0>;
902 reg = <0 0xe6e30000 0 0x10>;
912 reg = <0 0xe6e31000 0 0x10>;
922 reg = <0 0xe6e32000 0 0x10>;
932 reg = <0 0xe6e33000 0 0x10>;
942 reg = <0 0xe6e34000 0 0x10>;
953 reg = <0 0xe6e60000 0 64>;
961 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
962 <&dmac2 0x51>, <&dmac2 0x50>;
970 reg = <0 0xe6e68000 0 64>;
978 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
979 <&dmac2 0x53>, <&dmac2 0x52>;
987 reg = <0 0xe6c50000 0 64>;
995 dmas = <&dmac1 0x57>, <&dmac1 0x56>,
996 <&dmac2 0x57>, <&dmac2 0x56>;
1004 reg = <0 0xe6c40000 0 64>;
1012 dmas = <&dmac1 0x59>, <&dmac1 0x58>,
1013 <&dmac2 0x59>, <&dmac2 0x58>;
1021 reg = <0 0xe6e90000 0 0x0064>;
1024 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1025 <&dmac2 0x41>, <&dmac2 0x40>;
1030 #size-cells = <0>;
1037 reg = <0 0xe6ea0000 0 0x0064>;
1040 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1041 <&dmac2 0x43>, <&dmac2 0x42>;
1046 #size-cells = <0>;
1053 reg = <0 0xe6c00000 0 0x0064>;
1056 dmas = <&dmac1 0x45>, <&dmac1 0x44>,
1057 <&dmac2 0x45>, <&dmac2 0x44>;
1062 #size-cells = <0>;
1069 reg = <0 0xe6c10000 0 0x0064>;
1072 dmas = <&dmac1 0x47>, <&dmac1 0x46>,
1073 <&dmac2 0x47>, <&dmac2 0x46>;
1078 #size-cells = <0>;
1085 reg = <0 0xe6c20000 0 0x0064>;
1088 dmas = <&dmac1 0x49>, <&dmac1 0x48>,
1089 <&dmac2 0x49>, <&dmac2 0x48>;
1094 #size-cells = <0>;
1101 reg = <0 0xe6c28000 0 0x0064>;
1104 dmas = <&dmac1 0x4b>, <&dmac1 0x4a>,
1105 <&dmac2 0x4b>, <&dmac2 0x4a>;
1110 #size-cells = <0>;
1117 reg = <0 0xe6ef0000 0 0x1000>;
1122 renesas,id = <0>;
1127 #size-cells = <0>;
1131 #size-cells = <0>;
1135 vin00isp0: endpoint@0 {
1136 reg = <0>;
1146 reg = <0 0xe6ef1000 0 0x1000>;
1156 #size-cells = <0>;
1160 #size-cells = <0>;
1164 vin01isp0: endpoint@0 {
1165 reg = <0>;
1175 reg = <0 0xe6ef2000 0 0x1000>;
1185 #size-cells = <0>;
1189 #size-cells = <0>;
1193 vin02isp0: endpoint@0 {
1194 reg = <0>;
1204 reg = <0 0xe6ef3000 0 0x1000>;
1214 #size-cells = <0>;
1218 #size-cells = <0>;
1222 vin03isp0: endpoint@0 {
1223 reg = <0>;
1233 reg = <0 0xe6ef4000 0 0x1000>;
1243 #size-cells = <0>;
1247 #size-cells = <0>;
1251 vin04isp0: endpoint@0 {
1252 reg = <0>;
1262 reg = <0 0xe6ef5000 0 0x1000>;
1272 #size-cells = <0>;
1276 #size-cells = <0>;
1280 vin05isp0: endpoint@0 {
1281 reg = <0>;
1291 reg = <0 0xe6ef6000 0 0x1000>;
1301 #size-cells = <0>;
1305 #size-cells = <0>;
1309 vin06isp0: endpoint@0 {
1310 reg = <0>;
1320 reg = <0 0xe6ef7000 0 0x1000>;
1330 #size-cells = <0>;
1334 #size-cells = <0>;
1338 vin07isp0: endpoint@0 {
1339 reg = <0>;
1349 reg = <0 0xe6ef8000 0 0x1000>;
1359 #size-cells = <0>;
1363 #size-cells = <0>;
1378 reg = <0 0xe6ef9000 0 0x1000>;
1388 #size-cells = <0>;
1392 #size-cells = <0>;
1407 reg = <0 0xe6efa000 0 0x1000>;
1417 #size-cells = <0>;
1421 #size-cells = <0>;
1436 reg = <0 0xe6efb000 0 0x1000>;
1446 #size-cells = <0>;
1450 #size-cells = <0>;
1465 reg = <0 0xe6efc000 0 0x1000>;
1475 #size-cells = <0>;
1479 #size-cells = <0>;
1494 reg = <0 0xe6efd000 0 0x1000>;
1504 #size-cells = <0>;
1508 #size-cells = <0>;
1523 reg = <0 0xe6efe000 0 0x1000>;
1533 #size-cells = <0>;
1537 #size-cells = <0>;
1552 reg = <0 0xe6eff000 0 0x1000>;
1562 #size-cells = <0>;
1566 #size-cells = <0>;
1581 reg = <0 0xe7350000 0 0x1000>,
1582 <0 0xe7300000 0 0x10000>;
1611 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
1624 reg = <0 0xe7351000 0 0x1000>,
1625 <0 0xe7310000 0 0x10000>;
1652 reg = <0 0xec400000 0 0x40000>,
1653 <0 0xec540000 0 0x1000>,
1654 <0 0xec541000 0 0x050>,
1655 <0 0xec5a0000 0 0x020>;
1658 clock-names = "ssiu.0", "ssi.0", "clkin";
1660 #clock-cells = <0>;
1662 #sound-dai-cells = <0>;
1666 reset-names = "ssiu.0", "ssi.0";
1670 ssiu00: ssiu-0 {
1671 dmas = <&dmac1 0x6e>, <&dmac1 0x6f>;
1675 dmas = <&dmac1 0x6c>, <&dmac1 0x6d>;
1679 dmas = <&dmac1 0x6a>, <&dmac1 0x6b>;
1683 dmas = <&dmac1 0x68>, <&dmac1 0x69>;
1687 dmas = <&dmac1 0x66>, <&dmac1 0x67>;
1691 dmas = <&dmac1 0x64>, <&dmac1 0x65>;
1695 dmas = <&dmac1 0x62>, <&dmac1 0x63>;
1699 dmas = <&dmac1 0x60>, <&dmac1 0x61>;
1705 ssi0: ssi-0 {
1714 reg = <0 0xee140000 0 0x2000>;
1729 reg = <0 0xee200000 0 0x200>,
1730 <0 0x08000000 0 0x04000000>,
1731 <0 0xee208000 0 0x100>;
1738 #size-cells = <0>;
1745 reg = <0 0xee480000 0 0x20000>;
1754 reg = <0 0xee4c0000 0 0x20000>;
1763 reg = <0 0xeed00000 0 0x20000>;
1772 reg = <0 0xeed40000 0 0x20000>;
1781 reg = <0 0xeed80000 0 0x20000>;
1790 reg = <0 0xeedc0000 0 0x20000>;
1799 reg = <0 0xeee00000 0 0x20000>;
1808 reg = <0 0xeee80000 0 0x20000>;
1817 reg = <0 0xeeec0000 0 0x20000>;
1826 reg = <0 0xeef00000 0 0x20000>;
1835 reg = <0 0xeefc0000 0 0x20000>;
1845 #address-cells = <0>;
1847 reg = <0x0 0xf1000000 0 0x20000>,
1848 <0x0 0xf1060000 0 0x110000>;
1854 reg = <0 0xfe500000 0 0x40000>;
1863 #size-cells = <0>;
1865 port@0 {
1866 reg = <0>;
1880 reg = <0 0xfe540000 0 0x40000>;
1889 #size-cells = <0>;
1891 port@0 {
1892 reg = <0>;
1906 reg = <0 0xfea10000 0 0x200>;
1914 reg = <0 0xfedb0000 0 0x200>;
1923 reg = <0 0xfea20000 0 0x8000>;
1933 reg = <0 0xfedd0000 0 0x8000>;
1944 reg = <0 0xfeb00000 0 0x40000>;
1947 clock-names = "du.0";
1950 reset-names = "du.0";
1951 renesas,vsps = <&vspd0 0>;
1957 #size-cells = <0>;
1959 port@0 {
1960 reg = <0>;
1971 reg = <0 0xfed00000 0 0x10000>;
1980 #size-cells = <0>;
1982 port@0 {
1984 #size-cells = <0>;
1986 reg = <0>;
1988 isp0csi40: endpoint@0 {
1989 reg = <0>;
2055 reg = <0 0xfed20000 0 0x10000>;
2064 #size-cells = <0>;
2066 port@0 {
2068 #size-cells = <0>;
2070 reg = <0>;
2138 reg = <0 0xfed80000 0 0x10000>;
2150 #size-cells = <0>;
2152 port@0 {
2153 reg = <0>;
2167 reg = <0 0xfff00044 0 4>;
2176 thermal-sensors = <&tsc 0>;