Lines Matching +full:0 +full:xe6160000
20 #clock-cells = <0>;
21 clock-frequency = <0>;
27 #clock-cells = <0>;
28 clock-frequency = <0>;
31 cluster0_opp: opp-table-0 {
48 #size-cells = <0>;
67 a76_0: cpu@0 {
69 reg = <0>;
81 reg = <0x100>;
93 reg = <0x200>;
105 reg = <0x300>;
118 CPU_SLEEP_0: cpu-sleep-0 {
120 arm,psci-suspend-param = <0x0010000>;
138 #clock-cells = <0>;
140 clock-frequency = <0>;
145 #clock-cells = <0>;
147 clock-frequency = <0>;
163 #clock-cells = <0>;
164 clock-frequency = <0>;
169 #clock-cells = <0>;
170 clock-frequency = <0>;
183 reg = <0 0xe6020000 0 0x0c>;
193 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
194 <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
195 <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
196 <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>;
202 reg = <0 0xe6050180 0 0x54>;
206 gpio-ranges = <&pfc 0 0 19>;
217 reg = <0 0xe6050980 0 0x54>;
221 gpio-ranges = <&pfc 0 32 30>;
232 reg = <0 0xe6058180 0 0x54>;
236 gpio-ranges = <&pfc 0 64 20>;
247 reg = <0 0xe6058980 0 0x54>;
251 gpio-ranges = <&pfc 0 96 32>;
262 reg = <0 0xe6060180 0 0x54>;
266 gpio-ranges = <&pfc 0 128 25>;
277 reg = <0 0xe6060980 0 0x54>;
281 gpio-ranges = <&pfc 0 160 21>;
292 reg = <0 0xe6061180 0 0x54>;
296 gpio-ranges = <&pfc 0 192 21>;
307 reg = <0 0xe6061980 0 0x54>;
311 gpio-ranges = <&pfc 0 224 21>;
322 reg = <0 0xe60f0000 0 0x1004>;
335 reg = <0 0xe6130000 0 0x1004>;
354 reg = <0 0xe6140000 0 0x1004>;
373 reg = <0 0xe6148000 0 0x1004>;
391 reg = <0 0xe6150000 0 0x4000>;
395 #power-domain-cells = <0>;
401 reg = <0 0xe6160000 0 0x4000>;
406 reg = <0 0xe6180000 0 0x4000>;
412 reg = <0 0xe6198000 0 0x200>,
413 <0 0xe61a0000 0 0x200>;
424 reg = <0 0xe61c0000 0 0x200>;
425 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
438 reg = <0 0xe61e0000 0 0x30>;
452 reg = <0 0xe6fc0000 0 0x30>;
467 reg = <0 0xe6fd0000 0 0x30>;
482 reg = <0 0xe6fe0000 0 0x30>;
497 reg = <0 0xffc00000 0 0x30>;
513 reg = <0 0xe6500000 0 0x40>;
518 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
519 <&dmac2 0x91>, <&dmac2 0x90>;
523 #size-cells = <0>;
530 reg = <0 0xe6508000 0 0x40>;
535 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
536 <&dmac2 0x93>, <&dmac2 0x92>;
540 #size-cells = <0>;
547 reg = <0 0xe6510000 0 0x40>;
552 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
553 <&dmac2 0x95>, <&dmac2 0x94>;
557 #size-cells = <0>;
564 reg = <0 0xe66d0000 0 0x40>;
569 dmas = <&dmac1 0x97>, <&dmac1 0x96>,
570 <&dmac2 0x97>, <&dmac2 0x96>;
574 #size-cells = <0>;
581 reg = <0 0xe6540000 0 0x60>;
589 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
590 <&dmac2 0x31>, <&dmac2 0x30>;
598 reg = <0 0xe6550000 0 0x60>;
606 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
607 <&dmac2 0x33>, <&dmac2 0x32>;
615 reg = <0 0xe6560000 0 0x60>;
623 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
624 <&dmac2 0x35>, <&dmac2 0x34>;
632 reg = <0 0xe66a0000 0 0x60>;
640 dmas = <&dmac1 0x37>, <&dmac1 0x36>,
641 <&dmac2 0x37>, <&dmac2 0x36>;
649 reg = <0 0xe6660000 0 0x8500>;
683 reg = <0 0xe6800000 0 0x1000>;
721 rx-internal-delay-ps = <0>;
722 tx-internal-delay-ps = <0>;
723 iommus = <&ipmmu_hc 0>;
725 #size-cells = <0>;
732 reg = <0 0xe6810000 0 0x1000>;
770 rx-internal-delay-ps = <0>;
771 tx-internal-delay-ps = <0>;
774 #size-cells = <0>;
781 reg = <0 0xe6820000 0 0x1000>;
819 rx-internal-delay-ps = <0>;
820 tx-internal-delay-ps = <0>;
823 #size-cells = <0>;
829 reg = <0 0xe6e30000 0 0x10>;
839 reg = <0 0xe6e31000 0 0x10>;
849 reg = <0 0xe6e32000 0 0x10>;
859 reg = <0 0xe6e33000 0 0x10>;
869 reg = <0 0xe6e34000 0 0x10>;
880 reg = <0 0xe6e60000 0 64>;
888 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
889 <&dmac2 0x51>, <&dmac2 0x50>;
897 reg = <0 0xe6e68000 0 64>;
905 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
906 <&dmac2 0x53>, <&dmac2 0x52>;
914 reg = <0 0xe6c50000 0 64>;
922 dmas = <&dmac1 0x57>, <&dmac1 0x56>,
923 <&dmac2 0x57>, <&dmac2 0x56>;
931 reg = <0 0xe6c40000 0 64>;
939 dmas = <&dmac1 0x59>, <&dmac1 0x58>,
940 <&dmac2 0x59>, <&dmac2 0x58>;
948 reg = <0 0xe6e90000 0 0x0064>;
951 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
952 <&dmac2 0x41>, <&dmac2 0x40>;
957 #size-cells = <0>;
964 reg = <0 0xe6ea0000 0 0x0064>;
967 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
968 <&dmac2 0x43>, <&dmac2 0x42>;
973 #size-cells = <0>;
980 reg = <0 0xe6c00000 0 0x0064>;
983 dmas = <&dmac1 0x45>, <&dmac1 0x44>,
984 <&dmac2 0x45>, <&dmac2 0x44>;
989 #size-cells = <0>;
996 reg = <0 0xe6c10000 0 0x0064>;
999 dmas = <&dmac1 0x47>, <&dmac1 0x46>,
1000 <&dmac2 0x47>, <&dmac2 0x46>;
1005 #size-cells = <0>;
1012 reg = <0 0xe6c20000 0 0x0064>;
1015 dmas = <&dmac1 0x49>, <&dmac1 0x48>,
1016 <&dmac2 0x49>, <&dmac2 0x48>;
1021 #size-cells = <0>;
1028 reg = <0 0xe6c28000 0 0x0064>;
1031 dmas = <&dmac1 0x4b>, <&dmac1 0x4a>,
1032 <&dmac2 0x4b>, <&dmac2 0x4a>;
1037 #size-cells = <0>;
1044 reg = <0 0xe6ef0000 0 0x1000>;
1049 renesas,id = <0>;
1054 #size-cells = <0>;
1058 #size-cells = <0>;
1062 vin00isp0: endpoint@0 {
1063 reg = <0>;
1073 reg = <0 0xe6ef1000 0 0x1000>;
1083 #size-cells = <0>;
1087 #size-cells = <0>;
1091 vin01isp0: endpoint@0 {
1092 reg = <0>;
1102 reg = <0 0xe6ef2000 0 0x1000>;
1112 #size-cells = <0>;
1116 #size-cells = <0>;
1120 vin02isp0: endpoint@0 {
1121 reg = <0>;
1131 reg = <0 0xe6ef3000 0 0x1000>;
1141 #size-cells = <0>;
1145 #size-cells = <0>;
1149 vin03isp0: endpoint@0 {
1150 reg = <0>;
1160 reg = <0 0xe6ef4000 0 0x1000>;
1170 #size-cells = <0>;
1174 #size-cells = <0>;
1178 vin04isp0: endpoint@0 {
1179 reg = <0>;
1189 reg = <0 0xe6ef5000 0 0x1000>;
1199 #size-cells = <0>;
1203 #size-cells = <0>;
1207 vin05isp0: endpoint@0 {
1208 reg = <0>;
1218 reg = <0 0xe6ef6000 0 0x1000>;
1228 #size-cells = <0>;
1232 #size-cells = <0>;
1236 vin06isp0: endpoint@0 {
1237 reg = <0>;
1247 reg = <0 0xe6ef7000 0 0x1000>;
1257 #size-cells = <0>;
1261 #size-cells = <0>;
1265 vin07isp0: endpoint@0 {
1266 reg = <0>;
1276 reg = <0 0xe6ef8000 0 0x1000>;
1286 #size-cells = <0>;
1290 #size-cells = <0>;
1305 reg = <0 0xe6ef9000 0 0x1000>;
1315 #size-cells = <0>;
1319 #size-cells = <0>;
1334 reg = <0 0xe6efa000 0 0x1000>;
1344 #size-cells = <0>;
1348 #size-cells = <0>;
1363 reg = <0 0xe6efb000 0 0x1000>;
1373 #size-cells = <0>;
1377 #size-cells = <0>;
1392 reg = <0 0xe6efc000 0 0x1000>;
1402 #size-cells = <0>;
1406 #size-cells = <0>;
1421 reg = <0 0xe6efd000 0 0x1000>;
1431 #size-cells = <0>;
1435 #size-cells = <0>;
1450 reg = <0 0xe6efe000 0 0x1000>;
1460 #size-cells = <0>;
1464 #size-cells = <0>;
1479 reg = <0 0xe6eff000 0 0x1000>;
1489 #size-cells = <0>;
1493 #size-cells = <0>;
1508 reg = <0 0xe7350000 0 0x1000>,
1509 <0 0xe7300000 0 0x10000>;
1538 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
1551 reg = <0 0xe7351000 0 0x1000>,
1552 <0 0xe7310000 0 0x10000>;
1579 reg = <0 0xec400000 0 0x40000>,
1580 <0 0xec540000 0 0x1000>,
1581 <0 0xec541000 0 0x050>,
1582 <0 0xec5a0000 0 0x020>;
1585 clock-names = "ssiu.0", "ssi.0", "clkin";
1587 #clock-cells = <0>;
1589 #sound-dai-cells = <0>;
1593 reset-names = "ssiu.0", "ssi.0";
1597 ssiu00: ssiu-0 {
1598 dmas = <&dmac1 0x6e>, <&dmac1 0x6f>;
1602 dmas = <&dmac1 0x6c>, <&dmac1 0x6d>;
1606 dmas = <&dmac1 0x6a>, <&dmac1 0x6b>;
1610 dmas = <&dmac1 0x68>, <&dmac1 0x69>;
1614 dmas = <&dmac1 0x66>, <&dmac1 0x67>;
1618 dmas = <&dmac1 0x64>, <&dmac1 0x65>;
1622 dmas = <&dmac1 0x62>, <&dmac1 0x63>;
1626 dmas = <&dmac1 0x60>, <&dmac1 0x61>;
1632 ssi0: ssi-0 {
1641 reg = <0 0xee140000 0 0x2000>;
1656 reg = <0 0xee200000 0 0x200>,
1657 <0 0x08000000 0 0x04000000>,
1658 <0 0xee208000 0 0x100>;
1665 #size-cells = <0>;
1672 reg = <0 0xee480000 0 0x20000>;
1681 reg = <0 0xee4c0000 0 0x20000>;
1690 reg = <0 0xeed00000 0 0x20000>;
1699 reg = <0 0xeed40000 0 0x20000>;
1708 reg = <0 0xeed80000 0 0x20000>;
1717 reg = <0 0xeedc0000 0 0x20000>;
1726 reg = <0 0xeee00000 0 0x20000>;
1735 reg = <0 0xeee80000 0 0x20000>;
1744 reg = <0 0xeeec0000 0 0x20000>;
1753 reg = <0 0xeef00000 0 0x20000>;
1762 reg = <0 0xeefc0000 0 0x20000>;
1772 #address-cells = <0>;
1774 reg = <0x0 0xf1000000 0 0x20000>,
1775 <0x0 0xf1060000 0 0x110000>;
1781 reg = <0 0xfe500000 0 0x40000>;
1790 #size-cells = <0>;
1792 port@0 {
1793 reg = <0>;
1807 reg = <0 0xfe540000 0 0x40000>;
1816 #size-cells = <0>;
1818 port@0 {
1819 reg = <0>;
1834 reg = <0 0xfed00000 0 0x10000>;
1843 #size-cells = <0>;
1845 port@0 {
1847 #size-cells = <0>;
1849 reg = <0>;
1851 isp0csi40: endpoint@0 {
1852 reg = <0>;
1918 reg = <0 0xfed20000 0 0x10000>;
1927 #size-cells = <0>;
1929 port@0 {
1931 #size-cells = <0>;
1933 reg = <0>;
2001 reg = <0 0xfff00044 0 4>;
2009 thermal-sensors = <&tsc 0>;