Lines Matching +full:0 +full:xfeb00000
20 #clock-cells = <0>;
21 clock-frequency = <0>;
27 #clock-cells = <0>;
28 clock-frequency = <0>;
31 cluster0_opp: opp-table-0 {
66 #size-cells = <0>;
88 a76_0: cpu@0 {
90 reg = <0>;
102 reg = <0x100>;
114 reg = <0x10000>;
126 reg = <0x10100>;
139 CPU_SLEEP_0: cpu-sleep-0 {
141 arm,psci-suspend-param = <0x0010000>;
149 L3_CA76_0: cache-controller-0 {
166 #clock-cells = <0>;
168 clock-frequency = <0>;
174 #clock-cells = <0>;
176 clock-frequency = <0>;
182 #clock-cells = <0>;
184 clock-frequency = <0>;
189 #clock-cells = <0>;
191 clock-frequency = <0>;
207 #clock-cells = <0>;
208 clock-frequency = <0>;
213 #clock-cells = <0>;
214 clock-frequency = <0>;
229 reg = <0 0xe6020000 0 0x0c>;
239 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
240 <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
241 <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
242 <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>,
243 <0 0xe6068000 0 0x16c>;
250 reg = <0 0xe6050180 0 0x54>;
257 gpio-ranges = <&pfc 0 0 19>;
265 reg = <0 0xe6050980 0 0x54>;
272 gpio-ranges = <&pfc 0 32 29>;
280 reg = <0 0xe6058180 0 0x54>;
287 gpio-ranges = <&pfc 0 64 20>;
295 reg = <0 0xe6058980 0 0x54>;
302 gpio-ranges = <&pfc 0 96 30>;
310 reg = <0 0xe6060180 0 0x54>;
317 gpio-ranges = <&pfc 0 128 25>;
325 reg = <0 0xe6060980 0 0x54>;
332 gpio-ranges = <&pfc 0 160 21>;
340 reg = <0 0xe6061180 0 0x54>;
347 gpio-ranges = <&pfc 0 192 21>;
355 reg = <0 0xe6061980 0 0x54>;
362 gpio-ranges = <&pfc 0 224 21>;
370 reg = <0 0xe6068180 0 0x54>;
377 gpio-ranges = <&pfc 0 256 14>;
385 reg = <0 0xe60f0000 0 0x1004>;
398 reg = <0 0xe6130000 0 0x1004>;
417 reg = <0 0xe6140000 0 0x1004>;
436 reg = <0 0xe6148000 0 0x1004>;
454 reg = <0 0xe6150000 0 0x4000>;
458 #power-domain-cells = <0>;
465 reg = <0 0xe6160000 0 0x4000>;
471 reg = <0 0xe6180000 0 0x4000>;
477 reg = <0 0xe6198000 0 0x200>,
478 <0 0xe61a0000 0 0x200>,
479 <0 0xe61a8000 0 0x200>,
480 <0 0xe61b0000 0 0x200>;
489 reg = <0 0xe61be000 0 0x1000>, <0 0xe61bf000 0 0x1000>;
496 reg = <0 0xe61c0000 0 0x200>;
497 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
510 reg = <0 0xe61e0000 0 0x30>;
524 reg = <0 0xe6fc0000 0 0x30>;
539 reg = <0 0xe6fd0000 0 0x30>;
554 reg = <0 0xe6fe0000 0 0x30>;
569 reg = <0 0xffc00000 0 0x30>;
584 reg = <0 0xe6460000 0 0x7000>,
585 <0 0xe6449000 0 0x500>;
599 reg = <0 0xe6500000 0 0x40>;
602 dmas = <&dmac0 0x91>, <&dmac0 0x90>,
603 <&dmac1 0x91>, <&dmac1 0x90>;
609 #size-cells = <0>;
616 reg = <0 0xe6508000 0 0x40>;
619 dmas = <&dmac0 0x93>, <&dmac0 0x92>,
620 <&dmac1 0x93>, <&dmac1 0x92>;
626 #size-cells = <0>;
633 reg = <0 0xe6510000 0 0x40>;
636 dmas = <&dmac0 0x95>, <&dmac0 0x94>,
637 <&dmac1 0x95>, <&dmac1 0x94>;
643 #size-cells = <0>;
650 reg = <0 0xe66d0000 0 0x40>;
653 dmas = <&dmac0 0x97>, <&dmac0 0x96>,
654 <&dmac1 0x97>, <&dmac1 0x96>;
660 #size-cells = <0>;
667 reg = <0 0xe66d8000 0 0x40>;
671 dmas = <&dmac0 0x99>, <&dmac0 0x98>,
672 <&dmac1 0x99>, <&dmac1 0x98>;
677 #size-cells = <0>;
684 reg = <0 0xe66e0000 0 0x40>;
687 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>,
688 <&dmac1 0x9b>, <&dmac1 0x9a>;
694 #size-cells = <0>;
701 reg = <0 0xe6540000 0 0x60>;
707 dmas = <&dmac0 0x31>, <&dmac0 0x30>,
708 <&dmac1 0x31>, <&dmac1 0x30>;
718 reg = <0 0xe6550000 0 0x60>;
724 dmas = <&dmac0 0x33>, <&dmac0 0x32>,
725 <&dmac1 0x33>, <&dmac1 0x32>;
735 reg = <0 0xe6560000 0 0x60>;
741 dmas = <&dmac0 0x35>, <&dmac0 0x34>,
742 <&dmac1 0x35>, <&dmac1 0x34>;
752 reg = <0 0xe66a0000 0 0x60>;
758 dmas = <&dmac0 0x37>, <&dmac0 0x36>,
759 <&dmac1 0x37>, <&dmac1 0x36>;
769 reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,
770 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
771 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
772 <0 0xfe000000 0 0x400000>;
788 bus-range = <0x00 0xff>;
790 ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>,
791 <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>;
792 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
794 interrupt-map-mask = <0 0 0 7>;
795 interrupt-map = <0 0 0 1 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
796 <0 0 0 2 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
797 <0 0 0 3 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
798 <0 0 0 4 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>;
806 reg = <0 0xe65d8000 0 0x1000>, <0 0xe65da000 0 0x0800>,
807 <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>,
808 <0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>,
809 <0 0xee900000 0 0x400000>;
825 bus-range = <0x00 0xff>;
827 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00400000>,
828 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x10000000>;
829 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
831 interrupt-map-mask = <0 0 0 7>;
832 interrupt-map = <0 0 0 1 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
833 <0 0 0 2 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
834 <0 0 0 3 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
835 <0 0 0 4 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
843 reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>,
844 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
845 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
846 <0 0xfe000000 0 0x400000>;
866 reg = <0 0xe65d8000 0 0x2000>, <0 0xe65da000 0 0x1000>,
867 <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>,
868 <0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>,
869 <0 0xee900000 0 0x400000>;
889 reg = <0 0xe6660000 0 0x8500>;
939 reg = <0 0xe6800000 0 0x1000>;
976 rx-internal-delay-ps = <0>;
977 tx-internal-delay-ps = <0>;
978 iommus = <&ipmmu_hc 0>;
985 reg = <0 0xe6810000 0 0x1000>;
1022 rx-internal-delay-ps = <0>;
1023 tx-internal-delay-ps = <0>;
1031 reg = <0 0xe6820000 0 0x1000>;
1068 rx-internal-delay-ps = <0>;
1069 tx-internal-delay-ps = <0>;
1076 reg = <0 0xe6e30000 0 0x10>;
1086 reg = <0 0xe6e31000 0 0x10>;
1096 reg = <0 0xe6e32000 0 0x10>;
1106 reg = <0 0xe6e33000 0 0x10>;
1116 reg = <0 0xe6e34000 0 0x10>;
1126 reg = <0 0xe6e35000 0 0x10>;
1136 reg = <0 0xe6e36000 0 0x10>;
1146 reg = <0 0xe6e37000 0 0x10>;
1156 reg = <0 0xe6e38000 0 0x10>;
1166 reg = <0 0xe6e39000 0 0x10>;
1177 reg = <0 0xe6e60000 0 64>;
1183 dmas = <&dmac0 0x51>, <&dmac0 0x50>,
1184 <&dmac1 0x51>, <&dmac1 0x50>;
1194 reg = <0 0xe6e68000 0 64>;
1200 dmas = <&dmac0 0x53>, <&dmac0 0x52>,
1201 <&dmac1 0x53>, <&dmac1 0x52>;
1211 reg = <0 0xe6c50000 0 64>;
1217 dmas = <&dmac0 0x57>, <&dmac0 0x56>,
1218 <&dmac1 0x57>, <&dmac1 0x56>;
1228 reg = <0 0xe6c40000 0 64>;
1234 dmas = <&dmac0 0x59>, <&dmac0 0x58>,
1235 <&dmac1 0x59>, <&dmac1 0x58>;
1244 reg = <0 0xe6e80000 0 0x148>;
1256 reg = <0 0xe6e90000 0 0x0064>;
1259 dmas = <&dmac0 0x41>, <&dmac0 0x40>,
1260 <&dmac1 0x41>, <&dmac1 0x40>;
1265 #size-cells = <0>;
1272 reg = <0 0xe6ea0000 0 0x0064>;
1275 dmas = <&dmac0 0x43>, <&dmac0 0x42>,
1276 <&dmac1 0x43>, <&dmac1 0x42>;
1281 #size-cells = <0>;
1288 reg = <0 0xe6c00000 0 0x0064>;
1291 dmas = <&dmac0 0x45>, <&dmac0 0x44>,
1292 <&dmac1 0x45>, <&dmac1 0x44>;
1297 #size-cells = <0>;
1304 reg = <0 0xe6c10000 0 0x0064>;
1307 dmas = <&dmac0 0x47>, <&dmac0 0x46>,
1308 <&dmac1 0x47>, <&dmac1 0x46>;
1313 #size-cells = <0>;
1320 reg = <0 0xe6c20000 0 0x0064>;
1323 dmas = <&dmac0 0x49>, <&dmac0 0x48>,
1324 <&dmac1 0x49>, <&dmac1 0x48>;
1329 #size-cells = <0>;
1336 reg = <0 0xe6c28000 0 0x0064>;
1339 dmas = <&dmac0 0x4b>, <&dmac0 0x4a>,
1340 <&dmac1 0x4b>, <&dmac1 0x4a>;
1345 #size-cells = <0>;
1352 reg = <0 0xe6ef0000 0 0x1000>;
1357 renesas,id = <0>;
1362 #size-cells = <0>;
1366 #size-cells = <0>;
1370 vin00isp0: endpoint@0 {
1371 reg = <0>;
1381 reg = <0 0xe6ef1000 0 0x1000>;
1391 #size-cells = <0>;
1395 #size-cells = <0>;
1399 vin01isp0: endpoint@0 {
1400 reg = <0>;
1410 reg = <0 0xe6ef2000 0 0x1000>;
1420 #size-cells = <0>;
1424 #size-cells = <0>;
1428 vin02isp0: endpoint@0 {
1429 reg = <0>;
1439 reg = <0 0xe6ef3000 0 0x1000>;
1449 #size-cells = <0>;
1453 #size-cells = <0>;
1457 vin03isp0: endpoint@0 {
1458 reg = <0>;
1468 reg = <0 0xe6ef4000 0 0x1000>;
1478 #size-cells = <0>;
1482 #size-cells = <0>;
1486 vin04isp0: endpoint@0 {
1487 reg = <0>;
1497 reg = <0 0xe6ef5000 0 0x1000>;
1507 #size-cells = <0>;
1511 #size-cells = <0>;
1515 vin05isp0: endpoint@0 {
1516 reg = <0>;
1526 reg = <0 0xe6ef6000 0 0x1000>;
1536 #size-cells = <0>;
1540 #size-cells = <0>;
1544 vin06isp0: endpoint@0 {
1545 reg = <0>;
1555 reg = <0 0xe6ef7000 0 0x1000>;
1565 #size-cells = <0>;
1569 #size-cells = <0>;
1573 vin07isp0: endpoint@0 {
1574 reg = <0>;
1584 reg = <0 0xe6ef8000 0 0x1000>;
1594 #size-cells = <0>;
1598 #size-cells = <0>;
1613 reg = <0 0xe6ef9000 0 0x1000>;
1623 #size-cells = <0>;
1627 #size-cells = <0>;
1642 reg = <0 0xe6efa000 0 0x1000>;
1652 #size-cells = <0>;
1656 #size-cells = <0>;
1671 reg = <0 0xe6efb000 0 0x1000>;
1681 #size-cells = <0>;
1685 #size-cells = <0>;
1700 reg = <0 0xe6efc000 0 0x1000>;
1710 #size-cells = <0>;
1714 #size-cells = <0>;
1729 reg = <0 0xe6efd000 0 0x1000>;
1739 #size-cells = <0>;
1743 #size-cells = <0>;
1758 reg = <0 0xe6efe000 0 0x1000>;
1768 #size-cells = <0>;
1772 #size-cells = <0>;
1787 reg = <0 0xe6eff000 0 0x1000>;
1797 #size-cells = <0>;
1801 #size-cells = <0>;
1816 reg = <0 0xe7350000 0 0x1000>,
1817 <0 0xe7300000 0 0x10000>;
1846 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
1859 reg = <0 0xe7351000 0 0x1000>,
1860 <0 0xe7310000 0 0x10000>;
1901 reg = <0 0xec5a0000 0 0x020>,
1902 <0 0xec540000 0 0x1000>,
1903 <0 0xec541000 0 0x050>,
1904 <0 0xec400000 0 0x40000>;
1908 clock-names = "ssiu.0", "ssi.0", "clkin";
1910 #clock-cells = <0>;
1912 #sound-dai-cells = <0>;
1916 reset-names = "ssiu.0", "ssi.0";
1920 ssiu00: ssiu-0 {
1921 dmas = <&dmac0 0x6e>, <&dmac0 0x6f>;
1925 dmas = <&dmac0 0x6c>, <&dmac0 0x6d>;
1929 dmas = <&dmac0 0x6a>, <&dmac0 0x6b>;
1933 dmas = <&dmac0 0x68>, <&dmac0 0x69>;
1937 dmas = <&dmac0 0x66>, <&dmac0 0x67>;
1941 dmas = <&dmac0 0x64>, <&dmac0 0x65>;
1945 dmas = <&dmac0 0x62>, <&dmac0 0x63>;
1949 dmas = <&dmac0 0x60>, <&dmac0 0x61>;
1955 ssi0: ssi-0 {
1964 reg = <0 0xee140000 0 0x2000>;
1979 reg = <0 0xee200000 0 0x200>,
1980 <0 0x08000000 0 0x04000000>,
1981 <0 0xee208000 0 0x100>;
1988 #size-cells = <0>;
1995 reg = <0 0xee480000 0 0x20000>;
2004 reg = <0 0xee4c0000 0 0x20000>;
2013 reg = <0 0xeed00000 0 0x20000>;
2022 reg = <0 0xeed40000 0 0x20000>;
2031 reg = <0 0xeed80000 0 0x20000>;
2040 reg = <0 0xeedc0000 0 0x20000>;
2049 reg = <0 0xeee00000 0 0x20000>;
2058 reg = <0 0xeee80000 0 0x20000>;
2067 reg = <0 0xeeec0000 0 0x20000>;
2076 reg = <0 0xeef00000 0 0x20000>;
2085 reg = <0 0xeef40000 0 0x20000>;
2094 reg = <0 0xeefc0000 0 0x20000>;
2104 #address-cells = <0>;
2106 reg = <0x0 0xf1000000 0 0x20000>,
2107 <0x0 0xf1060000 0 0x110000>;
2113 reg = <0 0xfe500000 0 0x40000>;
2122 #size-cells = <0>;
2124 port@0 {
2125 reg = <0>;
2139 reg = <0 0xfe540000 0 0x40000>;
2148 #size-cells = <0>;
2150 port@0 {
2151 reg = <0>;
2165 reg = <0 0xfea10000 0 0x200>;
2174 reg = <0 0xfea11000 0 0x200>;
2183 reg = <0 0xfedb0000 0 0x200>;
2192 reg = <0 0xfedb8000 0 0x200>;
2201 reg = <0 0xfea20000 0 0x7000>;
2212 reg = <0 0xfea28000 0 0x7000>;
2223 reg = <0 0xfedd0000 0 0x8000>;
2234 reg = <0 0xfedd8000 0 0x8000>;
2245 reg = <0 0xfeb00000 0 0x40000>;
2249 clock-names = "du.0";
2252 reset-names = "du.0";
2253 renesas,vsps = <&vspd0 0>, <&vspd1 0>;
2259 #size-cells = <0>;
2261 port@0 {
2262 reg = <0>;
2280 reg = <0 0xfed00000 0 0x10000>;
2289 #size-cells = <0>;
2291 port@0 {
2293 #size-cells = <0>;
2295 reg = <0>;
2297 isp0csi40: endpoint@0 {
2298 reg = <0>;
2364 reg = <0 0xfed20000 0 0x10000>;
2373 #size-cells = <0>;
2375 port@0 {
2377 #size-cells = <0>;
2379 reg = <0>;
2447 reg = <0 0xfed80000 0 0x10000>;
2459 #size-cells = <0>;
2461 port@0 {
2462 reg = <0>;
2476 reg = <0 0xfed90000 0 0x10000>;
2488 #size-cells = <0>;
2490 port@0 {
2491 reg = <0>;
2505 reg = <0 0xfff00044 0 4>;
2514 thermal-sensors = <&tsc 0>;