Lines Matching +full:0 +full:xe66d8000
20 #clock-cells = <0>;
21 clock-frequency = <0>;
27 #clock-cells = <0>;
28 clock-frequency = <0>;
31 cluster0_opp: opp-table-0 {
66 #size-cells = <0>;
88 a76_0: cpu@0 {
90 reg = <0>;
102 reg = <0x100>;
114 reg = <0x10000>;
126 reg = <0x10100>;
139 CPU_SLEEP_0: cpu-sleep-0 {
141 arm,psci-suspend-param = <0x0010000>;
149 L3_CA76_0: cache-controller-0 {
166 #clock-cells = <0>;
168 clock-frequency = <0>;
173 #clock-cells = <0>;
175 clock-frequency = <0>;
180 #clock-cells = <0>;
182 clock-frequency = <0>;
187 #clock-cells = <0>;
189 clock-frequency = <0>;
205 #clock-cells = <0>;
206 clock-frequency = <0>;
211 #clock-cells = <0>;
212 clock-frequency = <0>;
225 reg = <0 0xe6020000 0 0x0c>;
235 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
236 <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
237 <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
238 <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>,
239 <0 0xe6068000 0 0x16c>;
245 reg = <0 0xe6050180 0 0x54>;
252 gpio-ranges = <&pfc 0 0 19>;
260 reg = <0 0xe6050980 0 0x54>;
267 gpio-ranges = <&pfc 0 32 29>;
275 reg = <0 0xe6058180 0 0x54>;
282 gpio-ranges = <&pfc 0 64 20>;
290 reg = <0 0xe6058980 0 0x54>;
297 gpio-ranges = <&pfc 0 96 30>;
305 reg = <0 0xe6060180 0 0x54>;
312 gpio-ranges = <&pfc 0 128 25>;
320 reg = <0 0xe6060980 0 0x54>;
327 gpio-ranges = <&pfc 0 160 21>;
335 reg = <0 0xe6061180 0 0x54>;
342 gpio-ranges = <&pfc 0 192 21>;
350 reg = <0 0xe6061980 0 0x54>;
357 gpio-ranges = <&pfc 0 224 21>;
365 reg = <0 0xe6068180 0 0x54>;
372 gpio-ranges = <&pfc 0 256 14>;
380 reg = <0 0xe60f0000 0 0x1004>;
393 reg = <0 0xe6130000 0 0x1004>;
412 reg = <0 0xe6140000 0 0x1004>;
431 reg = <0 0xe6148000 0 0x1004>;
449 reg = <0 0xe6150000 0 0x4000>;
453 #power-domain-cells = <0>;
459 reg = <0 0xe6160000 0 0x4000>;
464 reg = <0 0xe6180000 0 0x4000>;
470 reg = <0 0xe6198000 0 0x200>,
471 <0 0xe61a0000 0 0x200>,
472 <0 0xe61a8000 0 0x200>,
473 <0 0xe61b0000 0 0x200>;
484 reg = <0 0xe61c0000 0 0x200>;
485 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
498 reg = <0 0xe61e0000 0 0x30>;
512 reg = <0 0xe6fc0000 0 0x30>;
527 reg = <0 0xe6fd0000 0 0x30>;
542 reg = <0 0xe6fe0000 0 0x30>;
557 reg = <0 0xffc00000 0 0x30>;
572 reg = <0 0xe6460000 0 0x7000>,
573 <0 0xe6449000 0 0x500>;
587 reg = <0 0xe6500000 0 0x40>;
590 dmas = <&dmac0 0x91>, <&dmac0 0x90>,
591 <&dmac1 0x91>, <&dmac1 0x90>;
597 #size-cells = <0>;
604 reg = <0 0xe6508000 0 0x40>;
607 dmas = <&dmac0 0x93>, <&dmac0 0x92>,
608 <&dmac1 0x93>, <&dmac1 0x92>;
614 #size-cells = <0>;
621 reg = <0 0xe6510000 0 0x40>;
624 dmas = <&dmac0 0x95>, <&dmac0 0x94>,
625 <&dmac1 0x95>, <&dmac1 0x94>;
631 #size-cells = <0>;
638 reg = <0 0xe66d0000 0 0x40>;
641 dmas = <&dmac0 0x97>, <&dmac0 0x96>,
642 <&dmac1 0x97>, <&dmac1 0x96>;
648 #size-cells = <0>;
655 reg = <0 0xe66d8000 0 0x40>;
659 dmas = <&dmac0 0x99>, <&dmac0 0x98>,
660 <&dmac1 0x99>, <&dmac1 0x98>;
665 #size-cells = <0>;
672 reg = <0 0xe66e0000 0 0x40>;
675 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>,
676 <&dmac1 0x9b>, <&dmac1 0x9a>;
682 #size-cells = <0>;
689 reg = <0 0xe6540000 0 0x60>;
695 dmas = <&dmac0 0x31>, <&dmac0 0x30>,
696 <&dmac1 0x31>, <&dmac1 0x30>;
706 reg = <0 0xe6550000 0 0x60>;
712 dmas = <&dmac0 0x33>, <&dmac0 0x32>,
713 <&dmac1 0x33>, <&dmac1 0x32>;
723 reg = <0 0xe6560000 0 0x60>;
729 dmas = <&dmac0 0x35>, <&dmac0 0x34>,
730 <&dmac1 0x35>, <&dmac1 0x34>;
740 reg = <0 0xe66a0000 0 0x60>;
746 dmas = <&dmac0 0x37>, <&dmac0 0x36>,
747 <&dmac1 0x37>, <&dmac1 0x36>;
757 reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,
758 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
759 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
760 <0 0xfe000000 0 0x400000>;
776 bus-range = <0x00 0xff>;
778 ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>,
779 <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>;
780 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
782 interrupt-map-mask = <0 0 0 7>;
783 interrupt-map = <0 0 0 1 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
784 <0 0 0 2 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
785 <0 0 0 3 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
786 <0 0 0 4 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>;
794 reg = <0 0xe65d8000 0 0x1000>, <0 0xe65da000 0 0x0800>,
795 <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>,
796 <0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>,
797 <0 0xee900000 0 0x400000>;
813 bus-range = <0x00 0xff>;
815 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00400000>,
816 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x10000000>;
817 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
819 interrupt-map-mask = <0 0 0 7>;
820 interrupt-map = <0 0 0 1 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
821 <0 0 0 2 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
822 <0 0 0 3 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
823 <0 0 0 4 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
831 reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>,
832 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
833 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
834 <0 0xfe000000 0 0x400000>;
854 reg = <0 0xe65d8000 0 0x2000>, <0 0xe65da000 0 0x1000>,
855 <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>,
856 <0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>,
857 <0 0xee900000 0 0x400000>;
877 reg = <0 0xe6660000 0 0x8500>;
927 reg = <0 0xe6800000 0 0x1000>;
964 rx-internal-delay-ps = <0>;
965 tx-internal-delay-ps = <0>;
966 iommus = <&ipmmu_hc 0>;
973 reg = <0 0xe6810000 0 0x1000>;
1010 rx-internal-delay-ps = <0>;
1011 tx-internal-delay-ps = <0>;
1019 reg = <0 0xe6820000 0 0x1000>;
1056 rx-internal-delay-ps = <0>;
1057 tx-internal-delay-ps = <0>;
1064 reg = <0 0xe6e30000 0 0x10>;
1074 reg = <0 0xe6e31000 0 0x10>;
1084 reg = <0 0xe6e32000 0 0x10>;
1094 reg = <0 0xe6e33000 0 0x10>;
1104 reg = <0 0xe6e34000 0 0x10>;
1114 reg = <0 0xe6e35000 0 0x10>;
1124 reg = <0 0xe6e36000 0 0x10>;
1134 reg = <0 0xe6e37000 0 0x10>;
1144 reg = <0 0xe6e38000 0 0x10>;
1154 reg = <0 0xe6e39000 0 0x10>;
1165 reg = <0 0xe6e60000 0 64>;
1171 dmas = <&dmac0 0x51>, <&dmac0 0x50>,
1172 <&dmac1 0x51>, <&dmac1 0x50>;
1182 reg = <0 0xe6e68000 0 64>;
1188 dmas = <&dmac0 0x53>, <&dmac0 0x52>,
1189 <&dmac1 0x53>, <&dmac1 0x52>;
1199 reg = <0 0xe6c50000 0 64>;
1205 dmas = <&dmac0 0x57>, <&dmac0 0x56>,
1206 <&dmac1 0x57>, <&dmac1 0x56>;
1216 reg = <0 0xe6c40000 0 64>;
1222 dmas = <&dmac0 0x59>, <&dmac0 0x58>,
1223 <&dmac1 0x59>, <&dmac1 0x58>;
1232 reg = <0 0xe6e80000 0 0x148>;
1244 reg = <0 0xe6e90000 0 0x0064>;
1247 dmas = <&dmac0 0x41>, <&dmac0 0x40>,
1248 <&dmac1 0x41>, <&dmac1 0x40>;
1253 #size-cells = <0>;
1260 reg = <0 0xe6ea0000 0 0x0064>;
1263 dmas = <&dmac0 0x43>, <&dmac0 0x42>,
1264 <&dmac1 0x43>, <&dmac1 0x42>;
1269 #size-cells = <0>;
1276 reg = <0 0xe6c00000 0 0x0064>;
1279 dmas = <&dmac0 0x45>, <&dmac0 0x44>,
1280 <&dmac1 0x45>, <&dmac1 0x44>;
1285 #size-cells = <0>;
1292 reg = <0 0xe6c10000 0 0x0064>;
1295 dmas = <&dmac0 0x47>, <&dmac0 0x46>,
1296 <&dmac1 0x47>, <&dmac1 0x46>;
1301 #size-cells = <0>;
1308 reg = <0 0xe6c20000 0 0x0064>;
1311 dmas = <&dmac0 0x49>, <&dmac0 0x48>,
1312 <&dmac1 0x49>, <&dmac1 0x48>;
1317 #size-cells = <0>;
1324 reg = <0 0xe6c28000 0 0x0064>;
1327 dmas = <&dmac0 0x4b>, <&dmac0 0x4a>,
1328 <&dmac1 0x4b>, <&dmac1 0x4a>;
1333 #size-cells = <0>;
1340 reg = <0 0xe6ef0000 0 0x1000>;
1345 renesas,id = <0>;
1350 #size-cells = <0>;
1354 #size-cells = <0>;
1358 vin00isp0: endpoint@0 {
1359 reg = <0>;
1369 reg = <0 0xe6ef1000 0 0x1000>;
1379 #size-cells = <0>;
1383 #size-cells = <0>;
1387 vin01isp0: endpoint@0 {
1388 reg = <0>;
1398 reg = <0 0xe6ef2000 0 0x1000>;
1408 #size-cells = <0>;
1412 #size-cells = <0>;
1416 vin02isp0: endpoint@0 {
1417 reg = <0>;
1427 reg = <0 0xe6ef3000 0 0x1000>;
1437 #size-cells = <0>;
1441 #size-cells = <0>;
1445 vin03isp0: endpoint@0 {
1446 reg = <0>;
1456 reg = <0 0xe6ef4000 0 0x1000>;
1466 #size-cells = <0>;
1470 #size-cells = <0>;
1474 vin04isp0: endpoint@0 {
1475 reg = <0>;
1485 reg = <0 0xe6ef5000 0 0x1000>;
1495 #size-cells = <0>;
1499 #size-cells = <0>;
1503 vin05isp0: endpoint@0 {
1504 reg = <0>;
1514 reg = <0 0xe6ef6000 0 0x1000>;
1524 #size-cells = <0>;
1528 #size-cells = <0>;
1532 vin06isp0: endpoint@0 {
1533 reg = <0>;
1543 reg = <0 0xe6ef7000 0 0x1000>;
1553 #size-cells = <0>;
1557 #size-cells = <0>;
1561 vin07isp0: endpoint@0 {
1562 reg = <0>;
1572 reg = <0 0xe6ef8000 0 0x1000>;
1582 #size-cells = <0>;
1586 #size-cells = <0>;
1601 reg = <0 0xe6ef9000 0 0x1000>;
1611 #size-cells = <0>;
1615 #size-cells = <0>;
1630 reg = <0 0xe6efa000 0 0x1000>;
1640 #size-cells = <0>;
1644 #size-cells = <0>;
1659 reg = <0 0xe6efb000 0 0x1000>;
1669 #size-cells = <0>;
1673 #size-cells = <0>;
1688 reg = <0 0xe6efc000 0 0x1000>;
1698 #size-cells = <0>;
1702 #size-cells = <0>;
1717 reg = <0 0xe6efd000 0 0x1000>;
1727 #size-cells = <0>;
1731 #size-cells = <0>;
1746 reg = <0 0xe6efe000 0 0x1000>;
1756 #size-cells = <0>;
1760 #size-cells = <0>;
1775 reg = <0 0xe6eff000 0 0x1000>;
1785 #size-cells = <0>;
1789 #size-cells = <0>;
1804 reg = <0 0xe7350000 0 0x1000>,
1805 <0 0xe7300000 0 0x10000>;
1834 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
1847 reg = <0 0xe7351000 0 0x1000>,
1848 <0 0xe7310000 0 0x10000>;
1889 reg = <0 0xec5a0000 0 0x020>,
1890 <0 0xec540000 0 0x1000>,
1891 <0 0xec541000 0 0x050>,
1892 <0 0xec400000 0 0x40000>;
1896 clock-names = "ssiu.0", "ssi.0", "clkin";
1898 #clock-cells = <0>;
1900 #sound-dai-cells = <0>;
1904 reset-names = "ssiu.0", "ssi.0";
1908 ssiu00: ssiu-0 {
1909 dmas = <&dmac0 0x6e>, <&dmac0 0x6f>;
1913 dmas = <&dmac0 0x6c>, <&dmac0 0x6d>;
1917 dmas = <&dmac0 0x6a>, <&dmac0 0x6b>;
1921 dmas = <&dmac0 0x68>, <&dmac0 0x69>;
1925 dmas = <&dmac0 0x66>, <&dmac0 0x67>;
1929 dmas = <&dmac0 0x64>, <&dmac0 0x65>;
1933 dmas = <&dmac0 0x62>, <&dmac0 0x63>;
1937 dmas = <&dmac0 0x60>, <&dmac0 0x61>;
1943 ssi0: ssi-0 {
1952 reg = <0 0xee140000 0 0x2000>;
1967 reg = <0 0xee200000 0 0x200>,
1968 <0 0x08000000 0 0x04000000>,
1969 <0 0xee208000 0 0x100>;
1976 #size-cells = <0>;
1983 reg = <0 0xee480000 0 0x20000>;
1992 reg = <0 0xee4c0000 0 0x20000>;
2001 reg = <0 0xeed00000 0 0x20000>;
2010 reg = <0 0xeed40000 0 0x20000>;
2019 reg = <0 0xeed80000 0 0x20000>;
2028 reg = <0 0xeedc0000 0 0x20000>;
2037 reg = <0 0xeee00000 0 0x20000>;
2046 reg = <0 0xeee80000 0 0x20000>;
2055 reg = <0 0xeeec0000 0 0x20000>;
2064 reg = <0 0xeef00000 0 0x20000>;
2073 reg = <0 0xeef40000 0 0x20000>;
2082 reg = <0 0xeefc0000 0 0x20000>;
2092 #address-cells = <0>;
2094 reg = <0x0 0xf1000000 0 0x20000>,
2095 <0x0 0xf1060000 0 0x110000>;
2101 reg = <0 0xfe500000 0 0x40000>;
2110 #size-cells = <0>;
2112 port@0 {
2113 reg = <0>;
2127 reg = <0 0xfe540000 0 0x40000>;
2136 #size-cells = <0>;
2138 port@0 {
2139 reg = <0>;
2153 reg = <0 0xfea10000 0 0x200>;
2162 reg = <0 0xfea11000 0 0x200>;
2171 reg = <0 0xfea20000 0 0x7000>;
2182 reg = <0 0xfea28000 0 0x7000>;
2193 reg = <0 0xfeb00000 0 0x40000>;
2197 clock-names = "du.0";
2200 reset-names = "du.0";
2201 renesas,vsps = <&vspd0 0>, <&vspd1 0>;
2207 #size-cells = <0>;
2209 port@0 {
2210 reg = <0>;
2228 reg = <0 0xfed00000 0 0x10000>;
2237 #size-cells = <0>;
2239 port@0 {
2241 #size-cells = <0>;
2243 reg = <0>;
2245 isp0csi40: endpoint@0 {
2246 reg = <0>;
2312 reg = <0 0xfed20000 0 0x10000>;
2321 #size-cells = <0>;
2323 port@0 {
2325 #size-cells = <0>;
2327 reg = <0>;
2395 reg = <0 0xfed80000 0 0x10000>;
2407 #size-cells = <0>;
2409 port@0 {
2410 reg = <0>;
2424 reg = <0 0xfed90000 0 0x10000>;
2436 #size-cells = <0>;
2438 port@0 {
2439 reg = <0>;
2453 reg = <0 0xfff00044 0 4>;
2461 thermal-sensors = <&tsc 0>;