Lines Matching +full:0 +full:xe6449000
20 #clock-cells = <0>;
21 clock-frequency = <0>;
27 #clock-cells = <0>;
28 clock-frequency = <0>;
31 cluster0_opp: opp-table-0 {
66 #size-cells = <0>;
88 a76_0: cpu@0 {
90 reg = <0>;
102 reg = <0x100>;
114 reg = <0x10000>;
126 reg = <0x10100>;
139 CPU_SLEEP_0: cpu-sleep-0 {
141 arm,psci-suspend-param = <0x0010000>;
149 L3_CA76_0: cache-controller-0 {
166 #clock-cells = <0>;
168 clock-frequency = <0>;
173 #clock-cells = <0>;
175 clock-frequency = <0>;
180 #clock-cells = <0>;
182 clock-frequency = <0>;
187 #clock-cells = <0>;
189 clock-frequency = <0>;
205 #clock-cells = <0>;
206 clock-frequency = <0>;
211 #clock-cells = <0>;
212 clock-frequency = <0>;
225 reg = <0 0xe6020000 0 0x0c>;
235 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
236 <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
237 <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
238 <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>,
239 <0 0xe6068000 0 0x16c>;
245 reg = <0 0xe6050180 0 0x54>;
252 gpio-ranges = <&pfc 0 0 19>;
260 reg = <0 0xe6050980 0 0x54>;
267 gpio-ranges = <&pfc 0 32 29>;
275 reg = <0 0xe6058180 0 0x54>;
282 gpio-ranges = <&pfc 0 64 20>;
290 reg = <0 0xe6058980 0 0x54>;
297 gpio-ranges = <&pfc 0 96 30>;
305 reg = <0 0xe6060180 0 0x54>;
312 gpio-ranges = <&pfc 0 128 25>;
320 reg = <0 0xe6060980 0 0x54>;
327 gpio-ranges = <&pfc 0 160 21>;
335 reg = <0 0xe6061180 0 0x54>;
342 gpio-ranges = <&pfc 0 192 21>;
350 reg = <0 0xe6061980 0 0x54>;
357 gpio-ranges = <&pfc 0 224 21>;
365 reg = <0 0xe6068180 0 0x54>;
372 gpio-ranges = <&pfc 0 256 14>;
380 reg = <0 0xe60f0000 0 0x1004>;
393 reg = <0 0xe6130000 0 0x1004>;
412 reg = <0 0xe6140000 0 0x1004>;
431 reg = <0 0xe6148000 0 0x1004>;
449 reg = <0 0xe6150000 0 0x4000>;
453 #power-domain-cells = <0>;
459 reg = <0 0xe6160000 0 0x4000>;
464 reg = <0 0xe6180000 0 0x4000>;
470 reg = <0 0xe6198000 0 0x200>,
471 <0 0xe61a0000 0 0x200>,
472 <0 0xe61a8000 0 0x200>,
473 <0 0xe61b0000 0 0x200>;
482 reg = <0 0xe61be000 0 0x1000>, <0 0xe61bf000 0 0x1000>;
489 reg = <0 0xe61c0000 0 0x200>;
490 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
503 reg = <0 0xe61e0000 0 0x30>;
517 reg = <0 0xe6fc0000 0 0x30>;
532 reg = <0 0xe6fd0000 0 0x30>;
547 reg = <0 0xe6fe0000 0 0x30>;
562 reg = <0 0xffc00000 0 0x30>;
577 reg = <0 0xe6460000 0 0x7000>,
578 <0 0xe6449000 0 0x500>;
592 reg = <0 0xe6500000 0 0x40>;
595 dmas = <&dmac0 0x91>, <&dmac0 0x90>,
596 <&dmac1 0x91>, <&dmac1 0x90>;
602 #size-cells = <0>;
609 reg = <0 0xe6508000 0 0x40>;
612 dmas = <&dmac0 0x93>, <&dmac0 0x92>,
613 <&dmac1 0x93>, <&dmac1 0x92>;
619 #size-cells = <0>;
626 reg = <0 0xe6510000 0 0x40>;
629 dmas = <&dmac0 0x95>, <&dmac0 0x94>,
630 <&dmac1 0x95>, <&dmac1 0x94>;
636 #size-cells = <0>;
643 reg = <0 0xe66d0000 0 0x40>;
646 dmas = <&dmac0 0x97>, <&dmac0 0x96>,
647 <&dmac1 0x97>, <&dmac1 0x96>;
653 #size-cells = <0>;
660 reg = <0 0xe66d8000 0 0x40>;
664 dmas = <&dmac0 0x99>, <&dmac0 0x98>,
665 <&dmac1 0x99>, <&dmac1 0x98>;
670 #size-cells = <0>;
677 reg = <0 0xe66e0000 0 0x40>;
680 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>,
681 <&dmac1 0x9b>, <&dmac1 0x9a>;
687 #size-cells = <0>;
694 reg = <0 0xe6540000 0 0x60>;
700 dmas = <&dmac0 0x31>, <&dmac0 0x30>,
701 <&dmac1 0x31>, <&dmac1 0x30>;
711 reg = <0 0xe6550000 0 0x60>;
717 dmas = <&dmac0 0x33>, <&dmac0 0x32>,
718 <&dmac1 0x33>, <&dmac1 0x32>;
728 reg = <0 0xe6560000 0 0x60>;
734 dmas = <&dmac0 0x35>, <&dmac0 0x34>,
735 <&dmac1 0x35>, <&dmac1 0x34>;
745 reg = <0 0xe66a0000 0 0x60>;
751 dmas = <&dmac0 0x37>, <&dmac0 0x36>,
752 <&dmac1 0x37>, <&dmac1 0x36>;
762 reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,
763 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
764 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
765 <0 0xfe000000 0 0x400000>;
781 bus-range = <0x00 0xff>;
783 ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>,
784 <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>;
785 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
787 interrupt-map-mask = <0 0 0 7>;
788 interrupt-map = <0 0 0 1 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
789 <0 0 0 2 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
790 <0 0 0 3 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
791 <0 0 0 4 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>;
799 reg = <0 0xe65d8000 0 0x1000>, <0 0xe65da000 0 0x0800>,
800 <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>,
801 <0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>,
802 <0 0xee900000 0 0x400000>;
818 bus-range = <0x00 0xff>;
820 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00400000>,
821 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x10000000>;
822 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
824 interrupt-map-mask = <0 0 0 7>;
825 interrupt-map = <0 0 0 1 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
826 <0 0 0 2 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
827 <0 0 0 3 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
828 <0 0 0 4 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
836 reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>,
837 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
838 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
839 <0 0xfe000000 0 0x400000>;
859 reg = <0 0xe65d8000 0 0x2000>, <0 0xe65da000 0 0x1000>,
860 <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>,
861 <0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>,
862 <0 0xee900000 0 0x400000>;
882 reg = <0 0xe6660000 0 0x8500>;
932 reg = <0 0xe6800000 0 0x1000>;
969 rx-internal-delay-ps = <0>;
970 tx-internal-delay-ps = <0>;
971 iommus = <&ipmmu_hc 0>;
978 reg = <0 0xe6810000 0 0x1000>;
1015 rx-internal-delay-ps = <0>;
1016 tx-internal-delay-ps = <0>;
1024 reg = <0 0xe6820000 0 0x1000>;
1061 rx-internal-delay-ps = <0>;
1062 tx-internal-delay-ps = <0>;
1069 reg = <0 0xe6e30000 0 0x10>;
1079 reg = <0 0xe6e31000 0 0x10>;
1089 reg = <0 0xe6e32000 0 0x10>;
1099 reg = <0 0xe6e33000 0 0x10>;
1109 reg = <0 0xe6e34000 0 0x10>;
1119 reg = <0 0xe6e35000 0 0x10>;
1129 reg = <0 0xe6e36000 0 0x10>;
1139 reg = <0 0xe6e37000 0 0x10>;
1149 reg = <0 0xe6e38000 0 0x10>;
1159 reg = <0 0xe6e39000 0 0x10>;
1170 reg = <0 0xe6e60000 0 64>;
1176 dmas = <&dmac0 0x51>, <&dmac0 0x50>,
1177 <&dmac1 0x51>, <&dmac1 0x50>;
1187 reg = <0 0xe6e68000 0 64>;
1193 dmas = <&dmac0 0x53>, <&dmac0 0x52>,
1194 <&dmac1 0x53>, <&dmac1 0x52>;
1204 reg = <0 0xe6c50000 0 64>;
1210 dmas = <&dmac0 0x57>, <&dmac0 0x56>,
1211 <&dmac1 0x57>, <&dmac1 0x56>;
1221 reg = <0 0xe6c40000 0 64>;
1227 dmas = <&dmac0 0x59>, <&dmac0 0x58>,
1228 <&dmac1 0x59>, <&dmac1 0x58>;
1237 reg = <0 0xe6e80000 0 0x148>;
1249 reg = <0 0xe6e90000 0 0x0064>;
1252 dmas = <&dmac0 0x41>, <&dmac0 0x40>,
1253 <&dmac1 0x41>, <&dmac1 0x40>;
1258 #size-cells = <0>;
1265 reg = <0 0xe6ea0000 0 0x0064>;
1268 dmas = <&dmac0 0x43>, <&dmac0 0x42>,
1269 <&dmac1 0x43>, <&dmac1 0x42>;
1274 #size-cells = <0>;
1281 reg = <0 0xe6c00000 0 0x0064>;
1284 dmas = <&dmac0 0x45>, <&dmac0 0x44>,
1285 <&dmac1 0x45>, <&dmac1 0x44>;
1290 #size-cells = <0>;
1297 reg = <0 0xe6c10000 0 0x0064>;
1300 dmas = <&dmac0 0x47>, <&dmac0 0x46>,
1301 <&dmac1 0x47>, <&dmac1 0x46>;
1306 #size-cells = <0>;
1313 reg = <0 0xe6c20000 0 0x0064>;
1316 dmas = <&dmac0 0x49>, <&dmac0 0x48>,
1317 <&dmac1 0x49>, <&dmac1 0x48>;
1322 #size-cells = <0>;
1329 reg = <0 0xe6c28000 0 0x0064>;
1332 dmas = <&dmac0 0x4b>, <&dmac0 0x4a>,
1333 <&dmac1 0x4b>, <&dmac1 0x4a>;
1338 #size-cells = <0>;
1345 reg = <0 0xe6ef0000 0 0x1000>;
1350 renesas,id = <0>;
1355 #size-cells = <0>;
1359 #size-cells = <0>;
1363 vin00isp0: endpoint@0 {
1364 reg = <0>;
1374 reg = <0 0xe6ef1000 0 0x1000>;
1384 #size-cells = <0>;
1388 #size-cells = <0>;
1392 vin01isp0: endpoint@0 {
1393 reg = <0>;
1403 reg = <0 0xe6ef2000 0 0x1000>;
1413 #size-cells = <0>;
1417 #size-cells = <0>;
1421 vin02isp0: endpoint@0 {
1422 reg = <0>;
1432 reg = <0 0xe6ef3000 0 0x1000>;
1442 #size-cells = <0>;
1446 #size-cells = <0>;
1450 vin03isp0: endpoint@0 {
1451 reg = <0>;
1461 reg = <0 0xe6ef4000 0 0x1000>;
1471 #size-cells = <0>;
1475 #size-cells = <0>;
1479 vin04isp0: endpoint@0 {
1480 reg = <0>;
1490 reg = <0 0xe6ef5000 0 0x1000>;
1500 #size-cells = <0>;
1504 #size-cells = <0>;
1508 vin05isp0: endpoint@0 {
1509 reg = <0>;
1519 reg = <0 0xe6ef6000 0 0x1000>;
1529 #size-cells = <0>;
1533 #size-cells = <0>;
1537 vin06isp0: endpoint@0 {
1538 reg = <0>;
1548 reg = <0 0xe6ef7000 0 0x1000>;
1558 #size-cells = <0>;
1562 #size-cells = <0>;
1566 vin07isp0: endpoint@0 {
1567 reg = <0>;
1577 reg = <0 0xe6ef8000 0 0x1000>;
1587 #size-cells = <0>;
1591 #size-cells = <0>;
1606 reg = <0 0xe6ef9000 0 0x1000>;
1616 #size-cells = <0>;
1620 #size-cells = <0>;
1635 reg = <0 0xe6efa000 0 0x1000>;
1645 #size-cells = <0>;
1649 #size-cells = <0>;
1664 reg = <0 0xe6efb000 0 0x1000>;
1674 #size-cells = <0>;
1678 #size-cells = <0>;
1693 reg = <0 0xe6efc000 0 0x1000>;
1703 #size-cells = <0>;
1707 #size-cells = <0>;
1722 reg = <0 0xe6efd000 0 0x1000>;
1732 #size-cells = <0>;
1736 #size-cells = <0>;
1751 reg = <0 0xe6efe000 0 0x1000>;
1761 #size-cells = <0>;
1765 #size-cells = <0>;
1780 reg = <0 0xe6eff000 0 0x1000>;
1790 #size-cells = <0>;
1794 #size-cells = <0>;
1809 reg = <0 0xe7350000 0 0x1000>,
1810 <0 0xe7300000 0 0x10000>;
1839 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
1852 reg = <0 0xe7351000 0 0x1000>,
1853 <0 0xe7310000 0 0x10000>;
1894 reg = <0 0xec5a0000 0 0x020>,
1895 <0 0xec540000 0 0x1000>,
1896 <0 0xec541000 0 0x050>,
1897 <0 0xec400000 0 0x40000>;
1901 clock-names = "ssiu.0", "ssi.0", "clkin";
1903 #clock-cells = <0>;
1905 #sound-dai-cells = <0>;
1909 reset-names = "ssiu.0", "ssi.0";
1913 ssiu00: ssiu-0 {
1914 dmas = <&dmac0 0x6e>, <&dmac0 0x6f>;
1918 dmas = <&dmac0 0x6c>, <&dmac0 0x6d>;
1922 dmas = <&dmac0 0x6a>, <&dmac0 0x6b>;
1926 dmas = <&dmac0 0x68>, <&dmac0 0x69>;
1930 dmas = <&dmac0 0x66>, <&dmac0 0x67>;
1934 dmas = <&dmac0 0x64>, <&dmac0 0x65>;
1938 dmas = <&dmac0 0x62>, <&dmac0 0x63>;
1942 dmas = <&dmac0 0x60>, <&dmac0 0x61>;
1948 ssi0: ssi-0 {
1957 reg = <0 0xee140000 0 0x2000>;
1972 reg = <0 0xee200000 0 0x200>,
1973 <0 0x08000000 0 0x04000000>,
1974 <0 0xee208000 0 0x100>;
1981 #size-cells = <0>;
1988 reg = <0 0xee480000 0 0x20000>;
1997 reg = <0 0xee4c0000 0 0x20000>;
2006 reg = <0 0xeed00000 0 0x20000>;
2015 reg = <0 0xeed40000 0 0x20000>;
2024 reg = <0 0xeed80000 0 0x20000>;
2033 reg = <0 0xeedc0000 0 0x20000>;
2042 reg = <0 0xeee00000 0 0x20000>;
2051 reg = <0 0xeee80000 0 0x20000>;
2060 reg = <0 0xeeec0000 0 0x20000>;
2069 reg = <0 0xeef00000 0 0x20000>;
2078 reg = <0 0xeef40000 0 0x20000>;
2087 reg = <0 0xeefc0000 0 0x20000>;
2097 #address-cells = <0>;
2099 reg = <0x0 0xf1000000 0 0x20000>,
2100 <0x0 0xf1060000 0 0x110000>;
2106 reg = <0 0xfe500000 0 0x40000>;
2115 #size-cells = <0>;
2117 port@0 {
2118 reg = <0>;
2132 reg = <0 0xfe540000 0 0x40000>;
2141 #size-cells = <0>;
2143 port@0 {
2144 reg = <0>;
2158 reg = <0 0xfea10000 0 0x200>;
2167 reg = <0 0xfea11000 0 0x200>;
2176 reg = <0 0xfea20000 0 0x7000>;
2187 reg = <0 0xfea28000 0 0x7000>;
2198 reg = <0 0xfeb00000 0 0x40000>;
2202 clock-names = "du.0";
2205 reset-names = "du.0";
2206 renesas,vsps = <&vspd0 0>, <&vspd1 0>;
2212 #size-cells = <0>;
2214 port@0 {
2215 reg = <0>;
2233 reg = <0 0xfed00000 0 0x10000>;
2242 #size-cells = <0>;
2244 port@0 {
2246 #size-cells = <0>;
2248 reg = <0>;
2250 isp0csi40: endpoint@0 {
2251 reg = <0>;
2317 reg = <0 0xfed20000 0 0x10000>;
2326 #size-cells = <0>;
2328 port@0 {
2330 #size-cells = <0>;
2332 reg = <0>;
2400 reg = <0 0xfed80000 0 0x10000>;
2412 #size-cells = <0>;
2414 port@0 {
2415 reg = <0>;
2429 reg = <0 0xfed90000 0 0x10000>;
2441 #size-cells = <0>;
2443 port@0 {
2444 reg = <0>;
2458 reg = <0 0xfff00044 0 4>;
2466 thermal-sensors = <&tsc 0>;