Lines Matching +full:cpu +full:- +full:ufs
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC
8 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a779f0-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
17 cluster01_opp: opp-table-0 {
18 compatible = "operating-points-v2";
19 opp-shared;
21 opp-500000000 {
22 opp-hz = /bits/ 64 <500000000>;
23 opp-microvolt = <880000>;
24 clock-latency-ns = <500000>;
26 opp-800000000 {
27 opp-hz = /bits/ 64 <800000000>;
28 opp-microvolt = <880000>;
29 clock-latency-ns = <500000>;
31 opp-1000000000 {
32 opp-hz = /bits/ 64 <1000000000>;
33 opp-microvolt = <880000>;
34 clock-latency-ns = <500000>;
36 opp-1200000000 {
37 opp-hz = /bits/ 64 <1200000000>;
38 opp-microvolt = <880000>;
39 clock-latency-ns = <500000>;
40 opp-suspend;
44 cluster23_opp: opp-table-1 {
45 compatible = "operating-points-v2";
46 opp-shared;
48 opp-500000000 {
49 opp-hz = /bits/ 64 <500000000>;
50 opp-microvolt = <880000>;
51 clock-latency-ns = <500000>;
53 opp-800000000 {
54 opp-hz = /bits/ 64 <800000000>;
55 opp-microvolt = <880000>;
56 clock-latency-ns = <500000>;
58 opp-1000000000 {
59 opp-hz = /bits/ 64 <1000000000>;
60 opp-microvolt = <880000>;
61 clock-latency-ns = <500000>;
63 opp-1200000000 {
64 opp-hz = /bits/ 64 <1200000000>;
65 opp-microvolt = <880000>;
66 clock-latency-ns = <500000>;
67 opp-suspend;
72 #address-cells = <1>;
73 #size-cells = <0>;
75 cpu-map {
78 cpu = <&a55_0>;
81 cpu = <&a55_1>;
87 cpu = <&a55_2>;
90 cpu = <&a55_3>;
96 cpu = <&a55_4>;
99 cpu = <&a55_5>;
105 cpu = <&a55_6>;
108 cpu = <&a55_7>;
113 a55_0: cpu@0 {
114 compatible = "arm,cortex-a55";
116 device_type = "cpu";
117 power-domains = <&sysc R8A779F0_PD_A1E0D0C0>;
118 next-level-cache = <&L3_CA55_0>;
119 enable-method = "psci";
120 cpu-idle-states = <&CPU_SLEEP_0>;
122 operating-points-v2 = <&cluster01_opp>;
125 a55_1: cpu@100 {
126 compatible = "arm,cortex-a55";
128 device_type = "cpu";
129 power-domains = <&sysc R8A779F0_PD_A1E0D0C1>;
130 next-level-cache = <&L3_CA55_0>;
131 enable-method = "psci";
132 cpu-idle-states = <&CPU_SLEEP_0>;
134 operating-points-v2 = <&cluster01_opp>;
137 a55_2: cpu@10000 {
138 compatible = "arm,cortex-a55";
140 device_type = "cpu";
141 power-domains = <&sysc R8A779F0_PD_A1E0D1C0>;
142 next-level-cache = <&L3_CA55_1>;
143 enable-method = "psci";
144 cpu-idle-states = <&CPU_SLEEP_0>;
146 operating-points-v2 = <&cluster01_opp>;
149 a55_3: cpu@10100 {
150 compatible = "arm,cortex-a55";
152 device_type = "cpu";
153 power-domains = <&sysc R8A779F0_PD_A1E0D1C1>;
154 next-level-cache = <&L3_CA55_1>;
155 enable-method = "psci";
156 cpu-idle-states = <&CPU_SLEEP_0>;
158 operating-points-v2 = <&cluster01_opp>;
161 a55_4: cpu@20000 {
162 compatible = "arm,cortex-a55";
164 device_type = "cpu";
165 power-domains = <&sysc R8A779F0_PD_A1E1D0C0>;
166 next-level-cache = <&L3_CA55_2>;
167 enable-method = "psci";
168 cpu-idle-states = <&CPU_SLEEP_0>;
170 operating-points-v2 = <&cluster23_opp>;
173 a55_5: cpu@20100 {
174 compatible = "arm,cortex-a55";
176 device_type = "cpu";
177 power-domains = <&sysc R8A779F0_PD_A1E1D0C1>;
178 next-level-cache = <&L3_CA55_2>;
179 enable-method = "psci";
180 cpu-idle-states = <&CPU_SLEEP_0>;
182 operating-points-v2 = <&cluster23_opp>;
185 a55_6: cpu@30000 {
186 compatible = "arm,cortex-a55";
188 device_type = "cpu";
189 power-domains = <&sysc R8A779F0_PD_A1E1D1C0>;
190 next-level-cache = <&L3_CA55_3>;
191 enable-method = "psci";
192 cpu-idle-states = <&CPU_SLEEP_0>;
194 operating-points-v2 = <&cluster23_opp>;
197 a55_7: cpu@30100 {
198 compatible = "arm,cortex-a55";
200 device_type = "cpu";
201 power-domains = <&sysc R8A779F0_PD_A1E1D1C1>;
202 next-level-cache = <&L3_CA55_3>;
203 enable-method = "psci";
204 cpu-idle-states = <&CPU_SLEEP_0>;
206 operating-points-v2 = <&cluster23_opp>;
209 L3_CA55_0: cache-controller-0 {
211 power-domains = <&sysc R8A779F0_PD_A2E0D0>;
212 cache-unified;
213 cache-level = <3>;
216 L3_CA55_1: cache-controller-1 {
218 power-domains = <&sysc R8A779F0_PD_A2E0D1>;
219 cache-unified;
220 cache-level = <3>;
223 L3_CA55_2: cache-controller-2 {
225 power-domains = <&sysc R8A779F0_PD_A2E1D0>;
226 cache-unified;
227 cache-level = <3>;
230 L3_CA55_3: cache-controller-3 {
232 power-domains = <&sysc R8A779F0_PD_A2E1D1>;
233 cache-unified;
234 cache-level = <3>;
237 idle-states {
238 entry-method = "psci";
240 CPU_SLEEP_0: cpu-sleep-0 {
241 compatible = "arm,idle-state";
242 arm,psci-suspend-param = <0x0010000>;
243 local-timer-stop;
244 entry-latency-us = <400>;
245 exit-latency-us = <500>;
246 min-residency-us = <4000>;
252 compatible = "fixed-clock";
253 #clock-cells = <0>;
255 clock-frequency = <0>;
256 bootph-all;
260 compatible = "fixed-clock";
261 #clock-cells = <0>;
263 clock-frequency = <0>;
264 bootph-all;
267 pcie0_clkref: pcie0-clkref {
268 compatible = "fixed-clock";
269 #clock-cells = <0>;
271 clock-frequency = <0>;
274 pcie1_clkref: pcie1-clkref {
275 compatible = "fixed-clock";
276 #clock-cells = <0>;
278 clock-frequency = <0>;
282 compatible = "arm,cortex-a55-pmu";
283 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
287 compatible = "arm,psci-1.0", "arm,psci-0.2";
291 /* External SCIF clock - to be overridden by boards that provide it */
293 compatible = "fixed-clock";
294 #clock-cells = <0>;
295 clock-frequency = <0>;
299 compatible = "simple-bus";
300 interrupt-parent = <&gic>;
301 bootph-all;
303 #address-cells = <2>;
304 #size-cells = <2>;
308 compatible = "renesas,r8a779f0-wdt",
309 "renesas,rcar-gen4-wdt";
313 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
319 compatible = "renesas,pfc-r8a779f0";
322 bootph-all;
326 compatible = "renesas,gpio-r8a779f0",
327 "renesas,rcar-gen4-gpio";
331 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
333 gpio-controller;
334 #gpio-cells = <2>;
335 gpio-ranges = <&pfc 0 0 21>;
336 interrupt-controller;
337 #interrupt-cells = <2>;
341 compatible = "renesas,gpio-r8a779f0",
342 "renesas,rcar-gen4-gpio";
346 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
348 gpio-controller;
349 #gpio-cells = <2>;
350 gpio-ranges = <&pfc 0 32 25>;
351 interrupt-controller;
352 #interrupt-cells = <2>;
356 compatible = "renesas,gpio-r8a779f0",
357 "renesas,rcar-gen4-gpio";
361 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
363 gpio-controller;
364 #gpio-cells = <2>;
365 gpio-ranges = <&pfc 0 64 17>;
366 interrupt-controller;
367 #interrupt-cells = <2>;
371 compatible = "renesas,gpio-r8a779f0",
372 "renesas,rcar-gen4-gpio";
376 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
378 gpio-controller;
379 #gpio-cells = <2>;
380 gpio-ranges = <&pfc 0 96 19>;
381 interrupt-controller;
382 #interrupt-cells = <2>;
386 compatible = "renesas,r8a779f0-efuse";
389 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
394 compatible = "renesas,r8a779f0-cmt0",
395 "renesas,rcar-gen4-cmt0";
400 clock-names = "fck";
401 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
407 compatible = "renesas,r8a779f0-cmt1",
408 "renesas,rcar-gen4-cmt1";
419 clock-names = "fck";
420 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
426 compatible = "renesas,r8a779f0-cmt1",
427 "renesas,rcar-gen4-cmt1";
438 clock-names = "fck";
439 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
445 compatible = "renesas,r8a779f0-cmt1",
446 "renesas,rcar-gen4-cmt1";
457 clock-names = "fck";
458 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
463 cpg: clock-controller@e6150000 {
464 compatible = "renesas,r8a779f0-cpg-mssr";
467 clock-names = "extal", "extalr";
468 #clock-cells = <2>;
469 #power-domain-cells = <0>;
470 #reset-cells = <1>;
471 bootph-all;
474 rst: reset-controller@e6160000 {
475 compatible = "renesas,r8a779f0-rst";
477 bootph-all;
480 sysc: system-controller@e6180000 {
481 compatible = "renesas,r8a779f0-sysc";
483 #power-domain-cells = <1>;
487 compatible = "renesas,r8a779f0-thermal";
493 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
495 #thermal-sensor-cells = <1>;
498 intc_ex: interrupt-controller@e61c0000 {
499 compatible = "renesas,intc-ex-r8a779f0", "renesas,irqc";
500 #interrupt-cells = <2>;
501 interrupt-controller;
510 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
514 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
519 interrupt-names = "tuni0", "tuni1", "tuni2";
521 clock-names = "fck";
522 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
528 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
534 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
536 clock-names = "fck";
537 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
543 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
549 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
551 clock-names = "fck";
552 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
558 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
564 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
566 clock-names = "fck";
567 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
573 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
579 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
581 clock-names = "fck";
582 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
588 compatible = "renesas,r8a779f0-ether-serdes";
591 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
593 #phy-cells = <1>;
598 compatible = "renesas,i2c-r8a779f0",
599 "renesas,rcar-gen4-i2c";
603 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
607 dma-names = "tx", "rx", "tx", "rx";
608 i2c-scl-internal-delay-ns = <110>;
609 #address-cells = <1>;
610 #size-cells = <0>;
615 compatible = "renesas,i2c-r8a779f0",
616 "renesas,rcar-gen4-i2c";
620 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
624 dma-names = "tx", "rx", "tx", "rx";
625 i2c-scl-internal-delay-ns = <110>;
626 #address-cells = <1>;
627 #size-cells = <0>;
632 compatible = "renesas,i2c-r8a779f0",
633 "renesas,rcar-gen4-i2c";
637 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
641 dma-names = "tx", "rx", "tx", "rx";
642 i2c-scl-internal-delay-ns = <110>;
643 #address-cells = <1>;
644 #size-cells = <0>;
649 compatible = "renesas,i2c-r8a779f0",
650 "renesas,rcar-gen4-i2c";
654 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
658 dma-names = "tx", "rx", "tx", "rx";
659 i2c-scl-internal-delay-ns = <110>;
660 #address-cells = <1>;
661 #size-cells = <0>;
666 compatible = "renesas,i2c-r8a779f0",
667 "renesas,rcar-gen4-i2c";
671 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
675 dma-names = "tx", "rx", "tx", "rx";
676 i2c-scl-internal-delay-ns = <110>;
677 #address-cells = <1>;
678 #size-cells = <0>;
683 compatible = "renesas,i2c-r8a779f0",
684 "renesas,rcar-gen4-i2c";
688 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
692 dma-names = "tx", "rx", "tx", "rx";
693 i2c-scl-internal-delay-ns = <110>;
694 #address-cells = <1>;
695 #size-cells = <0>;
700 compatible = "renesas,hscif-r8a779f0",
701 "renesas,rcar-gen4-hscif", "renesas,hscif";
707 clock-names = "fck", "brg_int", "scif_clk";
710 dma-names = "tx", "rx", "tx", "rx";
711 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
717 compatible = "renesas,hscif-r8a779f0",
718 "renesas,rcar-gen4-hscif", "renesas,hscif";
724 clock-names = "fck", "brg_int", "scif_clk";
727 dma-names = "tx", "rx", "tx", "rx";
728 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
734 compatible = "renesas,hscif-r8a779f0",
735 "renesas,rcar-gen4-hscif", "renesas,hscif";
741 clock-names = "fck", "brg_int", "scif_clk";
744 dma-names = "tx", "rx", "tx", "rx";
745 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
751 compatible = "renesas,hscif-r8a779f0",
752 "renesas,rcar-gen4-hscif", "renesas,hscif";
758 clock-names = "fck", "brg_int", "scif_clk";
761 dma-names = "tx", "rx", "tx", "rx";
762 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
768 compatible = "renesas,r8a779f0-pcie",
769 "renesas,rcar-gen4-pcie";
774 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";
779 interrupt-names = "msi", "dma", "sft_ce", "app";
781 clock-names = "core", "ref";
782 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
784 reset-names = "pwr";
785 max-link-speed = <4>;
786 num-lanes = <2>;
787 #address-cells = <3>;
788 #size-cells = <2>;
789 bus-range = <0x00 0xff>;
793 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
794 #interrupt-cells = <1>;
795 interrupt-map-mask = <0 0 0 7>;
796 interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
800 snps,enable-cdm-check;
805 compatible = "renesas,r8a779f0-pcie",
806 "renesas,rcar-gen4-pcie";
811 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";
816 interrupt-names = "msi", "dma", "sft_ce", "app";
818 clock-names = "core", "ref";
819 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
821 reset-names = "pwr";
822 max-link-speed = <4>;
823 num-lanes = <2>;
824 #address-cells = <3>;
825 #size-cells = <2>;
826 bus-range = <0x00 0xff>;
830 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
831 #interrupt-cells = <1>;
832 interrupt-map-mask = <0 0 0 7>;
833 interrupt-map = <0 0 0 1 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
837 snps,enable-cdm-check;
841 pciec0_ep: pcie-ep@e65d0000 {
842 compatible = "renesas,r8a779f0-pcie-ep",
843 "renesas,rcar-gen4-pcie-ep";
848 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space";
852 interrupt-names = "dma", "sft_ce", "app";
854 clock-names = "core", "ref";
855 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
857 reset-names = "pwr";
858 max-link-speed = <4>;
859 num-lanes = <2>;
860 max-functions = /bits/ 8 <2>;
864 pciec1_ep: pcie-ep@e65d8000 {
865 compatible = "renesas,r8a779f0-pcie-ep",
866 "renesas,rcar-gen4-pcie-ep";
871 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space";
875 interrupt-names = "dma", "sft_ce", "app";
877 clock-names = "core", "ref";
878 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
880 reset-names = "pwr";
881 max-link-speed = <4>;
882 num-lanes = <2>;
883 max-functions = /bits/ 8 <2>;
887 ufs: ufs@e6860000 { label
888 compatible = "renesas,r8a779f0-ufs";
892 clock-names = "fck", "ref_clk";
893 freq-table-hz = <200000000 200000000>, <38400000 38400000>;
894 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
900 compatible = "renesas,r8a779f0-ether-switch";
902 reg-names = "base", "secure_base";
950 interrupt-names = "mfwd_error", "race_error",
976 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
980 ethernet-ports {
981 #address-cells = <1>;
982 #size-cells = <0>;
1003 compatible = "renesas,scif-r8a779f0",
1004 "renesas,rcar-gen4-scif", "renesas,scif";
1010 clock-names = "fck", "brg_int", "scif_clk";
1013 dma-names = "tx", "rx", "tx", "rx";
1014 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1020 compatible = "renesas,scif-r8a779f0",
1021 "renesas,rcar-gen4-scif", "renesas,scif";
1027 clock-names = "fck", "brg_int", "scif_clk";
1030 dma-names = "tx", "rx", "tx", "rx";
1031 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1037 compatible = "renesas,scif-r8a779f0",
1038 "renesas,rcar-gen4-scif", "renesas,scif";
1044 clock-names = "fck", "brg_int", "scif_clk";
1047 dma-names = "tx", "rx", "tx", "rx";
1048 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1054 compatible = "renesas,scif-r8a779f0",
1055 "renesas,rcar-gen4-scif", "renesas,scif";
1061 clock-names = "fck", "brg_int", "scif_clk";
1064 dma-names = "tx", "rx", "tx", "rx";
1065 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1071 compatible = "renesas,msiof-r8a779f0",
1072 "renesas,rcar-gen4-msiof";
1078 dma-names = "tx", "rx", "tx", "rx";
1079 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1081 #address-cells = <1>;
1082 #size-cells = <0>;
1087 compatible = "renesas,msiof-r8a779f0",
1088 "renesas,rcar-gen4-msiof";
1094 dma-names = "tx", "rx", "tx", "rx";
1095 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1097 #address-cells = <1>;
1098 #size-cells = <0>;
1103 compatible = "renesas,msiof-r8a779f0",
1104 "renesas,rcar-gen4-msiof";
1110 dma-names = "tx", "rx", "tx", "rx";
1111 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1113 #address-cells = <1>;
1114 #size-cells = <0>;
1119 compatible = "renesas,msiof-r8a779f0",
1120 "renesas,rcar-gen4-msiof";
1126 dma-names = "tx", "rx", "tx", "rx";
1127 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1129 #address-cells = <1>;
1130 #size-cells = <0>;
1134 dmac0: dma-controller@e7350000 {
1135 compatible = "renesas,dmac-r8a779f0",
1136 "renesas,rcar-gen4-dmac";
1156 interrupt-names = "error",
1162 clock-names = "fck";
1163 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1165 #dma-cells = <1>;
1166 dma-channels = <16>;
1177 dmac1: dma-controller@e7351000 {
1178 compatible = "renesas,dmac-r8a779f0",
1179 "renesas,rcar-gen4-dmac";
1199 interrupt-names = "error",
1205 clock-names = "fck";
1206 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1208 #dma-cells = <1>;
1209 dma-channels = <16>;
1221 compatible = "renesas,sdhi-r8a779f0",
1222 "renesas,rcar-gen4-sdhi";
1226 clock-names = "core", "clkh";
1227 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1229 max-frequency = <200000000>;
1235 compatible = "renesas,ipmmu-r8a779f0",
1236 "renesas,rcar-gen4-ipmmu-vmsa";
1238 renesas,ipmmu-main = <&ipmmu_mm>;
1239 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1240 #iommu-cells = <1>;
1244 compatible = "renesas,ipmmu-r8a779f0",
1245 "renesas,rcar-gen4-ipmmu-vmsa";
1247 renesas,ipmmu-main = <&ipmmu_mm>;
1248 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1249 #iommu-cells = <1>;
1253 compatible = "renesas,ipmmu-r8a779f0",
1254 "renesas,rcar-gen4-ipmmu-vmsa";
1256 renesas,ipmmu-main = <&ipmmu_mm>;
1257 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1258 #iommu-cells = <1>;
1262 compatible = "renesas,ipmmu-r8a779f0",
1263 "renesas,rcar-gen4-ipmmu-vmsa";
1265 renesas,ipmmu-main = <&ipmmu_mm>;
1266 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1267 #iommu-cells = <1>;
1271 compatible = "renesas,ipmmu-r8a779f0",
1272 "renesas,rcar-gen4-ipmmu-vmsa";
1276 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1277 #iommu-cells = <1>;
1280 gic: interrupt-controller@f1000000 {
1281 compatible = "arm,gic-v3";
1282 #interrupt-cells = <3>;
1283 #address-cells = <0>;
1284 interrupt-controller;
1293 bootph-all;
1297 thermal-zones {
1298 sensor_thermal_rtcore: sensor1-thermal {
1299 polling-delay-passive = <250>;
1300 polling-delay = <1000>;
1301 thermal-sensors = <&tsc 0>;
1304 sensor1_crit: sensor1-crit {
1312 sensor_thermal_apcore0: sensor2-thermal {
1313 polling-delay-passive = <250>;
1314 polling-delay = <1000>;
1315 thermal-sensors = <&tsc 1>;
1318 sensor2_crit: sensor2-crit {
1326 sensor_thermal_apcore4: sensor3-thermal {
1327 polling-delay-passive = <250>;
1328 polling-delay = <1000>;
1329 thermal-sensors = <&tsc 2>;
1332 sensor3_crit: sensor3-crit {
1342 compatible = "arm,armv8-timer";
1343 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
1348 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
1349 "hyp-virt";
1352 ufs30_clk: ufs30-clk {
1353 compatible = "fixed-clock";
1354 #clock-cells = <0>;
1356 clock-frequency = <0>;