Lines Matching +full:0 +full:xe6160000
17 cluster01_opp: opp-table-0 {
73 #size-cells = <0>;
113 a55_0: cpu@0 {
115 reg = <0>;
127 reg = <0x100>;
139 reg = <0x10000>;
151 reg = <0x10100>;
163 reg = <0x20000>;
175 reg = <0x20100>;
187 reg = <0x30000>;
199 reg = <0x30100>;
209 L3_CA55_0: cache-controller-0 {
240 CPU_SLEEP_0: cpu-sleep-0 {
242 arm,psci-suspend-param = <0x0010000>;
253 #clock-cells = <0>;
255 clock-frequency = <0>;
260 #clock-cells = <0>;
262 clock-frequency = <0>;
267 #clock-cells = <0>;
269 clock-frequency = <0>;
274 #clock-cells = <0>;
276 clock-frequency = <0>;
292 #clock-cells = <0>;
293 clock-frequency = <0>;
306 reg = <0 0xe6020000 0 0x0c>;
316 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
317 <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>;
323 reg = <0 0xe6050180 0 0x54>;
330 gpio-ranges = <&pfc 0 0 21>;
338 reg = <0 0xe6050980 0 0x54>;
345 gpio-ranges = <&pfc 0 32 25>;
353 reg = <0 0xe6051180 0 0x54>;
360 gpio-ranges = <&pfc 0 64 17>;
368 reg = <0 0xe6051980 0 0x54>;
375 gpio-ranges = <&pfc 0 96 19>;
383 reg = <0 0xe60f0000 0 0x1004>;
396 reg = <0 0xe6130000 0 0x1004>;
415 reg = <0 0xe6140000 0 0x1004>;
434 reg = <0 0xe6148000 0 0x1004>;
452 reg = <0 0xe6150000 0 0x4000>;
456 #power-domain-cells = <0>;
462 reg = <0 0xe6160000 0 0x4000>;
467 reg = <0 0xe6180000 0 0x4000>;
474 reg = <0 0xe6198000 0 0x200>,
475 <0 0xe61a0000 0 0x200>,
476 <0 0xe61a8000 0 0x200>;
487 reg = <0 0xe61c0000 0 0x200>;
488 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
500 reg = <0 0xe61e0000 0 0x30>;
514 reg = <0 0xe6fc0000 0 0x30>;
529 reg = <0 0xe6fd0000 0 0x30>;
544 reg = <0 0xe6fe0000 0 0x30>;
559 reg = <0 0xffc00000 0 0x30>;
574 reg = <0 0xe6444000 0 0x2800>;
585 reg = <0 0xe6500000 0 0x40>;
590 dmas = <&dmac0 0x91>, <&dmac0 0x90>,
591 <&dmac1 0x91>, <&dmac1 0x90>;
595 #size-cells = <0>;
602 reg = <0 0xe6508000 0 0x40>;
607 dmas = <&dmac0 0x93>, <&dmac0 0x92>,
608 <&dmac1 0x93>, <&dmac1 0x92>;
612 #size-cells = <0>;
619 reg = <0 0xe6510000 0 0x40>;
620 interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>;
624 dmas = <&dmac0 0x95>, <&dmac0 0x94>,
625 <&dmac1 0x95>, <&dmac1 0x94>;
629 #size-cells = <0>;
636 reg = <0 0xe66d0000 0 0x40>;
641 dmas = <&dmac0 0x97>, <&dmac0 0x96>,
642 <&dmac1 0x97>, <&dmac1 0x96>;
646 #size-cells = <0>;
653 reg = <0 0xe66d8000 0 0x40>;
658 dmas = <&dmac0 0x99>, <&dmac0 0x98>,
659 <&dmac1 0x99>, <&dmac1 0x98>;
663 #size-cells = <0>;
670 reg = <0 0xe66e0000 0 0x40>;
675 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>,
676 <&dmac1 0x9b>, <&dmac1 0x9a>;
680 #size-cells = <0>;
687 reg = <0 0xe6540000 0 0x60>;
693 dmas = <&dmac0 0x31>, <&dmac0 0x30>,
694 <&dmac1 0x31>, <&dmac1 0x30>;
704 reg = <0 0xe6550000 0 0x60>;
710 dmas = <&dmac0 0x33>, <&dmac0 0x32>,
711 <&dmac1 0x33>, <&dmac1 0x32>;
721 reg = <0 0xe6560000 0 0x60>;
727 dmas = <&dmac0 0x35>, <&dmac0 0x34>,
728 <&dmac1 0x35>, <&dmac1 0x34>;
738 reg = <0 0xe66a0000 0 0x60>;
744 dmas = <&dmac0 0x37>, <&dmac0 0x36>,
745 <&dmac1 0x37>, <&dmac1 0x36>;
755 reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,
756 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
757 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
758 <0 0xfe000000 0 0x400000>;
774 bus-range = <0x00 0xff>;
776 ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>,
777 <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>;
778 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
780 interrupt-map-mask = <0 0 0 7>;
781 interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
782 <0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
783 <0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
784 <0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>;
792 reg = <0 0xe65d8000 0 0x1000>, <0 0xe65da000 0 0x0800>,
793 <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>,
794 <0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>,
795 <0 0xee900000 0 0x400000>;
811 bus-range = <0x00 0xff>;
813 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00400000>,
814 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x10000000>;
815 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
817 interrupt-map-mask = <0 0 0 7>;
818 interrupt-map = <0 0 0 1 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
819 <0 0 0 2 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
820 <0 0 0 3 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
821 <0 0 0 4 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
829 reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>,
830 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
831 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
832 <0 0xfe000000 0 0x400000>;
852 reg = <0 0xe65d8000 0 0x2000>, <0 0xe65da000 0 0x1000>,
853 <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>,
854 <0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>,
855 <0 0xee900000 0 0x400000>;
874 reg = <0 0xe6860000 0 0x100>;
886 reg = <0 0xe6880000 0 0x20000>, <0 0xe68c0000 0 0x20000>;
967 #size-cells = <0>;
969 port@0 {
970 reg = <0>;
971 phys = <ð_serdes 0>;
987 reg = <0 0xe6e60000 0 64>;
993 dmas = <&dmac0 0x51>, <&dmac0 0x50>,
994 <&dmac1 0x51>, <&dmac1 0x50>;
1004 reg = <0 0xe6e68000 0 64>;
1010 dmas = <&dmac0 0x53>, <&dmac0 0x52>,
1011 <&dmac1 0x53>, <&dmac1 0x52>;
1021 reg = <0 0xe6c50000 0 64>;
1027 dmas = <&dmac0 0x57>, <&dmac0 0x56>,
1028 <&dmac1 0x57>, <&dmac1 0x56>;
1038 reg = <0 0xe6c40000 0 64>;
1044 dmas = <&dmac0 0x59>, <&dmac0 0x58>,
1045 <&dmac1 0x59>, <&dmac1 0x58>;
1055 reg = <0 0xe6e90000 0 0x0064>;
1058 dmas = <&dmac0 0x41>, <&dmac0 0x40>,
1059 <&dmac1 0x41>, <&dmac1 0x40>;
1064 #size-cells = <0>;
1071 reg = <0 0xe6ea0000 0 0x0064>;
1074 dmas = <&dmac0 0x43>, <&dmac0 0x42>,
1075 <&dmac1 0x43>, <&dmac1 0x42>;
1080 #size-cells = <0>;
1087 reg = <0 0xe6c00000 0 0x0064>;
1090 dmas = <&dmac0 0x45>, <&dmac0 0x44>,
1091 <&dmac1 0x45>, <&dmac1 0x44>;
1096 #size-cells = <0>;
1103 reg = <0 0xe6c10000 0 0x0064>;
1106 dmas = <&dmac0 0x47>, <&dmac0 0x46>,
1107 <&dmac1 0x47>, <&dmac1 0x46>;
1112 #size-cells = <0>;
1119 reg = <0 0xe7350000 0 0x1000>,
1120 <0 0xe7300000 0 0x10000>;
1149 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
1162 reg = <0 0xe7351000 0 0x1000>,
1163 <0 0xe7310000 0 0x10000>;
1205 reg = <0 0xee140000 0 0x2000>;
1219 reg = <0 0xee480000 0 0x20000>;
1228 reg = <0 0xee4c0000 0 0x20000>;
1237 reg = <0 0xeed00000 0 0x20000>;
1246 reg = <0 0xeed40000 0 0x20000>;
1255 reg = <0 0xeefc0000 0 0x20000>;
1265 #address-cells = <0>;
1267 reg = <0x0 0xf1000000 0 0x20000>,
1268 <0x0 0xf1060000 0 0x110000>;
1274 reg = <0 0xfff00044 0 4>;
1282 thermal-sensors = <&tsc 0>;
1335 #clock-cells = <0>;
1337 clock-frequency = <0>;