Lines Matching +full:0 +full:xe6ef2000
20 #clock-cells = <0>;
21 clock-frequency = <0>;
26 #size-cells = <0>;
28 a76_0: cpu@0 {
30 reg = <0>;
37 L3_CA76_0: cache-controller-0 {
47 #clock-cells = <0>;
49 clock-frequency = <0>;
54 #clock-cells = <0>;
56 clock-frequency = <0>;
67 #clock-cells = <0>;
68 clock-frequency = <0>;
81 reg = <0 0xe6020000 0 0x0c>;
91 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
92 <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
93 <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
94 <0 0xe6068000 0 0x16c>, <0 0xe6068800 0 0x16c>,
95 <0 0xe6069000 0 0x16c>, <0 0xe6069800 0 0x16c>;
101 reg = <0 0xe6058180 0 0x54>;
108 gpio-ranges = <&pfc 0 0 28>;
116 reg = <0 0xe6050180 0 0x54>;
123 gpio-ranges = <&pfc 0 32 31>;
131 reg = <0 0xe6050980 0 0x54>;
138 gpio-ranges = <&pfc 0 64 25>;
146 reg = <0 0xe6058980 0 0x54>;
153 gpio-ranges = <&pfc 0 96 17>;
161 reg = <0 0xe6060180 0 0x54>;
168 gpio-ranges = <&pfc 0 128 27>;
176 reg = <0 0xe6060980 0 0x54>;
183 gpio-ranges = <&pfc 0 160 21>;
191 reg = <0 0xe6068180 0 0x54>;
198 gpio-ranges = <&pfc 0 192 21>;
206 reg = <0 0xe6068980 0 0x54>;
213 gpio-ranges = <&pfc 0 224 21>;
221 reg = <0 0xe6069180 0 0x54>;
228 gpio-ranges = <&pfc 0 256 21>;
236 reg = <0 0xe6069980 0 0x54>;
243 gpio-ranges = <&pfc 0 288 21>;
250 reg = <0 0xe6078800 0 0x100>;
259 reg = <0 0xe60f0000 0 0x1004>;
272 reg = <0 0xe6130000 0 0x1004>;
291 reg = <0 0xe6140000 0 0x1004>;
310 reg = <0 0xe6148000 0 0x1004>;
328 reg = <0 0xe6150000 0 0x4000>;
332 #power-domain-cells = <0>;
338 reg = <0 0xe6160000 0 0x4000>;
343 reg = <0 0xe6180000 0 0x4000>;
349 reg = <0 0xe6190000 0 0x200>,
350 <0 0xe6198000 0 0x200>,
351 <0 0xe61a0000 0 0x200>,
352 <0 0xe61a8000 0 0x200>,
353 <0 0xe61b0000 0 0x200>;
364 reg = <0 0xe61c0000 0 0x200>;
365 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
377 reg = <0 0xe61e0000 0 0x30>;
391 reg = <0 0xe6fc0000 0 0x30>;
406 reg = <0 0xe6fd0000 0 0x30>;
421 reg = <0 0xe6fe0000 0 0x30>;
436 reg = <0 0xffc00000 0 0x30>;
452 reg = <0 0xe6500000 0 0x40>;
457 dmas = <&dmac1 0x91>, <&dmac1 0x90>;
461 #size-cells = <0>;
468 reg = <0 0xe6508000 0 0x40>;
473 dmas = <&dmac1 0x93>, <&dmac1 0x92>;
477 #size-cells = <0>;
484 reg = <0 0xe6510000 0 0x40>;
489 dmas = <&dmac1 0x95>, <&dmac1 0x94>;
493 #size-cells = <0>;
500 reg = <0 0xe66d0000 0 0x40>;
505 dmas = <&dmac1 0x97>, <&dmac1 0x96>;
509 #size-cells = <0>;
516 reg = <0 0xe66d8000 0 0x40>;
521 dmas = <&dmac1 0x99>, <&dmac1 0x98>;
525 #size-cells = <0>;
532 reg = <0 0xe66e0000 0 0x40>;
537 dmas = <&dmac1 0x9b>, <&dmac1 0x9a>;
541 #size-cells = <0>;
548 reg = <0 0xe66e8000 0 0x40>;
553 dmas = <&dmac1 0x9d>, <&dmac1 0x9c>;
557 #size-cells = <0>;
564 reg = <0 0xe6540000 0 0x60>;
570 dmas = <&dmac1 0x31>, <&dmac1 0x30>;
580 reg = <0 0xe6550000 0 0x60>;
586 dmas = <&dmac1 0x33>, <&dmac1 0x32>;
596 reg = <0 0xe6560000 0 0x60>;
602 dmas = <&dmac1 0x35>, <&dmac1 0x34>;
612 reg = <0 0xe66a0000 0 0x60>;
618 dmas = <&dmac1 0x37>, <&dmac1 0x36>;
628 reg = <0 0xe6660000 0 0x8000>;
678 reg = <0 0xe6800000 0 0x1000>;
716 rx-internal-delay-ps = <0>;
717 tx-internal-delay-ps = <0>;
718 iommus = <&ipmmu_ds1 0>;
720 #size-cells = <0>;
727 reg = <0 0xe6810000 0 0x1000>;
765 rx-internal-delay-ps = <0>;
766 tx-internal-delay-ps = <0>;
769 #size-cells = <0>;
776 reg = <0 0xe6820000 0 0x1000>;
814 rx-internal-delay-ps = <0>;
815 tx-internal-delay-ps = <0>;
818 #size-cells = <0>;
825 reg = <0 0xe6830000 0 0x1000>;
863 rx-internal-delay-ps = <0>;
864 tx-internal-delay-ps = <0>;
867 #size-cells = <0>;
874 reg = <0 0xe6840000 0 0x1000>;
912 rx-internal-delay-ps = <0>;
913 tx-internal-delay-ps = <0>;
916 #size-cells = <0>;
923 reg = <0 0xe6850000 0 0x1000>;
961 rx-internal-delay-ps = <0>;
962 tx-internal-delay-ps = <0>;
965 #size-cells = <0>;
971 reg = <0 0xe6e30000 0 0x10>;
981 reg = <0 0xe6e31000 0 0x10>;
991 reg = <0 0xe6e32000 0 0x10>;
1001 reg = <0 0xe6e33000 0 0x10>;
1011 reg = <0 0xe6e34000 0 0x10>;
1022 reg = <0 0xe6e60000 0 64>;
1028 dmas = <&dmac1 0x51>, <&dmac1 0x50>;
1038 reg = <0 0xe6e68000 0 64>;
1044 dmas = <&dmac1 0x53>, <&dmac1 0x52>;
1054 reg = <0 0xe6c50000 0 64>;
1060 dmas = <&dmac1 0x57>, <&dmac1 0x56>;
1070 reg = <0 0xe6c40000 0 64>;
1076 dmas = <&dmac1 0x59>, <&dmac1 0x58>;
1085 reg = <0 0xe6e80000 0 0x148>;
1097 reg = <0 0xe6e90000 0 0x0064>;
1102 dmas = <&dmac1 0x41>, <&dmac1 0x40>;
1105 #size-cells = <0>;
1112 reg = <0 0xe6ea0000 0 0x0064>;
1117 dmas = <&dmac1 0x43>, <&dmac1 0x42>;
1120 #size-cells = <0>;
1127 reg = <0 0xe6c00000 0 0x0064>;
1132 dmas = <&dmac1 0x45>, <&dmac1 0x44>;
1135 #size-cells = <0>;
1142 reg = <0 0xe6c10000 0 0x0064>;
1147 dmas = <&dmac1 0x47>, <&dmac1 0x46>;
1150 #size-cells = <0>;
1157 reg = <0 0xe6c20000 0 0x0064>;
1162 dmas = <&dmac1 0x49>, <&dmac1 0x48>;
1165 #size-cells = <0>;
1172 reg = <0 0xe6c28000 0 0x0064>;
1177 dmas = <&dmac1 0x4b>, <&dmac1 0x4a>;
1180 #size-cells = <0>;
1187 reg = <0 0xe6ef0000 0 0x1000>;
1192 renesas,id = <0>;
1197 #size-cells = <0>;
1201 #size-cells = <0>;
1205 vin00isp0: endpoint@0 {
1206 reg = <0>;
1216 reg = <0 0xe6ef1000 0 0x1000>;
1226 #size-cells = <0>;
1230 #size-cells = <0>;
1234 vin01isp0: endpoint@0 {
1235 reg = <0>;
1245 reg = <0 0xe6ef2000 0 0x1000>;
1255 #size-cells = <0>;
1259 #size-cells = <0>;
1263 vin02isp0: endpoint@0 {
1264 reg = <0>;
1274 reg = <0 0xe6ef3000 0 0x1000>;
1284 #size-cells = <0>;
1288 #size-cells = <0>;
1292 vin03isp0: endpoint@0 {
1293 reg = <0>;
1303 reg = <0 0xe6ef4000 0 0x1000>;
1313 #size-cells = <0>;
1317 #size-cells = <0>;
1321 vin04isp0: endpoint@0 {
1322 reg = <0>;
1332 reg = <0 0xe6ef5000 0 0x1000>;
1342 #size-cells = <0>;
1346 #size-cells = <0>;
1350 vin05isp0: endpoint@0 {
1351 reg = <0>;
1361 reg = <0 0xe6ef6000 0 0x1000>;
1371 #size-cells = <0>;
1375 #size-cells = <0>;
1379 vin06isp0: endpoint@0 {
1380 reg = <0>;
1390 reg = <0 0xe6ef7000 0 0x1000>;
1400 #size-cells = <0>;
1404 #size-cells = <0>;
1408 vin07isp0: endpoint@0 {
1409 reg = <0>;
1419 reg = <0 0xe6ef8000 0 0x1000>;
1429 #size-cells = <0>;
1433 #size-cells = <0>;
1448 reg = <0 0xe6ef9000 0 0x1000>;
1458 #size-cells = <0>;
1462 #size-cells = <0>;
1477 reg = <0 0xe6efa000 0 0x1000>;
1487 #size-cells = <0>;
1491 #size-cells = <0>;
1506 reg = <0 0xe6efb000 0 0x1000>;
1516 #size-cells = <0>;
1520 #size-cells = <0>;
1535 reg = <0 0xe6efc000 0 0x1000>;
1545 #size-cells = <0>;
1549 #size-cells = <0>;
1564 reg = <0 0xe6efd000 0 0x1000>;
1574 #size-cells = <0>;
1578 #size-cells = <0>;
1593 reg = <0 0xe6efe000 0 0x1000>;
1603 #size-cells = <0>;
1607 #size-cells = <0>;
1622 reg = <0 0xe6eff000 0 0x1000>;
1632 #size-cells = <0>;
1636 #size-cells = <0>;
1651 reg = <0 0xe6ed0000 0 0x1000>;
1661 #size-cells = <0>;
1665 #size-cells = <0>;
1680 reg = <0 0xe6ed1000 0 0x1000>;
1690 #size-cells = <0>;
1694 #size-cells = <0>;
1709 reg = <0 0xe6ed2000 0 0x1000>;
1719 #size-cells = <0>;
1723 #size-cells = <0>;
1738 reg = <0 0xe6ed3000 0 0x1000>;
1748 #size-cells = <0>;
1752 #size-cells = <0>;
1767 reg = <0 0xe6ed4000 0 0x1000>;
1777 #size-cells = <0>;
1781 #size-cells = <0>;
1796 reg = <0 0xe6ed5000 0 0x1000>;
1806 #size-cells = <0>;
1810 #size-cells = <0>;
1825 reg = <0 0xe6ed6000 0 0x1000>;
1835 #size-cells = <0>;
1839 #size-cells = <0>;
1854 reg = <0 0xe6ed7000 0 0x1000>;
1864 #size-cells = <0>;
1868 #size-cells = <0>;
1883 reg = <0 0xe6ed8000 0 0x1000>;
1893 #size-cells = <0>;
1897 #size-cells = <0>;
1912 reg = <0 0xe6ed9000 0 0x1000>;
1922 #size-cells = <0>;
1926 #size-cells = <0>;
1941 reg = <0 0xe6eda000 0 0x1000>;
1951 #size-cells = <0>;
1955 #size-cells = <0>;
1970 reg = <0 0xe6edb000 0 0x1000>;
1980 #size-cells = <0>;
1984 #size-cells = <0>;
1999 reg = <0 0xe6edc000 0 0x1000>;
2009 #size-cells = <0>;
2013 #size-cells = <0>;
2028 reg = <0 0xe6edd000 0 0x1000>;
2038 #size-cells = <0>;
2042 #size-cells = <0>;
2057 reg = <0 0xe6ede000 0 0x1000>;
2067 #size-cells = <0>;
2071 #size-cells = <0>;
2086 reg = <0 0xe6edf000 0 0x1000>;
2096 #size-cells = <0>;
2100 #size-cells = <0>;
2115 reg = <0 0xe7350000 0 0x1000>,
2116 <0 0xe7300000 0 0x10000>;
2145 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
2158 reg = <0 0xe7351000 0 0x1000>,
2159 <0 0xe7310000 0 0x10000>;
2187 reg = <0 0xee140000 0 0x2000>;
2201 reg = <0 0xee200000 0 0x200>,
2202 <0 0x08000000 0 0x04000000>,
2203 <0 0xee208000 0 0x100>;
2210 #size-cells = <0>;
2217 reg = <0 0xee480000 0 0x20000>;
2226 reg = <0 0xee4c0000 0 0x20000>;
2235 reg = <0 0xeed00000 0 0x20000>;
2244 reg = <0 0xeed40000 0 0x20000>;
2253 reg = <0 0xeed80000 0 0x20000>;
2262 reg = <0 0xeedc0000 0 0x20000>;
2271 reg = <0 0xeee80000 0 0x20000>;
2280 reg = <0 0xeeec0000 0 0x20000>;
2289 reg = <0 0xeee00000 0 0x20000>;
2298 reg = <0 0xeef00000 0 0x20000>;
2307 reg = <0 0xeef40000 0 0x20000>;
2316 reg = <0 0xeefc0000 0 0x20000>;
2326 #address-cells = <0>;
2328 reg = <0x0 0xf1000000 0 0x20000>,
2329 <0x0 0xf1060000 0 0x110000>;
2335 reg = <0 0xfea10000 0 0x200>;
2344 reg = <0 0xfea11000 0 0x200>;
2353 reg = <0 0xfea20000 0 0x5000>;
2364 reg = <0 0xfea28000 0 0x5000>;
2375 reg = <0 0xfeaa0000 0 0x10000>;
2384 #size-cells = <0>;
2386 port@0 {
2387 reg = <0>;
2401 reg = <0 0xfeab0000 0 0x10000>;
2410 #size-cells = <0>;
2412 port@0 {
2413 reg = <0>;
2427 reg = <0 0xfed60000 0 0x10000>;
2436 #size-cells = <0>;
2438 port@0 {
2439 reg = <0>;
2453 reg = <0 0xfed70000 0 0x10000>;
2462 #size-cells = <0>;
2464 port@0 {
2465 reg = <0>;
2479 reg = <0 0xfeb00000 0 0x40000>;
2483 clock-names = "du.0";
2486 reset-names = "du.0";
2487 renesas,vsps = <&vspd0 0>, <&vspd1 0>;
2493 #size-cells = <0>;
2495 port@0 {
2496 reg = <0>;
2514 reg = <0 0xfed00000 0 0x10000>;
2523 #size-cells = <0>;
2525 port@0 {
2527 #size-cells = <0>;
2529 reg = <0>;
2531 isp0csi40: endpoint@0 {
2532 reg = <0>;
2598 reg = <0 0xfed20000 0 0x10000>;
2607 #size-cells = <0>;
2609 port@0 {
2611 #size-cells = <0>;
2613 reg = <0>;
2682 reg = <0 0xfed30000 0 0x10000>;
2691 #size-cells = <0>;
2693 port@0 {
2695 #size-cells = <0>;
2697 reg = <0>;
2699 isp2csi42: endpoint@0 {
2700 reg = <0>;
2766 reg = <0 0xfed40000 0 0x10000>;
2775 #size-cells = <0>;
2777 port@0 {
2779 #size-cells = <0>;
2781 reg = <0>;
2849 reg = <0 0xfed80000 0 0x10000>;
2860 #size-cells = <0>;
2862 port@0 {
2863 reg = <0>;
2877 reg = <0 0xfed90000 0 0x10000>;
2888 #size-cells = <0>;
2890 port@0 {
2891 reg = <0>;
2905 reg = <0 0xfff00044 0 4>;
2913 thermal-sensors = <&tsc 0>;