Lines Matching +full:0 +full:xe66d8000
20 #clock-cells = <0>;
21 clock-frequency = <0>;
26 #size-cells = <0>;
28 a76_0: cpu@0 {
30 reg = <0>;
37 L3_CA76_0: cache-controller-0 {
47 #clock-cells = <0>;
49 clock-frequency = <0>;
54 #clock-cells = <0>;
56 clock-frequency = <0>;
67 #clock-cells = <0>;
68 clock-frequency = <0>;
81 reg = <0 0xe6020000 0 0x0c>;
91 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
92 <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
93 <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
94 <0 0xe6068000 0 0x16c>, <0 0xe6068800 0 0x16c>,
95 <0 0xe6069000 0 0x16c>, <0 0xe6069800 0 0x16c>;
101 reg = <0 0xe6058180 0 0x54>;
108 gpio-ranges = <&pfc 0 0 28>;
116 reg = <0 0xe6050180 0 0x54>;
123 gpio-ranges = <&pfc 0 32 31>;
131 reg = <0 0xe6050980 0 0x54>;
138 gpio-ranges = <&pfc 0 64 25>;
146 reg = <0 0xe6058980 0 0x54>;
153 gpio-ranges = <&pfc 0 96 17>;
161 reg = <0 0xe6060180 0 0x54>;
168 gpio-ranges = <&pfc 0 128 27>;
176 reg = <0 0xe6060980 0 0x54>;
183 gpio-ranges = <&pfc 0 160 21>;
191 reg = <0 0xe6068180 0 0x54>;
198 gpio-ranges = <&pfc 0 192 21>;
206 reg = <0 0xe6068980 0 0x54>;
213 gpio-ranges = <&pfc 0 224 21>;
221 reg = <0 0xe6069180 0 0x54>;
228 gpio-ranges = <&pfc 0 256 21>;
236 reg = <0 0xe6069980 0 0x54>;
243 gpio-ranges = <&pfc 0 288 21>;
251 reg = <0 0xe60f0000 0 0x1004>;
264 reg = <0 0xe6130000 0 0x1004>;
283 reg = <0 0xe6140000 0 0x1004>;
302 reg = <0 0xe6148000 0 0x1004>;
320 reg = <0 0xe6150000 0 0x4000>;
324 #power-domain-cells = <0>;
330 reg = <0 0xe6160000 0 0x4000>;
335 reg = <0 0xe6180000 0 0x4000>;
341 reg = <0 0xe6190000 0 0x200>,
342 <0 0xe6198000 0 0x200>,
343 <0 0xe61a0000 0 0x200>,
344 <0 0xe61a8000 0 0x200>,
345 <0 0xe61b0000 0 0x200>;
356 reg = <0 0xe61c0000 0 0x200>;
357 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
369 reg = <0 0xe61e0000 0 0x30>;
383 reg = <0 0xe6fc0000 0 0x30>;
398 reg = <0 0xe6fd0000 0 0x30>;
413 reg = <0 0xe6fe0000 0 0x30>;
428 reg = <0 0xffc00000 0 0x30>;
444 reg = <0 0xe6500000 0 0x40>;
449 dmas = <&dmac1 0x91>, <&dmac1 0x90>;
453 #size-cells = <0>;
460 reg = <0 0xe6508000 0 0x40>;
465 dmas = <&dmac1 0x93>, <&dmac1 0x92>;
469 #size-cells = <0>;
476 reg = <0 0xe6510000 0 0x40>;
481 dmas = <&dmac1 0x95>, <&dmac1 0x94>;
485 #size-cells = <0>;
492 reg = <0 0xe66d0000 0 0x40>;
497 dmas = <&dmac1 0x97>, <&dmac1 0x96>;
501 #size-cells = <0>;
508 reg = <0 0xe66d8000 0 0x40>;
513 dmas = <&dmac1 0x99>, <&dmac1 0x98>;
517 #size-cells = <0>;
524 reg = <0 0xe66e0000 0 0x40>;
529 dmas = <&dmac1 0x9b>, <&dmac1 0x9a>;
533 #size-cells = <0>;
540 reg = <0 0xe66e8000 0 0x40>;
545 dmas = <&dmac1 0x9d>, <&dmac1 0x9c>;
549 #size-cells = <0>;
556 reg = <0 0xe6540000 0 0x60>;
562 dmas = <&dmac1 0x31>, <&dmac1 0x30>;
572 reg = <0 0xe6550000 0 0x60>;
578 dmas = <&dmac1 0x33>, <&dmac1 0x32>;
588 reg = <0 0xe6560000 0 0x60>;
594 dmas = <&dmac1 0x35>, <&dmac1 0x34>;
604 reg = <0 0xe66a0000 0 0x60>;
610 dmas = <&dmac1 0x37>, <&dmac1 0x36>;
620 reg = <0 0xe6660000 0 0x8000>;
670 reg = <0 0xe6800000 0 0x1000>;
708 rx-internal-delay-ps = <0>;
709 tx-internal-delay-ps = <0>;
710 iommus = <&ipmmu_ds1 0>;
712 #size-cells = <0>;
719 reg = <0 0xe6810000 0 0x1000>;
757 rx-internal-delay-ps = <0>;
758 tx-internal-delay-ps = <0>;
761 #size-cells = <0>;
768 reg = <0 0xe6820000 0 0x1000>;
806 rx-internal-delay-ps = <0>;
807 tx-internal-delay-ps = <0>;
810 #size-cells = <0>;
817 reg = <0 0xe6830000 0 0x1000>;
855 rx-internal-delay-ps = <0>;
856 tx-internal-delay-ps = <0>;
859 #size-cells = <0>;
866 reg = <0 0xe6840000 0 0x1000>;
904 rx-internal-delay-ps = <0>;
905 tx-internal-delay-ps = <0>;
908 #size-cells = <0>;
915 reg = <0 0xe6850000 0 0x1000>;
953 rx-internal-delay-ps = <0>;
954 tx-internal-delay-ps = <0>;
957 #size-cells = <0>;
963 reg = <0 0xe6e30000 0 0x10>;
973 reg = <0 0xe6e31000 0 0x10>;
983 reg = <0 0xe6e32000 0 0x10>;
993 reg = <0 0xe6e33000 0 0x10>;
1003 reg = <0 0xe6e34000 0 0x10>;
1014 reg = <0 0xe6e60000 0 64>;
1020 dmas = <&dmac1 0x51>, <&dmac1 0x50>;
1030 reg = <0 0xe6e68000 0 64>;
1036 dmas = <&dmac1 0x53>, <&dmac1 0x52>;
1046 reg = <0 0xe6c50000 0 64>;
1052 dmas = <&dmac1 0x57>, <&dmac1 0x56>;
1062 reg = <0 0xe6c40000 0 64>;
1068 dmas = <&dmac1 0x59>, <&dmac1 0x58>;
1077 reg = <0 0xe6e80000 0 0x148>;
1089 reg = <0 0xe6e90000 0 0x0064>;
1094 dmas = <&dmac1 0x41>, <&dmac1 0x40>;
1097 #size-cells = <0>;
1104 reg = <0 0xe6ea0000 0 0x0064>;
1109 dmas = <&dmac1 0x43>, <&dmac1 0x42>;
1112 #size-cells = <0>;
1119 reg = <0 0xe6c00000 0 0x0064>;
1124 dmas = <&dmac1 0x45>, <&dmac1 0x44>;
1127 #size-cells = <0>;
1134 reg = <0 0xe6c10000 0 0x0064>;
1139 dmas = <&dmac1 0x47>, <&dmac1 0x46>;
1142 #size-cells = <0>;
1149 reg = <0 0xe6c20000 0 0x0064>;
1154 dmas = <&dmac1 0x49>, <&dmac1 0x48>;
1157 #size-cells = <0>;
1164 reg = <0 0xe6c28000 0 0x0064>;
1169 dmas = <&dmac1 0x4b>, <&dmac1 0x4a>;
1172 #size-cells = <0>;
1179 reg = <0 0xe6ef0000 0 0x1000>;
1184 renesas,id = <0>;
1189 #size-cells = <0>;
1193 #size-cells = <0>;
1197 vin00isp0: endpoint@0 {
1198 reg = <0>;
1208 reg = <0 0xe6ef1000 0 0x1000>;
1218 #size-cells = <0>;
1222 #size-cells = <0>;
1226 vin01isp0: endpoint@0 {
1227 reg = <0>;
1237 reg = <0 0xe6ef2000 0 0x1000>;
1247 #size-cells = <0>;
1251 #size-cells = <0>;
1255 vin02isp0: endpoint@0 {
1256 reg = <0>;
1266 reg = <0 0xe6ef3000 0 0x1000>;
1276 #size-cells = <0>;
1280 #size-cells = <0>;
1284 vin03isp0: endpoint@0 {
1285 reg = <0>;
1295 reg = <0 0xe6ef4000 0 0x1000>;
1305 #size-cells = <0>;
1309 #size-cells = <0>;
1313 vin04isp0: endpoint@0 {
1314 reg = <0>;
1324 reg = <0 0xe6ef5000 0 0x1000>;
1334 #size-cells = <0>;
1338 #size-cells = <0>;
1342 vin05isp0: endpoint@0 {
1343 reg = <0>;
1353 reg = <0 0xe6ef6000 0 0x1000>;
1363 #size-cells = <0>;
1367 #size-cells = <0>;
1371 vin06isp0: endpoint@0 {
1372 reg = <0>;
1382 reg = <0 0xe6ef7000 0 0x1000>;
1392 #size-cells = <0>;
1396 #size-cells = <0>;
1400 vin07isp0: endpoint@0 {
1401 reg = <0>;
1411 reg = <0 0xe6ef8000 0 0x1000>;
1421 #size-cells = <0>;
1425 #size-cells = <0>;
1440 reg = <0 0xe6ef9000 0 0x1000>;
1450 #size-cells = <0>;
1454 #size-cells = <0>;
1469 reg = <0 0xe6efa000 0 0x1000>;
1479 #size-cells = <0>;
1483 #size-cells = <0>;
1498 reg = <0 0xe6efb000 0 0x1000>;
1508 #size-cells = <0>;
1512 #size-cells = <0>;
1527 reg = <0 0xe6efc000 0 0x1000>;
1537 #size-cells = <0>;
1541 #size-cells = <0>;
1556 reg = <0 0xe6efd000 0 0x1000>;
1566 #size-cells = <0>;
1570 #size-cells = <0>;
1585 reg = <0 0xe6efe000 0 0x1000>;
1595 #size-cells = <0>;
1599 #size-cells = <0>;
1614 reg = <0 0xe6eff000 0 0x1000>;
1624 #size-cells = <0>;
1628 #size-cells = <0>;
1643 reg = <0 0xe6ed0000 0 0x1000>;
1653 #size-cells = <0>;
1657 #size-cells = <0>;
1672 reg = <0 0xe6ed1000 0 0x1000>;
1682 #size-cells = <0>;
1686 #size-cells = <0>;
1701 reg = <0 0xe6ed2000 0 0x1000>;
1711 #size-cells = <0>;
1715 #size-cells = <0>;
1730 reg = <0 0xe6ed3000 0 0x1000>;
1740 #size-cells = <0>;
1744 #size-cells = <0>;
1759 reg = <0 0xe6ed4000 0 0x1000>;
1769 #size-cells = <0>;
1773 #size-cells = <0>;
1788 reg = <0 0xe6ed5000 0 0x1000>;
1798 #size-cells = <0>;
1802 #size-cells = <0>;
1817 reg = <0 0xe6ed6000 0 0x1000>;
1827 #size-cells = <0>;
1831 #size-cells = <0>;
1846 reg = <0 0xe6ed7000 0 0x1000>;
1856 #size-cells = <0>;
1860 #size-cells = <0>;
1875 reg = <0 0xe6ed8000 0 0x1000>;
1885 #size-cells = <0>;
1889 #size-cells = <0>;
1904 reg = <0 0xe6ed9000 0 0x1000>;
1914 #size-cells = <0>;
1918 #size-cells = <0>;
1933 reg = <0 0xe6eda000 0 0x1000>;
1943 #size-cells = <0>;
1947 #size-cells = <0>;
1962 reg = <0 0xe6edb000 0 0x1000>;
1972 #size-cells = <0>;
1976 #size-cells = <0>;
1991 reg = <0 0xe6edc000 0 0x1000>;
2001 #size-cells = <0>;
2005 #size-cells = <0>;
2020 reg = <0 0xe6edd000 0 0x1000>;
2030 #size-cells = <0>;
2034 #size-cells = <0>;
2049 reg = <0 0xe6ede000 0 0x1000>;
2059 #size-cells = <0>;
2063 #size-cells = <0>;
2078 reg = <0 0xe6edf000 0 0x1000>;
2088 #size-cells = <0>;
2092 #size-cells = <0>;
2107 reg = <0 0xe7350000 0 0x1000>,
2108 <0 0xe7300000 0 0x10000>;
2137 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
2150 reg = <0 0xe7351000 0 0x1000>,
2151 <0 0xe7310000 0 0x10000>;
2179 reg = <0 0xee140000 0 0x2000>;
2193 reg = <0 0xee200000 0 0x200>,
2194 <0 0x08000000 0 0x04000000>,
2195 <0 0xee208000 0 0x100>;
2202 #size-cells = <0>;
2209 reg = <0 0xee480000 0 0x20000>;
2218 reg = <0 0xee4c0000 0 0x20000>;
2227 reg = <0 0xeed00000 0 0x20000>;
2236 reg = <0 0xeed40000 0 0x20000>;
2245 reg = <0 0xeed80000 0 0x20000>;
2254 reg = <0 0xeedc0000 0 0x20000>;
2263 reg = <0 0xeee80000 0 0x20000>;
2272 reg = <0 0xeeec0000 0 0x20000>;
2281 reg = <0 0xeee00000 0 0x20000>;
2290 reg = <0 0xeef00000 0 0x20000>;
2299 reg = <0 0xeef40000 0 0x20000>;
2308 reg = <0 0xeefc0000 0 0x20000>;
2318 #address-cells = <0>;
2320 reg = <0x0 0xf1000000 0 0x20000>,
2321 <0x0 0xf1060000 0 0x110000>;
2327 reg = <0 0xfea10000 0 0x200>;
2336 reg = <0 0xfea11000 0 0x200>;
2345 reg = <0 0xfea20000 0 0x5000>;
2356 reg = <0 0xfea28000 0 0x5000>;
2367 reg = <0 0xfeaa0000 0 0x10000>;
2376 #size-cells = <0>;
2378 port@0 {
2379 reg = <0>;
2393 reg = <0 0xfeab0000 0 0x10000>;
2402 #size-cells = <0>;
2404 port@0 {
2405 reg = <0>;
2419 reg = <0 0xfed60000 0 0x10000>;
2428 #size-cells = <0>;
2430 port@0 {
2431 reg = <0>;
2445 reg = <0 0xfed70000 0 0x10000>;
2454 #size-cells = <0>;
2456 port@0 {
2457 reg = <0>;
2471 reg = <0 0xfeb00000 0 0x40000>;
2475 clock-names = "du.0";
2478 reset-names = "du.0";
2479 renesas,vsps = <&vspd0 0>, <&vspd1 0>;
2485 #size-cells = <0>;
2487 port@0 {
2488 reg = <0>;
2506 reg = <0 0xfed00000 0 0x10000>;
2515 #size-cells = <0>;
2517 port@0 {
2519 #size-cells = <0>;
2521 reg = <0>;
2523 isp0csi40: endpoint@0 {
2524 reg = <0>;
2590 reg = <0 0xfed20000 0 0x10000>;
2599 #size-cells = <0>;
2601 port@0 {
2603 #size-cells = <0>;
2605 reg = <0>;
2674 reg = <0 0xfed30000 0 0x10000>;
2683 #size-cells = <0>;
2685 port@0 {
2687 #size-cells = <0>;
2689 reg = <0>;
2691 isp2csi42: endpoint@0 {
2692 reg = <0>;
2758 reg = <0 0xfed40000 0 0x10000>;
2767 #size-cells = <0>;
2769 port@0 {
2771 #size-cells = <0>;
2773 reg = <0>;
2841 reg = <0 0xfed80000 0 0x10000>;
2852 #size-cells = <0>;
2854 port@0 {
2855 reg = <0>;
2869 reg = <0 0xfed90000 0 0x10000>;
2880 #size-cells = <0>;
2882 port@0 {
2883 reg = <0>;
2897 reg = <0 0xfff00044 0 4>;
2905 thermal-sensors = <&tsc 0>;