Lines Matching +full:0 +full:xe6ef2000
22 #clock-cells = <0>;
23 clock-frequency = <0>;
28 #size-cells = <0>;
30 a53_0: cpu@0 {
33 reg = <0>;
80 #clock-cells = <0>;
82 clock-frequency = <0>;
87 #clock-cells = <0>;
89 clock-frequency = <0>;
95 #clock-cells = <0>;
96 clock-frequency = <0>;
116 #clock-cells = <0>;
117 clock-frequency = <0>;
131 reg = <0 0xe6020000 0 0x0c>;
142 reg = <0 0xe6050000 0 0x50>;
146 gpio-ranges = <&pfc 0 0 22>;
157 reg = <0 0xe6051000 0 0x50>;
161 gpio-ranges = <&pfc 0 32 28>;
172 reg = <0 0xe6052000 0 0x50>;
176 gpio-ranges = <&pfc 0 64 30>;
187 reg = <0 0xe6053000 0 0x50>;
191 gpio-ranges = <&pfc 0 96 17>;
202 reg = <0 0xe6054000 0 0x50>;
206 gpio-ranges = <&pfc 0 128 25>;
217 reg = <0 0xe6055000 0 0x50>;
221 gpio-ranges = <&pfc 0 160 15>;
231 reg = <0 0xe6060000 0 0x50c>;
237 reg = <0 0xe60f0000 0 0x1004>;
250 reg = <0 0xe6130000 0 0x1004>;
269 reg = <0 0xe6140000 0 0x1004>;
288 reg = <0 0xe6148000 0 0x1004>;
306 reg = <0 0xe6150000 0 0x1000>;
310 #power-domain-cells = <0>;
316 reg = <0 0xe6160000 0 0x200>;
321 reg = <0 0xe6180000 0 0x440>;
327 reg = <0 0xe6198000 0 0x100>,
328 <0 0xe61a0000 0 0x100>;
342 reg = <0 0xe61c0000 0 0x200>;
343 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
356 reg = <0 0xe61e0000 0 0x30>;
370 reg = <0 0xe6fc0000 0 0x30>;
385 reg = <0 0xe6fd0000 0 0x30>;
400 reg = <0 0xe6fe0000 0 0x30>;
415 reg = <0 0xffc00000 0 0x30>;
431 reg = <0 0xe6500000 0 0x40>;
436 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
437 <&dmac2 0x91>, <&dmac2 0x90>;
441 #size-cells = <0>;
448 reg = <0 0xe6508000 0 0x40>;
453 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
454 <&dmac2 0x93>, <&dmac2 0x92>;
458 #size-cells = <0>;
465 reg = <0 0xe6510000 0 0x40>;
470 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
471 <&dmac2 0x95>, <&dmac2 0x94>;
475 #size-cells = <0>;
482 reg = <0 0xe66d0000 0 0x40>;
489 #size-cells = <0>;
496 reg = <0 0xe66d8000 0 0x40>;
503 #size-cells = <0>;
510 reg = <0 0xe66e0000 0 0x40>;
515 dmas = <&dmac1 0x9b>, <&dmac1 0x9a>,
516 <&dmac2 0x9b>, <&dmac2 0x9a>;
520 #size-cells = <0>;
528 reg = <0 0xe6540000 0 0x60>;
534 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
535 <&dmac2 0x31>, <&dmac2 0x30>;
546 reg = <0 0xe6550000 0 0x60>;
552 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
553 <&dmac2 0x33>, <&dmac2 0x32>;
564 reg = <0 0xe6560000 0 0x60>;
570 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
571 <&dmac2 0x35>, <&dmac2 0x34>;
582 reg = <0 0xe66a0000 0 0x60>;
588 dmas = <&dmac1 0x37>, <&dmac1 0x36>,
589 <&dmac2 0x37>, <&dmac2 0x36>;
598 reg = <0 0xe65d0000 0 0x8000>;
599 #phy-cells = <0>;
609 reg = <0 0xe66c0000 0 0x8000>;
635 reg = <0 0xe6800000 0 0x800>;
673 rx-internal-delay-ps = <0>;
677 #size-cells = <0>;
683 reg = <0 0xe6e30000 0 0x10>;
693 reg = <0 0xe6e31000 0 0x10>;
703 reg = <0 0xe6e32000 0 0x10>;
713 reg = <0 0xe6e33000 0 0x10>;
723 reg = <0 0xe6e34000 0 0x10>;
735 reg = <0 0xe6e60000 0 0x40>;
741 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
742 <&dmac2 0x51>, <&dmac2 0x50>;
753 reg = <0 0xe6e68000 0 0x40>;
759 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
760 <&dmac2 0x53>, <&dmac2 0x52>;
771 reg = <0 0xe6c50000 0 0x40>;
777 dmas = <&dmac1 0x57>, <&dmac1 0x56>,
778 <&dmac2 0x57>, <&dmac2 0x56>;
789 reg = <0 0xe6c40000 0 0x40>;
795 dmas = <&dmac1 0x59>, <&dmac1 0x58>,
796 <&dmac2 0x59>, <&dmac2 0x58>;
805 reg = <0 0xe6e80000 0 0x148>;
817 reg = <0 0xe6e90000 0 0x64>;
823 #size-cells = <0>;
830 reg = <0 0xe6ea0000 0 0x0064>;
836 #size-cells = <0>;
843 reg = <0 0xe6c00000 0 0x0064>;
849 #size-cells = <0>;
856 reg = <0 0xe6c10000 0 0x0064>;
862 #size-cells = <0>;
868 reg = <0 0xe6ef0000 0 0x1000>;
873 renesas,id = <0>;
878 #size-cells = <0>;
882 #size-cells = <0>;
896 reg = <0 0xe6ef1000 0 0x1000>;
906 #size-cells = <0>;
910 #size-cells = <0>;
924 reg = <0 0xe6ef2000 0 0x1000>;
934 #size-cells = <0>;
938 #size-cells = <0>;
952 reg = <0 0xe6ef3000 0 0x1000>;
962 #size-cells = <0>;
966 #size-cells = <0>;
980 reg = <0 0xe6ef4000 0 0x1000>;
990 #size-cells = <0>;
994 #size-cells = <0>;
1008 reg = <0 0xe6ef5000 0 0x1000>;
1018 #size-cells = <0>;
1022 #size-cells = <0>;
1036 reg = <0 0xe6ef6000 0 0x1000>;
1046 #size-cells = <0>;
1050 #size-cells = <0>;
1064 reg = <0 0xe6ef7000 0 0x1000>;
1074 #size-cells = <0>;
1078 #size-cells = <0>;
1092 reg = <0 0xe6ef8000 0 0x1000>;
1103 reg = <0 0xe6ef9000 0 0x1000>;
1114 reg = <0 0xe6efa000 0 0x1000>;
1125 reg = <0 0xe6efb000 0 0x1000>;
1136 reg = <0 0xe6efc000 0 0x1000>;
1147 reg = <0 0xe6efd000 0 0x1000>;
1158 reg = <0 0xe6efe000 0 0x1000>;
1169 reg = <0 0xe6eff000 0 0x1000>;
1181 reg = <0 0xe7300000 0 0x10000>;
1210 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1223 reg = <0 0xe7310000 0 0x10000>;
1264 reg = <0 0xe7400000 0 0x1000>;
1271 #size-cells = <0>;
1277 reg = <0 0xe7740000 0 0x1000>;
1278 renesas,ipmmu-main = <&ipmmu_mm 0>;
1285 reg = <0 0xff8b0000 0 0x1000>;
1293 reg = <0 0xe67b0000 0 0x1000>;
1302 reg = <0 0xffc80000 0 0x1000>;
1310 reg = <0 0xfe990000 0 0x1000>;
1318 reg = <0 0xfebd0000 0 0x1000>;
1326 reg = <0 0xe7b00000 0 0x1000>;
1334 reg = <0 0xe7960000 0 0x1000>;
1343 reg = <0 0xee140000 0 0x2000>;
1357 reg = <0 0xee200000 0 0x200>,
1358 <0 0x08000000 0 0x4000000>,
1359 <0 0xee208000 0 0x100>;
1366 #size-cells = <0>;
1373 #address-cells = <0>;
1375 reg = <0x0 0xf1010000 0 0x1000>,
1376 <0x0 0xf1020000 0 0x20000>,
1377 <0x0 0xf1040000 0 0x20000>,
1378 <0x0 0xf1060000 0 0x20000>;
1390 reg = <0 0xfe000000 0 0x80000>;
1393 bus-range = <0x00 0xff>;
1395 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x0100000>,
1396 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000>,
1397 <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>,
1398 <0x42000000 0 0x38000000 0 0x38000000 0 0x8000000>;
1400 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
1405 interrupt-map-mask = <0 0 0 0>;
1406 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1413 iommu-map = <0 &ipmmu_vi0 5 1>;
1414 iommu-map-mask = <0>;
1420 reg = <0 0xfea20000 0 0x5000>;
1430 reg = <0 0xfea27000 0 0x200>;
1439 reg = <0 0xfeaa0000 0 0x10000>;
1448 #size-cells = <0>;
1450 port@0 {
1451 reg = <0>;
1456 #size-cells = <0>;
1460 csi40vin0: endpoint@0 {
1461 reg = <0>;
1482 reg = <0 0xfeab0000 0 0x10000>;
1491 #size-cells = <0>;
1493 port@0 {
1494 reg = <0>;
1499 #size-cells = <0>;
1503 csi41vin4: endpoint@0 {
1504 reg = <0>;
1525 reg = <0 0xfeb00000 0 0x80000>;
1528 clock-names = "du.0";
1531 reset-names = "du.0";
1532 renesas,vsps = <&vspd0 0>;
1538 #size-cells = <0>;
1540 port@0 {
1541 reg = <0>;
1555 reg = <0 0xfeb90000 0 0x14>;
1563 #size-cells = <0>;
1565 port@0 {
1566 reg = <0>;
1581 reg = <0 0xfff00044 0 4>;
1589 thermal-sensors = <&tsc 0>;