Lines Matching +full:0 +full:xe6053000
22 #clock-cells = <0>;
23 clock-frequency = <0>;
28 #size-cells = <0>;
30 a53_0: cpu@0 {
33 reg = <0>;
80 #clock-cells = <0>;
82 clock-frequency = <0>;
88 #clock-cells = <0>;
90 clock-frequency = <0>;
97 #clock-cells = <0>;
98 clock-frequency = <0>;
118 #clock-cells = <0>;
119 clock-frequency = <0>;
134 reg = <0 0xe6020000 0 0x0c>;
145 reg = <0 0xe6050000 0 0x50>;
149 gpio-ranges = <&pfc 0 0 22>;
160 reg = <0 0xe6051000 0 0x50>;
164 gpio-ranges = <&pfc 0 32 28>;
175 reg = <0 0xe6052000 0 0x50>;
179 gpio-ranges = <&pfc 0 64 30>;
190 reg = <0 0xe6053000 0 0x50>;
194 gpio-ranges = <&pfc 0 96 17>;
205 reg = <0 0xe6054000 0 0x50>;
209 gpio-ranges = <&pfc 0 128 25>;
220 reg = <0 0xe6055000 0 0x50>;
224 gpio-ranges = <&pfc 0 160 15>;
234 reg = <0 0xe6060000 0 0x50c>;
241 reg = <0 0xe60f0000 0 0x1004>;
254 reg = <0 0xe6130000 0 0x1004>;
273 reg = <0 0xe6140000 0 0x1004>;
292 reg = <0 0xe6148000 0 0x1004>;
310 reg = <0 0xe6150000 0 0x1000>;
314 #power-domain-cells = <0>;
321 reg = <0 0xe6160000 0 0x200>;
327 reg = <0 0xe6180000 0 0x440>;
333 reg = <0 0xe6198000 0 0x100>,
334 <0 0xe61a0000 0 0x100>;
348 reg = <0 0xe61c0000 0 0x200>;
349 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
362 reg = <0 0xe61e0000 0 0x30>;
376 reg = <0 0xe6fc0000 0 0x30>;
391 reg = <0 0xe6fd0000 0 0x30>;
406 reg = <0 0xe6fe0000 0 0x30>;
421 reg = <0 0xffc00000 0 0x30>;
437 reg = <0 0xe6500000 0 0x40>;
442 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
443 <&dmac2 0x91>, <&dmac2 0x90>;
447 #size-cells = <0>;
454 reg = <0 0xe6508000 0 0x40>;
459 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
460 <&dmac2 0x93>, <&dmac2 0x92>;
464 #size-cells = <0>;
471 reg = <0 0xe6510000 0 0x40>;
476 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
477 <&dmac2 0x95>, <&dmac2 0x94>;
481 #size-cells = <0>;
488 reg = <0 0xe66d0000 0 0x40>;
495 #size-cells = <0>;
502 reg = <0 0xe66d8000 0 0x40>;
509 #size-cells = <0>;
516 reg = <0 0xe66e0000 0 0x40>;
521 dmas = <&dmac1 0x9b>, <&dmac1 0x9a>,
522 <&dmac2 0x9b>, <&dmac2 0x9a>;
526 #size-cells = <0>;
534 reg = <0 0xe6540000 0 0x60>;
540 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
541 <&dmac2 0x31>, <&dmac2 0x30>;
552 reg = <0 0xe6550000 0 0x60>;
558 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
559 <&dmac2 0x33>, <&dmac2 0x32>;
570 reg = <0 0xe6560000 0 0x60>;
576 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
577 <&dmac2 0x35>, <&dmac2 0x34>;
588 reg = <0 0xe66a0000 0 0x60>;
594 dmas = <&dmac1 0x37>, <&dmac1 0x36>,
595 <&dmac2 0x37>, <&dmac2 0x36>;
604 reg = <0 0xe65d0000 0 0x8000>;
605 #phy-cells = <0>;
615 reg = <0 0xe66c0000 0 0x8000>;
641 reg = <0 0xe6800000 0 0x800>;
679 rx-internal-delay-ps = <0>;
683 #size-cells = <0>;
689 reg = <0 0xe6e30000 0 0x10>;
699 reg = <0 0xe6e31000 0 0x10>;
709 reg = <0 0xe6e32000 0 0x10>;
719 reg = <0 0xe6e33000 0 0x10>;
729 reg = <0 0xe6e34000 0 0x10>;
741 reg = <0 0xe6e60000 0 0x40>;
747 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
748 <&dmac2 0x51>, <&dmac2 0x50>;
759 reg = <0 0xe6e68000 0 0x40>;
765 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
766 <&dmac2 0x53>, <&dmac2 0x52>;
777 reg = <0 0xe6c50000 0 0x40>;
783 dmas = <&dmac1 0x57>, <&dmac1 0x56>,
784 <&dmac2 0x57>, <&dmac2 0x56>;
795 reg = <0 0xe6c40000 0 0x40>;
801 dmas = <&dmac1 0x59>, <&dmac1 0x58>,
802 <&dmac2 0x59>, <&dmac2 0x58>;
811 reg = <0 0xe6e80000 0 0x148>;
823 reg = <0 0xe6e90000 0 0x64>;
829 #size-cells = <0>;
836 reg = <0 0xe6ea0000 0 0x0064>;
842 #size-cells = <0>;
849 reg = <0 0xe6c00000 0 0x0064>;
855 #size-cells = <0>;
862 reg = <0 0xe6c10000 0 0x0064>;
868 #size-cells = <0>;
874 reg = <0 0xe6ef0000 0 0x1000>;
879 renesas,id = <0>;
884 #size-cells = <0>;
888 #size-cells = <0>;
902 reg = <0 0xe6ef1000 0 0x1000>;
912 #size-cells = <0>;
916 #size-cells = <0>;
930 reg = <0 0xe6ef2000 0 0x1000>;
940 #size-cells = <0>;
944 #size-cells = <0>;
958 reg = <0 0xe6ef3000 0 0x1000>;
968 #size-cells = <0>;
972 #size-cells = <0>;
986 reg = <0 0xe6ef4000 0 0x1000>;
996 #size-cells = <0>;
1000 #size-cells = <0>;
1014 reg = <0 0xe6ef5000 0 0x1000>;
1024 #size-cells = <0>;
1028 #size-cells = <0>;
1042 reg = <0 0xe6ef6000 0 0x1000>;
1052 #size-cells = <0>;
1056 #size-cells = <0>;
1070 reg = <0 0xe6ef7000 0 0x1000>;
1080 #size-cells = <0>;
1084 #size-cells = <0>;
1098 reg = <0 0xe6ef8000 0 0x1000>;
1109 reg = <0 0xe6ef9000 0 0x1000>;
1120 reg = <0 0xe6efa000 0 0x1000>;
1131 reg = <0 0xe6efb000 0 0x1000>;
1142 reg = <0 0xe6efc000 0 0x1000>;
1153 reg = <0 0xe6efd000 0 0x1000>;
1164 reg = <0 0xe6efe000 0 0x1000>;
1175 reg = <0 0xe6eff000 0 0x1000>;
1187 reg = <0 0xe7300000 0 0x10000>;
1216 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1229 reg = <0 0xe7310000 0 0x10000>;
1270 reg = <0 0xe7400000 0 0x1000>;
1277 #size-cells = <0>;
1283 reg = <0 0xe7740000 0 0x1000>;
1284 renesas,ipmmu-main = <&ipmmu_mm 0>;
1291 reg = <0 0xff8b0000 0 0x1000>;
1299 reg = <0 0xe67b0000 0 0x1000>;
1308 reg = <0 0xffc80000 0 0x1000>;
1316 reg = <0 0xfe990000 0 0x1000>;
1324 reg = <0 0xfebd0000 0 0x1000>;
1332 reg = <0 0xe7b00000 0 0x1000>;
1340 reg = <0 0xe7960000 0 0x1000>;
1349 reg = <0 0xee140000 0 0x2000>;
1363 reg = <0 0xee200000 0 0x200>,
1364 <0 0x08000000 0 0x4000000>,
1365 <0 0xee208000 0 0x100>;
1372 #size-cells = <0>;
1379 #address-cells = <0>;
1381 reg = <0x0 0xf1010000 0 0x1000>,
1382 <0x0 0xf1020000 0 0x20000>,
1383 <0x0 0xf1040000 0 0x20000>,
1384 <0x0 0xf1060000 0 0x20000>;
1396 reg = <0 0xfe000000 0 0x80000>;
1399 bus-range = <0x00 0xff>;
1401 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x0100000>,
1402 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000>,
1403 <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>,
1404 <0x42000000 0 0x38000000 0 0x38000000 0 0x8000000>;
1406 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
1411 interrupt-map-mask = <0 0 0 0>;
1412 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1419 iommu-map = <0 &ipmmu_vi0 5 1>;
1420 iommu-map-mask = <0>;
1426 reg = <0 0xfea20000 0 0x5000>;
1436 reg = <0 0xfea27000 0 0x200>;
1445 reg = <0 0xfeaa0000 0 0x10000>;
1454 #size-cells = <0>;
1456 port@0 {
1457 reg = <0>;
1462 #size-cells = <0>;
1466 csi40vin0: endpoint@0 {
1467 reg = <0>;
1488 reg = <0 0xfeab0000 0 0x10000>;
1497 #size-cells = <0>;
1499 port@0 {
1500 reg = <0>;
1505 #size-cells = <0>;
1509 csi41vin4: endpoint@0 {
1510 reg = <0>;
1531 reg = <0 0xfeb00000 0 0x80000>;
1534 clock-names = "du.0";
1537 reset-names = "du.0";
1538 renesas,vsps = <&vspd0 0>;
1544 #size-cells = <0>;
1546 port@0 {
1547 reg = <0>;
1561 reg = <0 0xfeb90000 0 0x14>;
1569 #size-cells = <0>;
1571 port@0 {
1572 reg = <0>;
1587 reg = <0 0xfff00044 0 4>;
1596 thermal-sensors = <&tsc 0>;