Lines Matching +full:- +full:resets
1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car V3H (R8A77980) SoC
9 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/power/r8a77980-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
19 /* External CAN clock - to be overridden by boards that provide it */
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <0>;
27 #address-cells = <1>;
28 #size-cells = <0>;
32 compatible = "arm,cortex-a53";
35 power-domains = <&sysc R8A77980_PD_CA53_CPU0>;
36 next-level-cache = <&L2_CA53>;
37 enable-method = "psci";
42 compatible = "arm,cortex-a53";
45 power-domains = <&sysc R8A77980_PD_CA53_CPU1>;
46 next-level-cache = <&L2_CA53>;
47 enable-method = "psci";
52 compatible = "arm,cortex-a53";
55 power-domains = <&sysc R8A77980_PD_CA53_CPU2>;
56 next-level-cache = <&L2_CA53>;
57 enable-method = "psci";
62 compatible = "arm,cortex-a53";
65 power-domains = <&sysc R8A77980_PD_CA53_CPU3>;
66 next-level-cache = <&L2_CA53>;
67 enable-method = "psci";
70 L2_CA53: cache-controller {
72 power-domains = <&sysc R8A77980_PD_CA53_SCU>;
73 cache-unified;
74 cache-level = <2>;
79 compatible = "fixed-clock";
80 #clock-cells = <0>;
82 clock-frequency = <0>;
86 compatible = "fixed-clock";
87 #clock-cells = <0>;
89 clock-frequency = <0>;
92 /* External PCIe clock - can be overridden by the board */
94 compatible = "fixed-clock";
95 #clock-cells = <0>;
96 clock-frequency = <0>;
100 compatible = "arm,cortex-a53-pmu";
101 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
105 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
109 compatible = "arm,psci-1.0", "arm,psci-0.2";
113 /* External SCIF clock - to be overridden by boards that provide it */
115 compatible = "fixed-clock";
116 #clock-cells = <0>;
117 clock-frequency = <0>;
121 compatible = "simple-bus";
122 interrupt-parent = <&gic>;
124 #address-cells = <2>;
125 #size-cells = <2>;
129 compatible = "renesas,r8a77980-wdt",
130 "renesas,rcar-gen3-wdt";
134 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
135 resets = <&cpg 402>;
140 compatible = "renesas,gpio-r8a77980",
141 "renesas,rcar-gen3-gpio";
144 #gpio-cells = <2>;
145 gpio-controller;
146 gpio-ranges = <&pfc 0 0 22>;
147 #interrupt-cells = <2>;
148 interrupt-controller;
150 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
151 resets = <&cpg 912>;
155 compatible = "renesas,gpio-r8a77980",
156 "renesas,rcar-gen3-gpio";
159 #gpio-cells = <2>;
160 gpio-controller;
161 gpio-ranges = <&pfc 0 32 28>;
162 #interrupt-cells = <2>;
163 interrupt-controller;
165 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
166 resets = <&cpg 911>;
170 compatible = "renesas,gpio-r8a77980",
171 "renesas,rcar-gen3-gpio";
174 #gpio-cells = <2>;
175 gpio-controller;
176 gpio-ranges = <&pfc 0 64 30>;
177 #interrupt-cells = <2>;
178 interrupt-controller;
180 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
181 resets = <&cpg 910>;
185 compatible = "renesas,gpio-r8a77980",
186 "renesas,rcar-gen3-gpio";
189 #gpio-cells = <2>;
190 gpio-controller;
191 gpio-ranges = <&pfc 0 96 17>;
192 #interrupt-cells = <2>;
193 interrupt-controller;
195 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
196 resets = <&cpg 909>;
200 compatible = "renesas,gpio-r8a77980",
201 "renesas,rcar-gen3-gpio";
204 #gpio-cells = <2>;
205 gpio-controller;
206 gpio-ranges = <&pfc 0 128 25>;
207 #interrupt-cells = <2>;
208 interrupt-controller;
210 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
211 resets = <&cpg 908>;
215 compatible = "renesas,gpio-r8a77980",
216 "renesas,rcar-gen3-gpio";
219 #gpio-cells = <2>;
220 gpio-controller;
221 gpio-ranges = <&pfc 0 160 15>;
222 #interrupt-cells = <2>;
223 interrupt-controller;
225 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
226 resets = <&cpg 907>;
230 compatible = "renesas,pfc-r8a77980";
235 compatible = "renesas,r8a77980-cmt0",
236 "renesas,rcar-gen3-cmt0";
241 clock-names = "fck";
242 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
243 resets = <&cpg 303>;
248 compatible = "renesas,r8a77980-cmt1",
249 "renesas,rcar-gen3-cmt1";
260 clock-names = "fck";
261 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
262 resets = <&cpg 302>;
267 compatible = "renesas,r8a77980-cmt1",
268 "renesas,rcar-gen3-cmt1";
279 clock-names = "fck";
280 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
281 resets = <&cpg 301>;
286 compatible = "renesas,r8a77980-cmt1",
287 "renesas,rcar-gen3-cmt1";
298 clock-names = "fck";
299 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
300 resets = <&cpg 300>;
304 cpg: clock-controller@e6150000 {
305 compatible = "renesas,r8a77980-cpg-mssr";
308 clock-names = "extal", "extalr";
309 #clock-cells = <2>;
310 #power-domain-cells = <0>;
311 #reset-cells = <1>;
314 rst: reset-controller@e6160000 {
315 compatible = "renesas,r8a77980-rst";
319 sysc: system-controller@e6180000 {
320 compatible = "renesas,r8a77980-sysc";
322 #power-domain-cells = <1>;
326 compatible = "renesas,r8a77980-thermal";
333 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
334 resets = <&cpg 522>;
335 #thermal-sensor-cells = <1>;
338 intc_ex: interrupt-controller@e61c0000 {
339 compatible = "renesas,intc-ex-r8a77980", "renesas,irqc";
340 #interrupt-cells = <2>;
341 interrupt-controller;
350 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
351 resets = <&cpg 407>;
355 compatible = "renesas,tmu-r8a77980", "renesas,tmu";
360 interrupt-names = "tuni0", "tuni1", "tuni2";
362 clock-names = "fck";
363 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
364 resets = <&cpg 125>;
369 compatible = "renesas,tmu-r8a77980", "renesas,tmu";
375 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
377 clock-names = "fck";
378 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
379 resets = <&cpg 124>;
384 compatible = "renesas,tmu-r8a77980", "renesas,tmu";
390 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
392 clock-names = "fck";
393 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
394 resets = <&cpg 123>;
399 compatible = "renesas,tmu-r8a77980", "renesas,tmu";
405 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
407 clock-names = "fck";
408 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
409 resets = <&cpg 122>;
414 compatible = "renesas,tmu-r8a77980", "renesas,tmu";
420 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
422 clock-names = "fck";
423 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
424 resets = <&cpg 121>;
429 compatible = "renesas,i2c-r8a77980",
430 "renesas,rcar-gen3-i2c";
434 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
435 resets = <&cpg 931>;
438 dma-names = "tx", "rx", "tx", "rx";
439 i2c-scl-internal-delay-ns = <6>;
440 #address-cells = <1>;
441 #size-cells = <0>;
446 compatible = "renesas,i2c-r8a77980",
447 "renesas,rcar-gen3-i2c";
451 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
452 resets = <&cpg 930>;
455 dma-names = "tx", "rx", "tx", "rx";
456 i2c-scl-internal-delay-ns = <6>;
457 #address-cells = <1>;
458 #size-cells = <0>;
463 compatible = "renesas,i2c-r8a77980",
464 "renesas,rcar-gen3-i2c";
468 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
469 resets = <&cpg 929>;
472 dma-names = "tx", "rx", "tx", "rx";
473 i2c-scl-internal-delay-ns = <6>;
474 #address-cells = <1>;
475 #size-cells = <0>;
480 compatible = "renesas,i2c-r8a77980",
481 "renesas,rcar-gen3-i2c";
485 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
486 resets = <&cpg 928>;
487 i2c-scl-internal-delay-ns = <6>;
488 #address-cells = <1>;
489 #size-cells = <0>;
494 compatible = "renesas,i2c-r8a77980",
495 "renesas,rcar-gen3-i2c";
499 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
500 resets = <&cpg 927>;
501 i2c-scl-internal-delay-ns = <6>;
502 #address-cells = <1>;
503 #size-cells = <0>;
508 compatible = "renesas,i2c-r8a77980",
509 "renesas,rcar-gen3-i2c";
513 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
514 resets = <&cpg 919>;
517 dma-names = "tx", "rx", "tx", "rx";
518 i2c-scl-internal-delay-ns = <6>;
519 #address-cells = <1>;
520 #size-cells = <0>;
525 compatible = "renesas,hscif-r8a77980",
526 "renesas,rcar-gen3-hscif",
533 clock-names = "fck", "brg_int", "scif_clk";
536 dma-names = "tx", "rx", "tx", "rx";
537 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
538 resets = <&cpg 520>;
543 compatible = "renesas,hscif-r8a77980",
544 "renesas,rcar-gen3-hscif",
551 clock-names = "fck", "brg_int", "scif_clk";
554 dma-names = "tx", "rx", "tx", "rx";
555 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
556 resets = <&cpg 519>;
561 compatible = "renesas,hscif-r8a77980",
562 "renesas,rcar-gen3-hscif",
569 clock-names = "fck", "brg_int", "scif_clk";
572 dma-names = "tx", "rx", "tx", "rx";
573 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
574 resets = <&cpg 518>;
579 compatible = "renesas,hscif-r8a77980",
580 "renesas,rcar-gen3-hscif",
587 clock-names = "fck", "brg_int", "scif_clk";
590 dma-names = "tx", "rx", "tx", "rx";
591 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
592 resets = <&cpg 517>;
596 pcie_phy: pcie-phy@e65d0000 {
597 compatible = "renesas,r8a77980-pcie-phy";
599 #phy-cells = <0>;
601 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
602 resets = <&cpg 319>;
607 compatible = "renesas,r8a77980-canfd",
608 "renesas,rcar-gen3-canfd";
612 interrupt-names = "ch_int", "g_int";
616 clock-names = "fck", "canfd", "can_clk";
617 assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>;
618 assigned-clock-rates = <40000000>;
619 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
620 resets = <&cpg 914>;
633 compatible = "renesas,etheravb-r8a77980",
634 "renesas,etheravb-rcar-gen3";
661 interrupt-names = "ch0", "ch1", "ch2", "ch3",
669 clock-names = "fck";
670 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
671 resets = <&cpg 812>;
672 phy-mode = "rgmii";
673 rx-internal-delay-ps = <0>;
674 tx-internal-delay-ps = <2000>;
676 #address-cells = <1>;
677 #size-cells = <0>;
682 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
684 #pwm-cells = <2>;
686 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
687 resets = <&cpg 523>;
692 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
694 #pwm-cells = <2>;
696 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
697 resets = <&cpg 523>;
702 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
704 #pwm-cells = <2>;
706 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
707 resets = <&cpg 523>;
712 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
714 #pwm-cells = <2>;
716 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
717 resets = <&cpg 523>;
722 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
724 #pwm-cells = <2>;
726 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
727 resets = <&cpg 523>;
732 compatible = "renesas,scif-r8a77980",
733 "renesas,rcar-gen3-scif",
740 clock-names = "fck", "brg_int", "scif_clk";
743 dma-names = "tx", "rx", "tx", "rx";
744 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
745 resets = <&cpg 207>;
750 compatible = "renesas,scif-r8a77980",
751 "renesas,rcar-gen3-scif",
758 clock-names = "fck", "brg_int", "scif_clk";
761 dma-names = "tx", "rx", "tx", "rx";
762 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
763 resets = <&cpg 206>;
768 compatible = "renesas,scif-r8a77980",
769 "renesas,rcar-gen3-scif",
776 clock-names = "fck", "brg_int", "scif_clk";
779 dma-names = "tx", "rx", "tx", "rx";
780 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
781 resets = <&cpg 204>;
786 compatible = "renesas,scif-r8a77980",
787 "renesas,rcar-gen3-scif",
794 clock-names = "fck", "brg_int", "scif_clk";
797 dma-names = "tx", "rx", "tx", "rx";
798 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
799 resets = <&cpg 203>;
804 compatible = "renesas,tpu-r8a77980", "renesas,tpu";
808 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
809 resets = <&cpg 304>;
810 #pwm-cells = <3>;
815 compatible = "renesas,msiof-r8a77980",
816 "renesas,rcar-gen3-msiof";
820 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
821 resets = <&cpg 211>;
822 #address-cells = <1>;
823 #size-cells = <0>;
828 compatible = "renesas,msiof-r8a77980",
829 "renesas,rcar-gen3-msiof";
833 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
834 resets = <&cpg 210>;
835 #address-cells = <1>;
836 #size-cells = <0>;
841 compatible = "renesas,msiof-r8a77980",
842 "renesas,rcar-gen3-msiof";
846 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
847 resets = <&cpg 209>;
848 #address-cells = <1>;
849 #size-cells = <0>;
854 compatible = "renesas,msiof-r8a77980",
855 "renesas,rcar-gen3-msiof";
859 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
860 resets = <&cpg 208>;
861 #address-cells = <1>;
862 #size-cells = <0>;
867 compatible = "renesas,vin-r8a77980";
871 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
872 resets = <&cpg 811>;
877 #address-cells = <1>;
878 #size-cells = <0>;
881 #address-cells = <1>;
882 #size-cells = <0>;
888 remote-endpoint = <&csi40vin0>;
895 compatible = "renesas,vin-r8a77980";
899 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
902 resets = <&cpg 810>;
905 #address-cells = <1>;
906 #size-cells = <0>;
909 #address-cells = <1>;
910 #size-cells = <0>;
916 remote-endpoint = <&csi40vin1>;
923 compatible = "renesas,vin-r8a77980";
927 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
928 resets = <&cpg 809>;
933 #address-cells = <1>;
934 #size-cells = <0>;
937 #address-cells = <1>;
938 #size-cells = <0>;
944 remote-endpoint = <&csi40vin2>;
951 compatible = "renesas,vin-r8a77980";
955 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
956 resets = <&cpg 808>;
961 #address-cells = <1>;
962 #size-cells = <0>;
965 #address-cells = <1>;
966 #size-cells = <0>;
972 remote-endpoint = <&csi40vin3>;
979 compatible = "renesas,vin-r8a77980";
983 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
984 resets = <&cpg 807>;
989 #address-cells = <1>;
990 #size-cells = <0>;
993 #address-cells = <1>;
994 #size-cells = <0>;
1000 remote-endpoint = <&csi41vin4>;
1007 compatible = "renesas,vin-r8a77980";
1011 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1012 resets = <&cpg 806>;
1017 #address-cells = <1>;
1018 #size-cells = <0>;
1021 #address-cells = <1>;
1022 #size-cells = <0>;
1028 remote-endpoint = <&csi41vin5>;
1035 compatible = "renesas,vin-r8a77980";
1039 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1040 resets = <&cpg 805>;
1045 #address-cells = <1>;
1046 #size-cells = <0>;
1049 #address-cells = <1>;
1050 #size-cells = <0>;
1056 remote-endpoint = <&csi41vin6>;
1063 compatible = "renesas,vin-r8a77980";
1067 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1068 resets = <&cpg 804>;
1073 #address-cells = <1>;
1074 #size-cells = <0>;
1077 #address-cells = <1>;
1078 #size-cells = <0>;
1084 remote-endpoint = <&csi41vin7>;
1091 compatible = "renesas,vin-r8a77980";
1095 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1096 resets = <&cpg 628>;
1102 compatible = "renesas,vin-r8a77980";
1106 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1107 resets = <&cpg 627>;
1113 compatible = "renesas,vin-r8a77980";
1117 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1118 resets = <&cpg 625>;
1124 compatible = "renesas,vin-r8a77980";
1128 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1129 resets = <&cpg 618>;
1135 compatible = "renesas,vin-r8a77980";
1139 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1140 resets = <&cpg 612>;
1146 compatible = "renesas,vin-r8a77980";
1150 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1151 resets = <&cpg 608>;
1157 compatible = "renesas,vin-r8a77980";
1161 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1162 resets = <&cpg 605>;
1168 compatible = "renesas,vin-r8a77980";
1172 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1173 resets = <&cpg 604>;
1178 dmac1: dma-controller@e7300000 {
1179 compatible = "renesas,dmac-r8a77980",
1180 "renesas,rcar-dmac";
1199 interrupt-names = "error",
1205 clock-names = "fck";
1206 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1207 resets = <&cpg 218>;
1208 #dma-cells = <1>;
1209 dma-channels = <16>;
1220 dmac2: dma-controller@e7310000 {
1221 compatible = "renesas,dmac-r8a77980",
1222 "renesas,rcar-dmac";
1241 interrupt-names = "error",
1247 clock-names = "fck";
1248 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1249 resets = <&cpg 217>;
1250 #dma-cells = <1>;
1251 dma-channels = <16>;
1263 compatible = "renesas,gether-r8a77980";
1267 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1268 resets = <&cpg 813>;
1270 #address-cells = <1>;
1271 #size-cells = <0>;
1276 compatible = "renesas,ipmmu-r8a77980";
1278 renesas,ipmmu-main = <&ipmmu_mm 0>;
1279 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1280 #iommu-cells = <1>;
1284 compatible = "renesas,ipmmu-r8a77980";
1286 renesas,ipmmu-main = <&ipmmu_mm 3>;
1287 power-domains = <&sysc R8A77980_PD_A3IR>;
1288 #iommu-cells = <1>;
1292 compatible = "renesas,ipmmu-r8a77980";
1296 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1297 #iommu-cells = <1>;
1301 compatible = "renesas,ipmmu-r8a77980";
1303 renesas,ipmmu-main = <&ipmmu_mm 10>;
1304 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1305 #iommu-cells = <1>;
1309 compatible = "renesas,ipmmu-r8a77980";
1311 renesas,ipmmu-main = <&ipmmu_mm 12>;
1312 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1313 #iommu-cells = <1>;
1317 compatible = "renesas,ipmmu-r8a77980";
1319 renesas,ipmmu-main = <&ipmmu_mm 14>;
1320 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1321 #iommu-cells = <1>;
1325 compatible = "renesas,ipmmu-r8a77980";
1327 renesas,ipmmu-main = <&ipmmu_mm 4>;
1328 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1329 #iommu-cells = <1>;
1333 compatible = "renesas,ipmmu-r8a77980";
1335 renesas,ipmmu-main = <&ipmmu_mm 11>;
1336 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1337 #iommu-cells = <1>;
1341 compatible = "renesas,sdhi-r8a77980",
1342 "renesas,rcar-gen3-sdhi";
1346 clock-names = "core", "clkh";
1347 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1348 resets = <&cpg 314>;
1349 max-frequency = <200000000>;
1355 compatible = "renesas,r8a77980-rpc-if",
1356 "renesas,rcar-gen3-rpc-if";
1360 reg-names = "regs", "dirmap", "wbuf";
1363 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1364 resets = <&cpg 917>;
1365 #address-cells = <1>;
1366 #size-cells = <0>;
1370 gic: interrupt-controller@f1010000 {
1371 compatible = "arm,gic-400";
1372 #interrupt-cells = <3>;
1373 #address-cells = <0>;
1374 interrupt-controller;
1382 clock-names = "clk";
1383 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1384 resets = <&cpg 408>;
1388 compatible = "renesas,pcie-r8a77980",
1389 "renesas,pcie-rcar-gen3";
1391 #address-cells = <3>;
1392 #size-cells = <2>;
1393 bus-range = <0x00 0xff>;
1400 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
1404 #interrupt-cells = <1>;
1405 interrupt-map-mask = <0 0 0 0>;
1406 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1408 clock-names = "pcie", "pcie_bus";
1409 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1410 resets = <&cpg 319>;
1412 phy-names = "pcie";
1413 iommu-map = <0 &ipmmu_vi0 5 1>;
1414 iommu-map-mask = <0>;
1423 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1424 resets = <&cpg 623>;
1432 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1433 resets = <&cpg 603>;
1438 compatible = "renesas,r8a77980-csi2";
1442 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1443 resets = <&cpg 716>;
1447 #address-cells = <1>;
1448 #size-cells = <0>;
1455 #address-cells = <1>;
1456 #size-cells = <0>;
1462 remote-endpoint = <&vin0csi40>;
1466 remote-endpoint = <&vin1csi40>;
1470 remote-endpoint = <&vin2csi40>;
1474 remote-endpoint = <&vin3csi40>;
1481 compatible = "renesas,r8a77980-csi2";
1485 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1486 resets = <&cpg 715>;
1490 #address-cells = <1>;
1491 #size-cells = <0>;
1498 #address-cells = <1>;
1499 #size-cells = <0>;
1505 remote-endpoint = <&vin4csi41>;
1509 remote-endpoint = <&vin5csi41>;
1513 remote-endpoint = <&vin6csi41>;
1517 remote-endpoint = <&vin7csi41>;
1524 compatible = "renesas,du-r8a77980";
1528 clock-names = "du.0";
1529 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1530 resets = <&cpg 724>;
1531 reset-names = "du.0";
1537 #address-cells = <1>;
1538 #size-cells = <0>;
1547 remote-endpoint = <&lvds0_in>;
1553 lvds0: lvds-encoder@feb90000 {
1554 compatible = "renesas,r8a77980-lvds";
1557 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1558 resets = <&cpg 727>;
1562 #address-cells = <1>;
1563 #size-cells = <0>;
1568 remote-endpoint =
1585 thermal-zones {
1586 sensor1_thermal: sensor1-thermal {
1587 polling-delay-passive = <250>;
1588 polling-delay = <1000>;
1589 thermal-sensors = <&tsc 0>;
1592 sensor1-passive {
1597 sensor1-critical {
1605 sensor2_thermal: sensor2-thermal {
1606 polling-delay-passive = <250>;
1607 polling-delay = <1000>;
1608 thermal-sensors = <&tsc 1>;
1611 sensor2-passive {
1616 sensor2-critical {
1626 compatible = "arm,armv8-timer";
1627 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
1635 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";