Lines Matching +full:0 +full:xfeb90000
22 #clock-cells = <0>;
23 clock-frequency = <0>;
28 #size-cells = <0>;
30 a53_0: cpu@0 {
33 reg = <0>;
60 #clock-cells = <0>;
62 clock-frequency = <0>;
68 #clock-cells = <0>;
70 clock-frequency = <0>;
89 #clock-cells = <0>;
90 clock-frequency = <0>;
105 reg = <0 0xe6020000 0 0x0c>;
116 reg = <0 0xe6050000 0 0x50>;
120 gpio-ranges = <&pfc 0 0 22>;
131 reg = <0 0xe6051000 0 0x50>;
135 gpio-ranges = <&pfc 0 32 28>;
146 reg = <0 0xe6052000 0 0x50>;
150 gpio-ranges = <&pfc 0 64 17>;
161 reg = <0 0xe6053000 0 0x50>;
165 gpio-ranges = <&pfc 0 96 17>;
176 reg = <0 0xe6054000 0 0x50>;
180 gpio-ranges = <&pfc 0 128 6>;
191 reg = <0 0xe6055000 0 0x50>;
195 gpio-ranges = <&pfc 0 160 15>;
205 reg = <0 0xe6060000 0 0x504>;
212 reg = <0 0xe60f0000 0 0x1004>;
225 reg = <0 0xe6130000 0 0x1004>;
244 reg = <0 0xe6140000 0 0x1004>;
263 reg = <0 0xe6148000 0 0x1004>;
281 reg = <0 0xe6150000 0 0x1000>;
285 #power-domain-cells = <0>;
292 reg = <0 0xe6160000 0 0x200>;
298 reg = <0 0xe6180000 0 0x440>;
304 reg = <0 0xe6190000 0 0x10>,
305 <0 0xe6190100 0 0x120>;
312 #thermal-sensor-cells = <0>;
319 reg = <0 0xe61c0000 0 0x200>;
320 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
333 reg = <0 0xe61e0000 0 0x30>;
347 reg = <0 0xe6fc0000 0 0x30>;
362 reg = <0 0xe6fd0000 0 0x30>;
377 reg = <0 0xe6fe0000 0 0x30>;
391 reg = <0 0xffc00000 0 0x30>;
406 reg = <0 0xe6500000 0 0x40>;
411 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
412 <&dmac2 0x91>, <&dmac2 0x90>;
416 #size-cells = <0>;
423 reg = <0 0xe6508000 0 0x40>;
428 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
429 <&dmac2 0x93>, <&dmac2 0x92>;
433 #size-cells = <0>;
440 reg = <0 0xe6510000 0 0x40>;
445 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
446 <&dmac2 0x95>, <&dmac2 0x94>;
450 #size-cells = <0>;
457 reg = <0 0xe66d0000 0 0x40>;
462 dmas = <&dmac1 0x97>, <&dmac1 0x96>,
463 <&dmac2 0x97>, <&dmac2 0x96>;
467 #size-cells = <0>;
474 reg = <0 0xe66d8000 0 0x40>;
479 dmas = <&dmac1 0x99>, <&dmac1 0x98>,
480 <&dmac2 0x99>, <&dmac2 0x98>;
484 #size-cells = <0>;
492 reg = <0 0xe6540000 0 96>;
498 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
499 <&dmac2 0x31>, <&dmac2 0x30>;
510 reg = <0 0xe6550000 0 96>;
516 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
517 <&dmac2 0x33>, <&dmac2 0x32>;
528 reg = <0 0xe6560000 0 96>;
534 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
535 <&dmac2 0x35>, <&dmac2 0x34>;
545 reg = <0 0xe66a0000 0 96>;
551 dmas = <&dmac1 0x37>, <&dmac1 0x36>,
552 <&dmac2 0x37>, <&dmac2 0x36>;
562 reg = <0 0xe66c0000 0 0x8000>;
588 reg = <0 0xe6800000 0 0x800>;
626 rx-internal-delay-ps = <0>;
627 tx-internal-delay-ps = <0>;
630 #size-cells = <0>;
636 reg = <0 0xe6e30000 0 8>;
646 reg = <0 0xe6e31000 0 8>;
656 reg = <0 0xe6e32000 0 8>;
666 reg = <0 0xe6e33000 0 8>;
676 reg = <0 0xe6e34000 0 8>;
688 reg = <0 0xe6e60000 0 64>;
694 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
695 <&dmac2 0x51>, <&dmac2 0x50>;
706 reg = <0 0xe6e68000 0 64>;
712 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
713 <&dmac2 0x53>, <&dmac2 0x52>;
724 reg = <0 0xe6c50000 0 64>;
730 dmas = <&dmac1 0x57>, <&dmac1 0x56>,
731 <&dmac2 0x57>, <&dmac2 0x56>;
741 reg = <0 0xe6c40000 0 64>;
747 dmas = <&dmac1 0x59>, <&dmac1 0x58>,
748 <&dmac2 0x59>, <&dmac2 0x58>;
757 reg = <0 0xe6e80000 0 0x148>;
769 reg = <0 0xe6e90000 0 0x64>;
774 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
775 <&dmac2 0x41>, <&dmac2 0x40>;
778 #size-cells = <0>;
785 reg = <0 0xe6ea0000 0 0x0064>;
790 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
791 <&dmac2 0x43>, <&dmac2 0x42>;
794 #size-cells = <0>;
801 reg = <0 0xe6c00000 0 0x0064>;
806 dmas = <&dmac1 0x45>, <&dmac1 0x44>,
807 <&dmac2 0x45>, <&dmac2 0x44>;
810 #size-cells = <0>;
817 reg = <0 0xe6c10000 0 0x0064>;
822 dmas = <&dmac1 0x47>, <&dmac1 0x46>,
823 <&dmac2 0x47>, <&dmac2 0x46>;
826 #size-cells = <0>;
832 reg = <0 0xe6ef0000 0 0x1000>;
837 renesas,id = <0>;
842 #size-cells = <0>;
846 #size-cells = <0>;
860 reg = <0 0xe6ef1000 0 0x1000>;
870 #size-cells = <0>;
874 #size-cells = <0>;
888 reg = <0 0xe6ef2000 0 0x1000>;
898 #size-cells = <0>;
902 #size-cells = <0>;
916 reg = <0 0xe6ef3000 0 0x1000>;
926 #size-cells = <0>;
930 #size-cells = <0>;
945 reg = <0 0xe7300000 0 0x10000>;
964 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
973 reg = <0 0xe7310000 0 0x10000>;
1000 reg = <0 0xe7740000 0 0x1000>;
1001 renesas,ipmmu-main = <&ipmmu_mm 0>;
1008 reg = <0 0xff8b0000 0 0x1000>;
1016 reg = <0 0xe67b0000 0 0x1000>;
1025 reg = <0 0xffc80000 0 0x1000>;
1033 reg = <0 0xfebd0000 0 0x1000>;
1042 reg = <0 0xee140000 0 0x2000>;
1055 reg = <0 0xee200000 0 0x200>,
1056 <0 0x08000000 0 0x4000000>,
1057 <0 0xee208000 0 0x100>;
1064 #size-cells = <0>;
1071 #address-cells = <0>;
1073 reg = <0 0xf1010000 0 0x1000>,
1074 <0 0xf1020000 0 0x20000>,
1075 <0 0xf1040000 0 0x20000>,
1076 <0 0xf1060000 0 0x20000>;
1087 reg = <0 0xfea20000 0 0x5000>;
1097 reg = <0 0xfea27000 0 0x200>;
1106 reg = <0 0xfeaa0000 0 0x10000>;
1115 #size-cells = <0>;
1117 port@0 {
1118 reg = <0>;
1123 #size-cells = <0>;
1127 csi40vin0: endpoint@0 {
1128 reg = <0>;
1149 reg = <0 0xfeb00000 0 0x80000>;
1152 clock-names = "du.0";
1155 reset-names = "du.0";
1156 renesas,vsps = <&vspd0 0>;
1162 #size-cells = <0>;
1164 port@0 {
1165 reg = <0>;
1179 reg = <0 0xfeb90000 0 0x14>;
1187 #size-cells = <0>;
1189 port@0 {
1190 reg = <0>;
1204 reg = <0 0xfff00044 0 4>;