Lines Matching +full:0 +full:xe6160000
22 #clock-cells = <0>;
23 clock-frequency = <0>;
28 #size-cells = <0>;
30 a53_0: cpu@0 {
33 reg = <0>;
60 #clock-cells = <0>;
62 clock-frequency = <0>;
67 #clock-cells = <0>;
69 clock-frequency = <0>;
87 #clock-cells = <0>;
88 clock-frequency = <0>;
102 reg = <0 0xe6020000 0 0x0c>;
113 reg = <0 0xe6050000 0 0x50>;
117 gpio-ranges = <&pfc 0 0 22>;
128 reg = <0 0xe6051000 0 0x50>;
132 gpio-ranges = <&pfc 0 32 28>;
143 reg = <0 0xe6052000 0 0x50>;
147 gpio-ranges = <&pfc 0 64 17>;
158 reg = <0 0xe6053000 0 0x50>;
162 gpio-ranges = <&pfc 0 96 17>;
173 reg = <0 0xe6054000 0 0x50>;
177 gpio-ranges = <&pfc 0 128 6>;
188 reg = <0 0xe6055000 0 0x50>;
192 gpio-ranges = <&pfc 0 160 15>;
202 reg = <0 0xe6060000 0 0x504>;
208 reg = <0 0xe60f0000 0 0x1004>;
221 reg = <0 0xe6130000 0 0x1004>;
240 reg = <0 0xe6140000 0 0x1004>;
259 reg = <0 0xe6148000 0 0x1004>;
277 reg = <0 0xe6150000 0 0x1000>;
281 #power-domain-cells = <0>;
287 reg = <0 0xe6160000 0 0x200>;
292 reg = <0 0xe6180000 0 0x440>;
298 reg = <0 0xe6190000 0 0x10>,
299 <0 0xe6190100 0 0x120>;
306 #thermal-sensor-cells = <0>;
313 reg = <0 0xe61c0000 0 0x200>;
314 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
327 reg = <0 0xe61e0000 0 0x30>;
341 reg = <0 0xe6fc0000 0 0x30>;
356 reg = <0 0xe6fd0000 0 0x30>;
371 reg = <0 0xe6fe0000 0 0x30>;
385 reg = <0 0xffc00000 0 0x30>;
400 reg = <0 0xe6500000 0 0x40>;
405 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
406 <&dmac2 0x91>, <&dmac2 0x90>;
410 #size-cells = <0>;
417 reg = <0 0xe6508000 0 0x40>;
422 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
423 <&dmac2 0x93>, <&dmac2 0x92>;
427 #size-cells = <0>;
434 reg = <0 0xe6510000 0 0x40>;
439 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
440 <&dmac2 0x95>, <&dmac2 0x94>;
444 #size-cells = <0>;
451 reg = <0 0xe66d0000 0 0x40>;
456 dmas = <&dmac1 0x97>, <&dmac1 0x96>,
457 <&dmac2 0x97>, <&dmac2 0x96>;
461 #size-cells = <0>;
468 reg = <0 0xe66d8000 0 0x40>;
473 dmas = <&dmac1 0x99>, <&dmac1 0x98>,
474 <&dmac2 0x99>, <&dmac2 0x98>;
478 #size-cells = <0>;
486 reg = <0 0xe6540000 0 96>;
492 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
493 <&dmac2 0x31>, <&dmac2 0x30>;
504 reg = <0 0xe6550000 0 96>;
510 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
511 <&dmac2 0x33>, <&dmac2 0x32>;
522 reg = <0 0xe6560000 0 96>;
528 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
529 <&dmac2 0x35>, <&dmac2 0x34>;
539 reg = <0 0xe66a0000 0 96>;
545 dmas = <&dmac1 0x37>, <&dmac1 0x36>,
546 <&dmac2 0x37>, <&dmac2 0x36>;
556 reg = <0 0xe66c0000 0 0x8000>;
582 reg = <0 0xe6800000 0 0x800>;
620 rx-internal-delay-ps = <0>;
621 tx-internal-delay-ps = <0>;
624 #size-cells = <0>;
630 reg = <0 0xe6e30000 0 8>;
640 reg = <0 0xe6e31000 0 8>;
650 reg = <0 0xe6e32000 0 8>;
660 reg = <0 0xe6e33000 0 8>;
670 reg = <0 0xe6e34000 0 8>;
682 reg = <0 0xe6e60000 0 64>;
688 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
689 <&dmac2 0x51>, <&dmac2 0x50>;
700 reg = <0 0xe6e68000 0 64>;
706 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
707 <&dmac2 0x53>, <&dmac2 0x52>;
718 reg = <0 0xe6c50000 0 64>;
724 dmas = <&dmac1 0x57>, <&dmac1 0x56>,
725 <&dmac2 0x57>, <&dmac2 0x56>;
735 reg = <0 0xe6c40000 0 64>;
741 dmas = <&dmac1 0x59>, <&dmac1 0x58>,
742 <&dmac2 0x59>, <&dmac2 0x58>;
751 reg = <0 0xe6e80000 0 0x148>;
763 reg = <0 0xe6e90000 0 0x64>;
768 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
769 <&dmac2 0x41>, <&dmac2 0x40>;
772 #size-cells = <0>;
779 reg = <0 0xe6ea0000 0 0x0064>;
784 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
785 <&dmac2 0x43>, <&dmac2 0x42>;
788 #size-cells = <0>;
795 reg = <0 0xe6c00000 0 0x0064>;
800 dmas = <&dmac1 0x45>, <&dmac1 0x44>,
801 <&dmac2 0x45>, <&dmac2 0x44>;
804 #size-cells = <0>;
811 reg = <0 0xe6c10000 0 0x0064>;
816 dmas = <&dmac1 0x47>, <&dmac1 0x46>,
817 <&dmac2 0x47>, <&dmac2 0x46>;
820 #size-cells = <0>;
826 reg = <0 0xe6ef0000 0 0x1000>;
831 renesas,id = <0>;
836 #size-cells = <0>;
840 #size-cells = <0>;
854 reg = <0 0xe6ef1000 0 0x1000>;
864 #size-cells = <0>;
868 #size-cells = <0>;
882 reg = <0 0xe6ef2000 0 0x1000>;
892 #size-cells = <0>;
896 #size-cells = <0>;
910 reg = <0 0xe6ef3000 0 0x1000>;
920 #size-cells = <0>;
924 #size-cells = <0>;
939 reg = <0 0xe7300000 0 0x10000>;
958 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
967 reg = <0 0xe7310000 0 0x10000>;
994 reg = <0 0xe7740000 0 0x1000>;
995 renesas,ipmmu-main = <&ipmmu_mm 0>;
1002 reg = <0 0xff8b0000 0 0x1000>;
1010 reg = <0 0xe67b0000 0 0x1000>;
1019 reg = <0 0xffc80000 0 0x1000>;
1027 reg = <0 0xfebd0000 0 0x1000>;
1036 reg = <0 0xee140000 0 0x2000>;
1049 reg = <0 0xee200000 0 0x200>,
1050 <0 0x08000000 0 0x4000000>,
1051 <0 0xee208000 0 0x100>;
1058 #size-cells = <0>;
1065 #address-cells = <0>;
1067 reg = <0 0xf1010000 0 0x1000>,
1068 <0 0xf1020000 0 0x20000>,
1069 <0 0xf1040000 0 0x20000>,
1070 <0 0xf1060000 0 0x20000>;
1081 reg = <0 0xfea20000 0 0x5000>;
1091 reg = <0 0xfea27000 0 0x200>;
1100 reg = <0 0xfeaa0000 0 0x10000>;
1109 #size-cells = <0>;
1111 port@0 {
1112 reg = <0>;
1117 #size-cells = <0>;
1121 csi40vin0: endpoint@0 {
1122 reg = <0>;
1143 reg = <0 0xfeb00000 0 0x80000>;
1146 clock-names = "du.0";
1149 reset-names = "du.0";
1150 renesas,vsps = <&vspd0 0>;
1156 #size-cells = <0>;
1158 port@0 {
1159 reg = <0>;
1173 reg = <0 0xfeb90000 0 0x14>;
1181 #size-cells = <0>;
1183 port@0 {
1184 reg = <0>;
1198 reg = <0 0xfff00044 0 4>;