Lines Matching +full:0 +full:xe6ef2000
23 * The external audio clocks are configured as 0 Hz fixed frequency
29 #clock-cells = <0>;
30 clock-frequency = <0>;
35 #clock-cells = <0>;
36 clock-frequency = <0>;
41 #clock-cells = <0>;
42 clock-frequency = <0>;
48 #clock-cells = <0>;
49 clock-frequency = <0>;
52 cluster0_opp: opp-table-0 {
92 #size-cells = <0>;
94 a57_0: cpu@0 {
96 reg = <0x0>;
110 reg = <0x1>;
120 L2_CA57: cache-controller-0 {
130 CPU_SLEEP_0: cpu-sleep-0 {
132 arm,psci-suspend-param = <0x0010000>;
143 #clock-cells = <0>;
145 clock-frequency = <0>;
150 #clock-cells = <0>;
152 clock-frequency = <0>;
158 #clock-cells = <0>;
159 clock-frequency = <0>;
178 #clock-cells = <0>;
179 clock-frequency = <0>;
192 reg = <0 0xe6020000 0 0x0c>;
203 reg = <0 0xe6050000 0 0x50>;
207 gpio-ranges = <&pfc 0 0 16>;
218 reg = <0 0xe6051000 0 0x50>;
222 gpio-ranges = <&pfc 0 32 29>;
233 reg = <0 0xe6052000 0 0x50>;
237 gpio-ranges = <&pfc 0 64 15>;
248 reg = <0 0xe6053000 0 0x50>;
252 gpio-ranges = <&pfc 0 96 16>;
263 reg = <0 0xe6054000 0 0x50>;
267 gpio-ranges = <&pfc 0 128 18>;
278 reg = <0 0xe6055000 0 0x50>;
282 gpio-ranges = <&pfc 0 160 26>;
293 reg = <0 0xe6055400 0 0x50>;
297 gpio-ranges = <&pfc 0 192 32>;
308 reg = <0 0xe6055800 0 0x50>;
312 gpio-ranges = <&pfc 0 224 4>;
322 reg = <0 0xe6060000 0 0x50c>;
328 reg = <0 0xe60f0000 0 0x1004>;
341 reg = <0 0xe6130000 0 0x1004>;
360 reg = <0 0xe6140000 0 0x1004>;
379 reg = <0 0xe6148000 0 0x1004>;
397 reg = <0 0xe6150000 0 0x1000>;
401 #power-domain-cells = <0>;
407 reg = <0 0xe6160000 0 0x0200>;
412 reg = <0 0xe6180000 0 0x0400>;
418 reg = <0 0xe6198000 0 0x100>,
419 <0 0xe61a0000 0 0x100>,
420 <0 0xe61a8000 0 0x100>;
434 reg = <0 0xe61c0000 0 0x200>;
435 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
448 reg = <0 0xe61e0000 0 0x30>;
462 reg = <0 0xe6fc0000 0 0x30>;
477 reg = <0 0xe6fd0000 0 0x30>;
492 reg = <0 0xe6fe0000 0 0x30>;
506 reg = <0 0xffc00000 0 0x30>;
520 #size-cells = <0>;
523 reg = <0 0xe6500000 0 0x40>;
528 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
529 <&dmac2 0x91>, <&dmac2 0x90>;
537 #size-cells = <0>;
540 reg = <0 0xe6508000 0 0x40>;
545 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
546 <&dmac2 0x93>, <&dmac2 0x92>;
554 #size-cells = <0>;
557 reg = <0 0xe6510000 0 0x40>;
562 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
563 <&dmac2 0x95>, <&dmac2 0x94>;
571 #size-cells = <0>;
574 reg = <0 0xe66d0000 0 0x40>;
579 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
587 #size-cells = <0>;
590 reg = <0 0xe66d8000 0 0x40>;
595 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
603 #size-cells = <0>;
606 reg = <0 0xe66e0000 0 0x40>;
611 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
619 #size-cells = <0>;
622 reg = <0 0xe66e8000 0 0x40>;
627 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
635 #size-cells = <0>;
639 reg = <0 0xe60b0000 0 0x425>;
644 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
653 reg = <0 0xe6540000 0 0x60>;
659 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
660 <&dmac2 0x31>, <&dmac2 0x30>;
671 reg = <0 0xe6550000 0 0x60>;
677 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
678 <&dmac2 0x33>, <&dmac2 0x32>;
689 reg = <0 0xe6560000 0 0x60>;
695 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
696 <&dmac2 0x35>, <&dmac2 0x34>;
707 reg = <0 0xe66a0000 0 0x60>;
713 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
724 reg = <0 0xe66b0000 0 0x60>;
730 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
740 reg = <0 0xe6590000 0 0x200>;
743 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
744 <&usb_dmac1 0>, <&usb_dmac1 1>;
757 reg = <0 0xe65a0000 0 0x100>;
771 reg = <0 0xe65b0000 0 0x100>;
785 reg = <0 0xe65ee000 0 0x90>;
791 #phy-cells = <0>;
798 reg = <0x0 0xe6601000 0 0x1000>;
807 reg = <0 0xe6700000 0 0x10000>;
836 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
849 reg = <0 0xe7300000 0 0x10000>;
878 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
891 reg = <0 0xe7310000 0 0x10000>;
932 reg = <0 0xe6740000 0 0x1000>;
933 renesas,ipmmu-main = <&ipmmu_mm 0>;
940 reg = <0 0xe7740000 0 0x1000>;
948 reg = <0 0xe6570000 0 0x1000>;
956 reg = <0 0xe67b0000 0 0x1000>;
965 reg = <0 0xec670000 0 0x1000>;
973 reg = <0 0xfd800000 0 0x1000>;
981 reg = <0 0xffc80000 0 0x1000>;
989 reg = <0 0xfe6b0000 0 0x1000>;
997 reg = <0 0xfebd0000 0 0x1000>;
1005 reg = <0 0xfe990000 0 0x1000>;
1014 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
1052 rx-internal-delay-ps = <0>;
1053 tx-internal-delay-ps = <0>;
1056 #size-cells = <0>;
1063 reg = <0 0xe6c30000 0 0x1000>;
1079 reg = <0 0xe6c38000 0 0x1000>;
1095 reg = <0 0xe66c0000 0 0x8000>;
1120 reg = <0 0xe6e30000 0 8>;
1130 reg = <0 0xe6e31000 0 8>;
1140 reg = <0 0xe6e32000 0 8>;
1150 reg = <0 0xe6e33000 0 8>;
1160 reg = <0 0xe6e34000 0 8>;
1170 reg = <0 0xe6e35000 0 8>;
1180 reg = <0 0xe6e36000 0 8>;
1191 reg = <0 0xe6e60000 0 64>;
1197 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1198 <&dmac2 0x51>, <&dmac2 0x50>;
1208 reg = <0 0xe6e68000 0 64>;
1214 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1215 <&dmac2 0x53>, <&dmac2 0x52>;
1225 reg = <0 0xe6e88000 0 64>;
1231 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1232 <&dmac2 0x13>, <&dmac2 0x12>;
1242 reg = <0 0xe6c50000 0 64>;
1248 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1258 reg = <0 0xe6c40000 0 64>;
1264 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1274 reg = <0 0xe6f30000 0 64>;
1280 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1281 <&dmac2 0x5b>, <&dmac2 0x5a>;
1290 reg = <0 0xe6e80000 0 0x148>;
1302 reg = <0 0xe6e90000 0 0x0064>;
1305 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1306 <&dmac2 0x41>, <&dmac2 0x40>;
1311 #size-cells = <0>;
1318 reg = <0 0xe6ea0000 0 0x0064>;
1321 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1322 <&dmac2 0x43>, <&dmac2 0x42>;
1327 #size-cells = <0>;
1334 reg = <0 0xe6c00000 0 0x0064>;
1337 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1342 #size-cells = <0>;
1349 reg = <0 0xe6c10000 0 0x0064>;
1352 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1357 #size-cells = <0>;
1363 reg = <0 0xe6ef0000 0 0x1000>;
1368 renesas,id = <0>;
1373 #size-cells = <0>;
1377 #size-cells = <0>;
1381 vin0csi20: endpoint@0 {
1382 reg = <0>;
1395 reg = <0 0xe6ef1000 0 0x1000>;
1405 #size-cells = <0>;
1409 #size-cells = <0>;
1413 vin1csi20: endpoint@0 {
1414 reg = <0>;
1427 reg = <0 0xe6ef2000 0 0x1000>;
1437 #size-cells = <0>;
1441 #size-cells = <0>;
1445 vin2csi20: endpoint@0 {
1446 reg = <0>;
1459 reg = <0 0xe6ef3000 0 0x1000>;
1469 #size-cells = <0>;
1473 #size-cells = <0>;
1477 vin3csi20: endpoint@0 {
1478 reg = <0>;
1491 reg = <0 0xe6ef4000 0 0x1000>;
1501 #size-cells = <0>;
1505 #size-cells = <0>;
1509 vin4csi20: endpoint@0 {
1510 reg = <0>;
1523 reg = <0 0xe6ef5000 0 0x1000>;
1533 #size-cells = <0>;
1537 #size-cells = <0>;
1541 vin5csi20: endpoint@0 {
1542 reg = <0>;
1555 reg = <0 0xe6ef6000 0 0x1000>;
1565 #size-cells = <0>;
1569 #size-cells = <0>;
1573 vin6csi20: endpoint@0 {
1574 reg = <0>;
1587 reg = <0 0xe6ef7000 0 0x1000>;
1597 #size-cells = <0>;
1601 #size-cells = <0>;
1605 vin7csi20: endpoint@0 {
1606 reg = <0>;
1620 reg = <0 0xe6f40000 0 0x84>;
1624 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
1635 reg = <0 0xe6f50000 0 0x84>;
1639 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
1650 reg = <0 0xe6f60000 0 0x84>;
1654 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
1665 reg = <0 0xe6f70000 0 0x84>;
1669 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
1680 reg = <0 0xe6f80000 0 0x84>;
1684 dmas = <&dmac1 0x28>, <&dmac2 0x28>;
1695 reg = <0 0xe6f90000 0 0x84>;
1699 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
1710 reg = <0 0xe6fa0000 0 0x84>;
1714 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
1725 reg = <0 0xe6fb0000 0 0x84>;
1729 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
1741 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1747 * clkout : #clock-cells = <0>; <&rcar_sound>;
1751 reg = <0 0xec500000 0 0x1000>, /* SCU */
1752 <0 0xec5a0000 0 0x100>, /* ADG */
1753 <0 0xec540000 0 0x1000>, /* SSIU */
1754 <0 0xec541000 0 0x280>, /* SSI */
1755 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1778 "ssi.1", "ssi.0",
1781 "src.1", "src.0",
1782 "mix.1", "mix.0",
1783 "ctu.1", "ctu.0",
1784 "dvc.0", "dvc.1",
1796 "ssi.1", "ssi.0";
1800 dvc0: dvc-0 {
1801 dmas = <&audma1 0xbc>;
1805 dmas = <&audma1 0xbe>;
1811 mix0: mix-0 { };
1816 ctu00: ctu-0 { };
1827 src0: src-0 {
1829 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1834 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1839 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1844 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1849 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1854 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1859 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1864 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1869 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1874 dmas = <&audma0 0x97>, <&audma1 0xba>;
1880 ssiu00: ssiu-0 {
1881 dmas = <&audma0 0x15>, <&audma1 0x16>;
1885 dmas = <&audma0 0x35>, <&audma1 0x36>;
1889 dmas = <&audma0 0x37>, <&audma1 0x38>;
1893 dmas = <&audma0 0x47>, <&audma1 0x48>;
1897 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1901 dmas = <&audma0 0x43>, <&audma1 0x44>;
1905 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1909 dmas = <&audma0 0x53>, <&audma1 0x54>;
1913 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1917 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1921 dmas = <&audma0 0x57>, <&audma1 0x58>;
1925 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1929 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1933 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1937 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1941 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1945 dmas = <&audma0 0x63>, <&audma1 0x64>;
1949 dmas = <&audma0 0x67>, <&audma1 0x68>;
1953 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
1957 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
1961 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
1965 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
1969 dmas = <&audma0 0xED>, <&audma1 0xEE>;
1973 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
1977 dmas = <&audma0 0x6f>, <&audma1 0x70>;
1981 dmas = <&audma0 0x21>, <&audma1 0x22>;
1985 dmas = <&audma0 0x23>, <&audma1 0x24>;
1989 dmas = <&audma0 0x25>, <&audma1 0x26>;
1993 dmas = <&audma0 0x27>, <&audma1 0x28>;
1997 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2001 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2005 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2009 dmas = <&audma0 0x71>, <&audma1 0x72>;
2013 dmas = <&audma0 0x17>, <&audma1 0x18>;
2017 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2021 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2025 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2029 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2033 dmas = <&audma0 0x31>, <&audma1 0x32>;
2037 dmas = <&audma0 0x33>, <&audma1 0x34>;
2041 dmas = <&audma0 0x73>, <&audma1 0x74>;
2045 dmas = <&audma0 0x75>, <&audma1 0x76>;
2049 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2053 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2057 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2061 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2065 dmas = <&audma0 0x81>, <&audma1 0x82>;
2069 dmas = <&audma0 0x83>, <&audma1 0x84>;
2073 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2077 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2081 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2085 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2091 ssi0: ssi-0 {
2093 dmas = <&audma0 0x01>, <&audma1 0x02>;
2098 dmas = <&audma0 0x03>, <&audma1 0x04>;
2103 dmas = <&audma0 0x05>, <&audma1 0x06>;
2108 dmas = <&audma0 0x07>, <&audma1 0x08>;
2113 dmas = <&audma0 0x09>, <&audma1 0x0a>;
2118 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
2123 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
2128 dmas = <&audma0 0x0f>, <&audma1 0x10>;
2133 dmas = <&audma0 0x11>, <&audma1 0x12>;
2138 dmas = <&audma0 0x13>, <&audma1 0x14>;
2147 reg = <0 0xec520000 0 0x800>;
2159 reg = <0 0xec700000 0 0x10000>;
2188 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
2201 reg = <0 0xec720000 0 0x10000>;
2243 reg = <0 0xee000000 0 0xc00>;
2254 reg = <0 0xee020000 0 0x400>;
2264 reg = <0 0xee080000 0 0x100>;
2276 reg = <0 0xee0a0000 0 0x100>;
2288 reg = <0 0xee080100 0 0x100>;
2301 reg = <0 0xee0a0100 0 0x100>;
2315 reg = <0 0xee080200 0 0x700>;
2327 reg = <0 0xee0a0200 0 0x700>;
2338 reg = <0 0xee100000 0 0x2000>;
2352 reg = <0 0xee120000 0 0x2000>;
2366 reg = <0 0xee140000 0 0x2000>;
2380 reg = <0 0xee160000 0 0x2000>;
2394 reg = <0 0xee200000 0 0x200>,
2395 <0 0x08000000 0 0x04000000>,
2396 <0 0xee208000 0 0x100>;
2403 #size-cells = <0>;
2410 reg = <0 0xee300000 0 0x200000>;
2422 #address-cells = <0>;
2424 reg = <0x0 0xf1010000 0 0x1000>,
2425 <0x0 0xf1020000 0 0x20000>,
2426 <0x0 0xf1040000 0 0x20000>,
2427 <0x0 0xf1060000 0 0x20000>;
2439 reg = <0 0xfe000000 0 0x80000>;
2442 bus-range = <0x00 0xff>;
2444 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2445 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2446 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2447 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2449 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2454 interrupt-map-mask = <0 0 0 0>;
2455 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2460 iommu-map = <0 &ipmmu_hc 0 1>;
2461 iommu-map-mask = <0>;
2468 reg = <0 0xee800000 0 0x80000>;
2471 bus-range = <0x00 0xff>;
2473 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2474 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2475 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2476 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2478 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2483 interrupt-map-mask = <0 0 0 0>;
2484 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2489 iommu-map = <0 &ipmmu_hc 1 1>;
2490 iommu-map-mask = <0>;
2496 reg = <0 0xfe940000 0 0x2400>;
2506 reg = <0 0xfe950000 0 0x200>;
2510 iommus = <&ipmmu_vp0 0>;
2515 reg = <0 0xfe960000 0 0x8000>;
2526 reg = <0 0xfe9a0000 0 0x8000>;
2537 reg = <0 0xfea20000 0 0x5000>;
2548 reg = <0 0xfea28000 0 0x5000>;
2559 reg = <0 0xfe96f000 0 0x200>;
2568 reg = <0 0xfea27000 0 0x200>;
2577 reg = <0 0xfea2f000 0 0x200>;
2586 reg = <0 0xfe9af000 0 0x200>;
2596 reg = <0 0xfea40000 0 0x1000>;
2605 reg = <0 0xfea50000 0 0x1000>;
2614 reg = <0 0xfea70000 0 0x1000>;
2622 reg = <0 0xfea80000 0 0x10000>;
2631 #size-cells = <0>;
2633 port@0 {
2634 reg = <0>;
2639 #size-cells = <0>;
2643 csi20vin0: endpoint@0 {
2644 reg = <0>;
2681 reg = <0 0xfeaa0000 0 0x10000>;
2690 #size-cells = <0>;
2692 port@0 {
2693 reg = <0>;
2698 #size-cells = <0>;
2702 csi40vin0: endpoint@0 {
2703 reg = <0>;
2741 reg = <0 0xfead0000 0 0x10000>;
2752 #size-cells = <0>;
2753 port@0 {
2754 reg = <0>;
2767 reg = <0 0xfeb00000 0 0x80000>;
2773 clock-names = "du.0", "du.1", "du.3";
2775 reset-names = "du.0", "du.3";
2778 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
2784 #size-cells = <0>;
2786 port@0 {
2787 reg = <0>;
2806 reg = <0 0xfeb90000 0 0x14>;
2814 #size-cells = <0>;
2816 port@0 {
2817 reg = <0>;
2830 reg = <0 0xfff00044 0 4>;
2838 thermal-sensors = <&tsc 0>;
2908 #clock-cells = <0>;
2909 clock-frequency = <0>;
2914 #clock-cells = <0>;
2915 clock-frequency = <0>;