Lines Matching +full:0 +full:xe65ee000
18 * The external audio clocks are configured as 0 Hz fixed frequency
24 #clock-cells = <0>;
25 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
36 #clock-cells = <0>;
37 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
47 cluster0_opp: opp-table-0 {
114 #size-cells = <0>;
142 a57_0: cpu@0 {
144 reg = <0x0>;
159 reg = <0x1>;
173 reg = <0x100>;
188 reg = <0x101>;
201 reg = <0x102>;
214 reg = <0x103>;
225 L2_CA57: cache-controller-0 {
242 CPU_SLEEP_0: cpu-sleep-0 {
244 arm,psci-suspend-param = <0x0010000>;
253 arm,psci-suspend-param = <0x0010000>;
264 #clock-cells = <0>;
266 clock-frequency = <0>;
272 #clock-cells = <0>;
274 clock-frequency = <0>;
281 #clock-cells = <0>;
282 clock-frequency = <0>;
309 #clock-cells = <0>;
310 clock-frequency = <0>;
325 reg = <0 0xe6020000 0 0x0c>;
336 reg = <0 0xe6050000 0 0x50>;
340 gpio-ranges = <&pfc 0 0 16>;
351 reg = <0 0xe6051000 0 0x50>;
355 gpio-ranges = <&pfc 0 32 29>;
366 reg = <0 0xe6052000 0 0x50>;
370 gpio-ranges = <&pfc 0 64 15>;
381 reg = <0 0xe6053000 0 0x50>;
385 gpio-ranges = <&pfc 0 96 16>;
396 reg = <0 0xe6054000 0 0x50>;
400 gpio-ranges = <&pfc 0 128 18>;
411 reg = <0 0xe6055000 0 0x50>;
415 gpio-ranges = <&pfc 0 160 26>;
426 reg = <0 0xe6055400 0 0x50>;
430 gpio-ranges = <&pfc 0 192 32>;
441 reg = <0 0xe6055800 0 0x50>;
445 gpio-ranges = <&pfc 0 224 4>;
455 reg = <0 0xe6060000 0 0x50c>;
462 reg = <0 0xe60f0000 0 0x1004>;
475 reg = <0 0xe6130000 0 0x1004>;
494 reg = <0 0xe6140000 0 0x1004>;
513 reg = <0 0xe6148000 0 0x1004>;
531 reg = <0 0xe6150000 0 0x1000>;
535 #power-domain-cells = <0>;
542 reg = <0 0xe6160000 0 0x0200>;
548 reg = <0 0xe6180000 0 0x0400>;
554 reg = <0 0xe6198000 0 0x100>,
555 <0 0xe61a0000 0 0x100>,
556 <0 0xe61a8000 0 0x100>;
570 reg = <0 0xe61c0000 0 0x200>;
571 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
584 reg = <0 0xe61e0000 0 0x30>;
598 reg = <0 0xe6fc0000 0 0x30>;
613 reg = <0 0xe6fd0000 0 0x30>;
628 reg = <0 0xe6fe0000 0 0x30>;
642 reg = <0 0xffc00000 0 0x30>;
656 #size-cells = <0>;
659 reg = <0 0xe6500000 0 0x40>;
664 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
665 <&dmac2 0x91>, <&dmac2 0x90>;
673 #size-cells = <0>;
676 reg = <0 0xe6508000 0 0x40>;
681 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
682 <&dmac2 0x93>, <&dmac2 0x92>;
690 #size-cells = <0>;
693 reg = <0 0xe6510000 0 0x40>;
698 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
699 <&dmac2 0x95>, <&dmac2 0x94>;
707 #size-cells = <0>;
710 reg = <0 0xe66d0000 0 0x40>;
715 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
723 #size-cells = <0>;
726 reg = <0 0xe66d8000 0 0x40>;
731 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
739 #size-cells = <0>;
742 reg = <0 0xe66e0000 0 0x40>;
747 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
755 #size-cells = <0>;
758 reg = <0 0xe66e8000 0 0x40>;
763 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
771 #size-cells = <0>;
775 reg = <0 0xe60b0000 0 0x425>;
780 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
789 reg = <0 0xe6540000 0 0x60>;
795 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
796 <&dmac2 0x31>, <&dmac2 0x30>;
807 reg = <0 0xe6550000 0 0x60>;
813 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
814 <&dmac2 0x33>, <&dmac2 0x32>;
825 reg = <0 0xe6560000 0 0x60>;
831 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
832 <&dmac2 0x35>, <&dmac2 0x34>;
843 reg = <0 0xe66a0000 0 0x60>;
849 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
860 reg = <0 0xe66b0000 0 0x60>;
866 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
876 reg = <0 0xe6590000 0 0x200>;
879 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
880 <&usb_dmac1 0>, <&usb_dmac1 1>;
893 reg = <0 0xe65a0000 0 0x100>;
907 reg = <0 0xe65b0000 0 0x100>;
921 reg = <0 0xe65ee000 0 0x90>;
927 #phy-cells = <0>;
934 reg = <0x0 0xe6601000 0 0x1000>;
943 reg = <0 0xe6700000 0 0x10000>;
972 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
985 reg = <0 0xe7300000 0 0x10000>;
1014 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1027 reg = <0 0xe7310000 0 0x10000>;
1068 reg = <0 0xe6740000 0 0x1000>;
1069 renesas,ipmmu-main = <&ipmmu_mm 0>;
1076 reg = <0 0xe7740000 0 0x1000>;
1084 reg = <0 0xe6570000 0 0x1000>;
1092 reg = <0 0xff8b0000 0 0x1000>;
1100 reg = <0 0xe67b0000 0 0x1000>;
1109 reg = <0 0xec670000 0 0x1000>;
1117 reg = <0 0xfd800000 0 0x1000>;
1125 reg = <0 0xfd950000 0 0x1000>;
1133 reg = <0 0xffc80000 0 0x1000>;
1141 reg = <0 0xfe6b0000 0 0x1000>;
1149 reg = <0 0xfebd0000 0 0x1000>;
1158 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
1196 rx-internal-delay-ps = <0>;
1197 tx-internal-delay-ps = <0>;
1200 #size-cells = <0>;
1207 reg = <0 0xe6c30000 0 0x1000>;
1223 reg = <0 0xe6c38000 0 0x1000>;
1239 reg = <0 0xe66c0000 0 0x8000>;
1264 reg = <0 0xe6e30000 0 8>;
1274 reg = <0 0xe6e31000 0 8>;
1284 reg = <0 0xe6e32000 0 8>;
1294 reg = <0 0xe6e33000 0 8>;
1304 reg = <0 0xe6e34000 0 8>;
1314 reg = <0 0xe6e35000 0 8>;
1324 reg = <0 0xe6e36000 0 8>;
1335 reg = <0 0xe6e60000 0 64>;
1341 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1342 <&dmac2 0x51>, <&dmac2 0x50>;
1352 reg = <0 0xe6e68000 0 64>;
1358 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1359 <&dmac2 0x53>, <&dmac2 0x52>;
1369 reg = <0 0xe6e88000 0 64>;
1375 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1376 <&dmac2 0x13>, <&dmac2 0x12>;
1386 reg = <0 0xe6c50000 0 64>;
1392 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1402 reg = <0 0xe6c40000 0 64>;
1408 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1418 reg = <0 0xe6f30000 0 64>;
1424 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1425 <&dmac2 0x5b>, <&dmac2 0x5a>;
1434 reg = <0 0xe6e80000 0 0x148>;
1446 reg = <0 0xe6e90000 0 0x0064>;
1449 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1450 <&dmac2 0x41>, <&dmac2 0x40>;
1455 #size-cells = <0>;
1462 reg = <0 0xe6ea0000 0 0x0064>;
1465 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1466 <&dmac2 0x43>, <&dmac2 0x42>;
1471 #size-cells = <0>;
1478 reg = <0 0xe6c00000 0 0x0064>;
1481 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1486 #size-cells = <0>;
1493 reg = <0 0xe6c10000 0 0x0064>;
1496 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1501 #size-cells = <0>;
1507 reg = <0 0xe6ef0000 0 0x1000>;
1512 renesas,id = <0>;
1517 #size-cells = <0>;
1521 #size-cells = <0>;
1525 vin0csi20: endpoint@0 {
1526 reg = <0>;
1539 reg = <0 0xe6ef1000 0 0x1000>;
1549 #size-cells = <0>;
1553 #size-cells = <0>;
1557 vin1csi20: endpoint@0 {
1558 reg = <0>;
1571 reg = <0 0xe6ef2000 0 0x1000>;
1581 #size-cells = <0>;
1585 #size-cells = <0>;
1589 vin2csi20: endpoint@0 {
1590 reg = <0>;
1603 reg = <0 0xe6ef3000 0 0x1000>;
1613 #size-cells = <0>;
1617 #size-cells = <0>;
1621 vin3csi20: endpoint@0 {
1622 reg = <0>;
1635 reg = <0 0xe6ef4000 0 0x1000>;
1645 #size-cells = <0>;
1649 #size-cells = <0>;
1653 vin4csi20: endpoint@0 {
1654 reg = <0>;
1667 reg = <0 0xe6ef5000 0 0x1000>;
1677 #size-cells = <0>;
1681 #size-cells = <0>;
1685 vin5csi20: endpoint@0 {
1686 reg = <0>;
1699 reg = <0 0xe6ef6000 0 0x1000>;
1709 #size-cells = <0>;
1713 #size-cells = <0>;
1717 vin6csi20: endpoint@0 {
1718 reg = <0>;
1731 reg = <0 0xe6ef7000 0 0x1000>;
1741 #size-cells = <0>;
1745 #size-cells = <0>;
1749 vin7csi20: endpoint@0 {
1750 reg = <0>;
1765 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1771 * clkout : #clock-cells = <0>; <&rcar_sound>;
1775 reg = <0 0xec500000 0 0x1000>, /* SCU */
1776 <0 0xec5a0000 0 0x100>, /* ADG */
1777 <0 0xec540000 0 0x1000>, /* SSIU */
1778 <0 0xec541000 0 0x280>, /* SSI */
1779 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1802 "ssi.1", "ssi.0",
1805 "src.1", "src.0",
1806 "mix.1", "mix.0",
1807 "ctu.1", "ctu.0",
1808 "dvc.0", "dvc.1",
1820 "ssi.1", "ssi.0";
1824 ctu00: ctu-0 { };
1835 dvc0: dvc-0 {
1836 dmas = <&audma1 0xbc>;
1840 dmas = <&audma1 0xbe>;
1846 mix0: mix-0 { };
1851 src0: src-0 {
1853 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1858 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1863 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1868 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1873 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1878 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1883 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1888 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1893 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1898 dmas = <&audma0 0x97>, <&audma1 0xba>;
1904 ssi0: ssi-0 {
1906 dmas = <&audma0 0x01>, <&audma1 0x02>;
1911 dmas = <&audma0 0x03>, <&audma1 0x04>;
1916 dmas = <&audma0 0x05>, <&audma1 0x06>;
1921 dmas = <&audma0 0x07>, <&audma1 0x08>;
1926 dmas = <&audma0 0x09>, <&audma1 0x0a>;
1931 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
1936 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
1941 dmas = <&audma0 0x0f>, <&audma1 0x10>;
1946 dmas = <&audma0 0x11>, <&audma1 0x12>;
1951 dmas = <&audma0 0x13>, <&audma1 0x14>;
1957 ssiu00: ssiu-0 {
1958 dmas = <&audma0 0x15>, <&audma1 0x16>;
1962 dmas = <&audma0 0x35>, <&audma1 0x36>;
1966 dmas = <&audma0 0x37>, <&audma1 0x38>;
1970 dmas = <&audma0 0x47>, <&audma1 0x48>;
1974 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1978 dmas = <&audma0 0x43>, <&audma1 0x44>;
1982 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1986 dmas = <&audma0 0x53>, <&audma1 0x54>;
1990 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1994 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1998 dmas = <&audma0 0x57>, <&audma1 0x58>;
2002 dmas = <&audma0 0x59>, <&audma1 0x5A>;
2006 dmas = <&audma0 0x5F>, <&audma1 0x60>;
2010 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
2014 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
2018 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
2022 dmas = <&audma0 0x63>, <&audma1 0x64>;
2026 dmas = <&audma0 0x67>, <&audma1 0x68>;
2030 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
2034 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
2038 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
2042 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
2046 dmas = <&audma0 0xED>, <&audma1 0xEE>;
2050 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
2054 dmas = <&audma0 0x6f>, <&audma1 0x70>;
2058 dmas = <&audma0 0x21>, <&audma1 0x22>;
2062 dmas = <&audma0 0x23>, <&audma1 0x24>;
2066 dmas = <&audma0 0x25>, <&audma1 0x26>;
2070 dmas = <&audma0 0x27>, <&audma1 0x28>;
2074 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2078 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2082 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2086 dmas = <&audma0 0x71>, <&audma1 0x72>;
2090 dmas = <&audma0 0x17>, <&audma1 0x18>;
2094 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2098 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2102 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2106 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2110 dmas = <&audma0 0x31>, <&audma1 0x32>;
2114 dmas = <&audma0 0x33>, <&audma1 0x34>;
2118 dmas = <&audma0 0x73>, <&audma1 0x74>;
2122 dmas = <&audma0 0x75>, <&audma1 0x76>;
2126 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2130 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2134 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2138 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2142 dmas = <&audma0 0x81>, <&audma1 0x82>;
2146 dmas = <&audma0 0x83>, <&audma1 0x84>;
2150 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2154 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2158 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2162 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2171 reg = <0 0xec520000 0 0x800>;
2183 reg = <0 0xec700000 0 0x10000>;
2212 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
2225 reg = <0 0xec720000 0 0x10000>;
2267 reg = <0 0xee000000 0 0xc00>;
2278 reg = <0 0xee020000 0 0x400>;
2288 reg = <0 0xee080000 0 0x100>;
2300 reg = <0 0xee0a0000 0 0x100>;
2312 reg = <0 0xee080100 0 0x100>;
2325 reg = <0 0xee0a0100 0 0x100>;
2339 reg = <0 0xee080200 0 0x700>;
2351 reg = <0 0xee0a0200 0 0x700>;
2362 reg = <0 0xee100000 0 0x2000>;
2376 reg = <0 0xee120000 0 0x2000>;
2390 reg = <0 0xee140000 0 0x2000>;
2404 reg = <0 0xee160000 0 0x2000>;
2418 reg = <0 0xee200000 0 0x200>,
2419 <0 0x08000000 0 0x04000000>,
2420 <0 0xee208000 0 0x100>;
2427 #size-cells = <0>;
2434 #address-cells = <0>;
2436 reg = <0x0 0xf1010000 0 0x1000>,
2437 <0x0 0xf1020000 0 0x20000>,
2438 <0x0 0xf1040000 0 0x20000>,
2439 <0x0 0xf1060000 0 0x20000>;
2451 reg = <0 0xfe000000 0 0x80000>;
2454 bus-range = <0x00 0xff>;
2456 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2457 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2458 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2459 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2461 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2466 interrupt-map-mask = <0 0 0 0>;
2467 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2472 iommu-map = <0 &ipmmu_hc 0 1>;
2473 iommu-map-mask = <0>;
2480 reg = <0 0xee800000 0 0x80000>;
2483 bus-range = <0x00 0xff>;
2485 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2486 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2487 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2488 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2490 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2495 interrupt-map-mask = <0 0 0 0>;
2496 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2501 iommu-map = <0 &ipmmu_hc 1 1>;
2502 iommu-map-mask = <0>;
2508 reg = <0 0xfe950000 0 0x200>;
2517 reg = <0 0xfe96f000 0 0x200>;
2526 reg = <0 0xfe9af000 0 0x200>;
2535 reg = <0 0xfea27000 0 0x200>;
2544 reg = <0 0xfea2f000 0 0x200>;
2553 reg = <0 0xfea37000 0 0x200>;
2562 reg = <0 0xfe960000 0 0x8000>;
2573 reg = <0 0xfea20000 0 0x5000>;
2584 reg = <0 0xfea28000 0 0x5000>;
2595 reg = <0 0xfea30000 0 0x5000>;
2606 reg = <0 0xfe9a0000 0 0x8000>;
2617 reg = <0 0xfea80000 0 0x10000>;
2626 #size-cells = <0>;
2628 port@0 {
2629 reg = <0>;
2634 #size-cells = <0>;
2638 csi20vin0: endpoint@0 {
2639 reg = <0>;
2676 reg = <0 0xfeaa0000 0 0x10000>;
2685 #size-cells = <0>;
2687 port@0 {
2688 reg = <0>;
2693 #size-cells = <0>;
2697 csi40vin0: endpoint@0 {
2698 reg = <0>;
2736 reg = <0 0xfead0000 0 0x10000>;
2746 #size-cells = <0>;
2747 port@0 {
2748 reg = <0>;
2765 reg = <0 0xfeb00000 0 0x70000>;
2771 clock-names = "du.0", "du.1", "du.2";
2773 reset-names = "du.0", "du.2";
2775 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
2780 #size-cells = <0>;
2782 port@0 {
2783 reg = <0>;
2802 reg = <0 0xfeb90000 0 0x14>;
2810 #size-cells = <0>;
2812 port@0 {
2813 reg = <0>;
2826 reg = <0 0xfff00044 0 4>;
2835 thermal-sensors = <&tsc 0>;
2876 cooling-device = <&a53_0 0 2>;
2908 #clock-cells = <0>;
2909 clock-frequency = <0>;
2914 #clock-cells = <0>;
2915 clock-frequency = <0>;