Lines Matching +full:0 +full:xe6160000
18 * The external audio clocks are configured as 0 Hz fixed frequency
24 #clock-cells = <0>;
25 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
36 #clock-cells = <0>;
37 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
47 cluster0_opp: opp-table-0 {
114 #size-cells = <0>;
142 a57_0: cpu@0 {
144 reg = <0x0>;
159 reg = <0x1>;
173 reg = <0x100>;
188 reg = <0x101>;
201 reg = <0x102>;
214 reg = <0x103>;
225 L2_CA57: cache-controller-0 {
242 CPU_SLEEP_0: cpu-sleep-0 {
244 arm,psci-suspend-param = <0x0010000>;
253 arm,psci-suspend-param = <0x0010000>;
264 #clock-cells = <0>;
266 clock-frequency = <0>;
271 #clock-cells = <0>;
273 clock-frequency = <0>;
279 #clock-cells = <0>;
280 clock-frequency = <0>;
307 #clock-cells = <0>;
308 clock-frequency = <0>;
321 reg = <0 0xe6020000 0 0x0c>;
332 reg = <0 0xe6050000 0 0x50>;
336 gpio-ranges = <&pfc 0 0 16>;
347 reg = <0 0xe6051000 0 0x50>;
351 gpio-ranges = <&pfc 0 32 29>;
362 reg = <0 0xe6052000 0 0x50>;
366 gpio-ranges = <&pfc 0 64 15>;
377 reg = <0 0xe6053000 0 0x50>;
381 gpio-ranges = <&pfc 0 96 16>;
392 reg = <0 0xe6054000 0 0x50>;
396 gpio-ranges = <&pfc 0 128 18>;
407 reg = <0 0xe6055000 0 0x50>;
411 gpio-ranges = <&pfc 0 160 26>;
422 reg = <0 0xe6055400 0 0x50>;
426 gpio-ranges = <&pfc 0 192 32>;
437 reg = <0 0xe6055800 0 0x50>;
441 gpio-ranges = <&pfc 0 224 4>;
451 reg = <0 0xe6060000 0 0x50c>;
457 reg = <0 0xe60f0000 0 0x1004>;
470 reg = <0 0xe6130000 0 0x1004>;
489 reg = <0 0xe6140000 0 0x1004>;
508 reg = <0 0xe6148000 0 0x1004>;
526 reg = <0 0xe6150000 0 0x1000>;
530 #power-domain-cells = <0>;
536 reg = <0 0xe6160000 0 0x0200>;
541 reg = <0 0xe6180000 0 0x0400>;
547 reg = <0 0xe6198000 0 0x100>,
548 <0 0xe61a0000 0 0x100>,
549 <0 0xe61a8000 0 0x100>;
563 reg = <0 0xe61c0000 0 0x200>;
564 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
577 reg = <0 0xe61e0000 0 0x30>;
591 reg = <0 0xe6fc0000 0 0x30>;
606 reg = <0 0xe6fd0000 0 0x30>;
621 reg = <0 0xe6fe0000 0 0x30>;
635 reg = <0 0xffc00000 0 0x30>;
649 #size-cells = <0>;
652 reg = <0 0xe6500000 0 0x40>;
657 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
658 <&dmac2 0x91>, <&dmac2 0x90>;
666 #size-cells = <0>;
669 reg = <0 0xe6508000 0 0x40>;
674 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
675 <&dmac2 0x93>, <&dmac2 0x92>;
683 #size-cells = <0>;
686 reg = <0 0xe6510000 0 0x40>;
691 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
692 <&dmac2 0x95>, <&dmac2 0x94>;
700 #size-cells = <0>;
703 reg = <0 0xe66d0000 0 0x40>;
708 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
716 #size-cells = <0>;
719 reg = <0 0xe66d8000 0 0x40>;
724 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
732 #size-cells = <0>;
735 reg = <0 0xe66e0000 0 0x40>;
740 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
748 #size-cells = <0>;
751 reg = <0 0xe66e8000 0 0x40>;
756 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
764 #size-cells = <0>;
768 reg = <0 0xe60b0000 0 0x425>;
773 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
782 reg = <0 0xe6540000 0 0x60>;
788 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
789 <&dmac2 0x31>, <&dmac2 0x30>;
800 reg = <0 0xe6550000 0 0x60>;
806 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
807 <&dmac2 0x33>, <&dmac2 0x32>;
818 reg = <0 0xe6560000 0 0x60>;
824 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
825 <&dmac2 0x35>, <&dmac2 0x34>;
836 reg = <0 0xe66a0000 0 0x60>;
842 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
853 reg = <0 0xe66b0000 0 0x60>;
859 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
869 reg = <0 0xe6590000 0 0x200>;
872 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
873 <&usb_dmac1 0>, <&usb_dmac1 1>;
886 reg = <0 0xe65a0000 0 0x100>;
900 reg = <0 0xe65b0000 0 0x100>;
914 reg = <0 0xe65ee000 0 0x90>;
920 #phy-cells = <0>;
927 reg = <0x0 0xe6601000 0 0x1000>;
936 reg = <0 0xe6700000 0 0x10000>;
965 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
978 reg = <0 0xe7300000 0 0x10000>;
1007 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1020 reg = <0 0xe7310000 0 0x10000>;
1061 reg = <0 0xe6740000 0 0x1000>;
1062 renesas,ipmmu-main = <&ipmmu_mm 0>;
1069 reg = <0 0xe7740000 0 0x1000>;
1077 reg = <0 0xe6570000 0 0x1000>;
1085 reg = <0 0xff8b0000 0 0x1000>;
1093 reg = <0 0xe67b0000 0 0x1000>;
1102 reg = <0 0xec670000 0 0x1000>;
1110 reg = <0 0xfd800000 0 0x1000>;
1118 reg = <0 0xfd950000 0 0x1000>;
1126 reg = <0 0xffc80000 0 0x1000>;
1134 reg = <0 0xfe6b0000 0 0x1000>;
1142 reg = <0 0xfebd0000 0 0x1000>;
1151 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
1189 rx-internal-delay-ps = <0>;
1190 tx-internal-delay-ps = <0>;
1193 #size-cells = <0>;
1200 reg = <0 0xe6c30000 0 0x1000>;
1216 reg = <0 0xe6c38000 0 0x1000>;
1232 reg = <0 0xe66c0000 0 0x8000>;
1257 reg = <0 0xe6e30000 0 8>;
1267 reg = <0 0xe6e31000 0 8>;
1277 reg = <0 0xe6e32000 0 8>;
1287 reg = <0 0xe6e33000 0 8>;
1297 reg = <0 0xe6e34000 0 8>;
1307 reg = <0 0xe6e35000 0 8>;
1317 reg = <0 0xe6e36000 0 8>;
1328 reg = <0 0xe6e60000 0 64>;
1334 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1335 <&dmac2 0x51>, <&dmac2 0x50>;
1345 reg = <0 0xe6e68000 0 64>;
1351 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1352 <&dmac2 0x53>, <&dmac2 0x52>;
1362 reg = <0 0xe6e88000 0 64>;
1368 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1369 <&dmac2 0x13>, <&dmac2 0x12>;
1379 reg = <0 0xe6c50000 0 64>;
1385 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1395 reg = <0 0xe6c40000 0 64>;
1401 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1411 reg = <0 0xe6f30000 0 64>;
1417 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1418 <&dmac2 0x5b>, <&dmac2 0x5a>;
1427 reg = <0 0xe6e80000 0 0x148>;
1439 reg = <0 0xe6e90000 0 0x0064>;
1442 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1443 <&dmac2 0x41>, <&dmac2 0x40>;
1448 #size-cells = <0>;
1455 reg = <0 0xe6ea0000 0 0x0064>;
1458 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1459 <&dmac2 0x43>, <&dmac2 0x42>;
1464 #size-cells = <0>;
1471 reg = <0 0xe6c00000 0 0x0064>;
1474 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1479 #size-cells = <0>;
1486 reg = <0 0xe6c10000 0 0x0064>;
1489 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1494 #size-cells = <0>;
1500 reg = <0 0xe6ef0000 0 0x1000>;
1505 renesas,id = <0>;
1510 #size-cells = <0>;
1514 #size-cells = <0>;
1518 vin0csi20: endpoint@0 {
1519 reg = <0>;
1532 reg = <0 0xe6ef1000 0 0x1000>;
1542 #size-cells = <0>;
1546 #size-cells = <0>;
1550 vin1csi20: endpoint@0 {
1551 reg = <0>;
1564 reg = <0 0xe6ef2000 0 0x1000>;
1574 #size-cells = <0>;
1578 #size-cells = <0>;
1582 vin2csi20: endpoint@0 {
1583 reg = <0>;
1596 reg = <0 0xe6ef3000 0 0x1000>;
1606 #size-cells = <0>;
1610 #size-cells = <0>;
1614 vin3csi20: endpoint@0 {
1615 reg = <0>;
1628 reg = <0 0xe6ef4000 0 0x1000>;
1638 #size-cells = <0>;
1642 #size-cells = <0>;
1646 vin4csi20: endpoint@0 {
1647 reg = <0>;
1660 reg = <0 0xe6ef5000 0 0x1000>;
1670 #size-cells = <0>;
1674 #size-cells = <0>;
1678 vin5csi20: endpoint@0 {
1679 reg = <0>;
1692 reg = <0 0xe6ef6000 0 0x1000>;
1702 #size-cells = <0>;
1706 #size-cells = <0>;
1710 vin6csi20: endpoint@0 {
1711 reg = <0>;
1724 reg = <0 0xe6ef7000 0 0x1000>;
1734 #size-cells = <0>;
1738 #size-cells = <0>;
1742 vin7csi20: endpoint@0 {
1743 reg = <0>;
1758 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1764 * clkout : #clock-cells = <0>; <&rcar_sound>;
1768 reg = <0 0xec500000 0 0x1000>, /* SCU */
1769 <0 0xec5a0000 0 0x100>, /* ADG */
1770 <0 0xec540000 0 0x1000>, /* SSIU */
1771 <0 0xec541000 0 0x280>, /* SSI */
1772 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1795 "ssi.1", "ssi.0",
1798 "src.1", "src.0",
1799 "mix.1", "mix.0",
1800 "ctu.1", "ctu.0",
1801 "dvc.0", "dvc.1",
1813 "ssi.1", "ssi.0";
1817 ctu00: ctu-0 { };
1828 dvc0: dvc-0 {
1829 dmas = <&audma1 0xbc>;
1833 dmas = <&audma1 0xbe>;
1839 mix0: mix-0 { };
1844 src0: src-0 {
1846 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1851 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1856 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1861 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1866 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1871 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1876 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1881 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1886 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1891 dmas = <&audma0 0x97>, <&audma1 0xba>;
1897 ssi0: ssi-0 {
1899 dmas = <&audma0 0x01>, <&audma1 0x02>;
1904 dmas = <&audma0 0x03>, <&audma1 0x04>;
1909 dmas = <&audma0 0x05>, <&audma1 0x06>;
1914 dmas = <&audma0 0x07>, <&audma1 0x08>;
1919 dmas = <&audma0 0x09>, <&audma1 0x0a>;
1924 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
1929 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
1934 dmas = <&audma0 0x0f>, <&audma1 0x10>;
1939 dmas = <&audma0 0x11>, <&audma1 0x12>;
1944 dmas = <&audma0 0x13>, <&audma1 0x14>;
1950 ssiu00: ssiu-0 {
1951 dmas = <&audma0 0x15>, <&audma1 0x16>;
1955 dmas = <&audma0 0x35>, <&audma1 0x36>;
1959 dmas = <&audma0 0x37>, <&audma1 0x38>;
1963 dmas = <&audma0 0x47>, <&audma1 0x48>;
1967 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1971 dmas = <&audma0 0x43>, <&audma1 0x44>;
1975 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1979 dmas = <&audma0 0x53>, <&audma1 0x54>;
1983 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1987 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1991 dmas = <&audma0 0x57>, <&audma1 0x58>;
1995 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1999 dmas = <&audma0 0x5F>, <&audma1 0x60>;
2003 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
2007 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
2011 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
2015 dmas = <&audma0 0x63>, <&audma1 0x64>;
2019 dmas = <&audma0 0x67>, <&audma1 0x68>;
2023 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
2027 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
2031 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
2035 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
2039 dmas = <&audma0 0xED>, <&audma1 0xEE>;
2043 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
2047 dmas = <&audma0 0x6f>, <&audma1 0x70>;
2051 dmas = <&audma0 0x21>, <&audma1 0x22>;
2055 dmas = <&audma0 0x23>, <&audma1 0x24>;
2059 dmas = <&audma0 0x25>, <&audma1 0x26>;
2063 dmas = <&audma0 0x27>, <&audma1 0x28>;
2067 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2071 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2075 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2079 dmas = <&audma0 0x71>, <&audma1 0x72>;
2083 dmas = <&audma0 0x17>, <&audma1 0x18>;
2087 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2091 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2095 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2099 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2103 dmas = <&audma0 0x31>, <&audma1 0x32>;
2107 dmas = <&audma0 0x33>, <&audma1 0x34>;
2111 dmas = <&audma0 0x73>, <&audma1 0x74>;
2115 dmas = <&audma0 0x75>, <&audma1 0x76>;
2119 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2123 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2127 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2131 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2135 dmas = <&audma0 0x81>, <&audma1 0x82>;
2139 dmas = <&audma0 0x83>, <&audma1 0x84>;
2143 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2147 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2151 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2155 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2164 reg = <0 0xec520000 0 0x800>;
2176 reg = <0 0xec700000 0 0x10000>;
2205 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
2218 reg = <0 0xec720000 0 0x10000>;
2260 reg = <0 0xee000000 0 0xc00>;
2271 reg = <0 0xee020000 0 0x400>;
2281 reg = <0 0xee080000 0 0x100>;
2293 reg = <0 0xee0a0000 0 0x100>;
2305 reg = <0 0xee080100 0 0x100>;
2318 reg = <0 0xee0a0100 0 0x100>;
2332 reg = <0 0xee080200 0 0x700>;
2344 reg = <0 0xee0a0200 0 0x700>;
2355 reg = <0 0xee100000 0 0x2000>;
2369 reg = <0 0xee120000 0 0x2000>;
2383 reg = <0 0xee140000 0 0x2000>;
2397 reg = <0 0xee160000 0 0x2000>;
2411 reg = <0 0xee200000 0 0x200>,
2412 <0 0x08000000 0 0x04000000>,
2413 <0 0xee208000 0 0x100>;
2420 #size-cells = <0>;
2427 #address-cells = <0>;
2429 reg = <0x0 0xf1010000 0 0x1000>,
2430 <0x0 0xf1020000 0 0x20000>,
2431 <0x0 0xf1040000 0 0x20000>,
2432 <0x0 0xf1060000 0 0x20000>;
2444 reg = <0 0xfe000000 0 0x80000>;
2447 bus-range = <0x00 0xff>;
2449 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2450 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2451 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2452 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2454 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2459 interrupt-map-mask = <0 0 0 0>;
2460 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2465 iommu-map = <0 &ipmmu_hc 0 1>;
2466 iommu-map-mask = <0>;
2473 reg = <0 0xee800000 0 0x80000>;
2476 bus-range = <0x00 0xff>;
2478 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2479 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2480 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2481 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2483 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2488 interrupt-map-mask = <0 0 0 0>;
2489 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2494 iommu-map = <0 &ipmmu_hc 1 1>;
2495 iommu-map-mask = <0>;
2501 reg = <0 0xfe950000 0 0x200>;
2510 reg = <0 0xfe96f000 0 0x200>;
2519 reg = <0 0xfe9af000 0 0x200>;
2528 reg = <0 0xfea27000 0 0x200>;
2537 reg = <0 0xfea2f000 0 0x200>;
2546 reg = <0 0xfea37000 0 0x200>;
2555 reg = <0 0xfe960000 0 0x8000>;
2566 reg = <0 0xfea20000 0 0x5000>;
2577 reg = <0 0xfea28000 0 0x5000>;
2588 reg = <0 0xfea30000 0 0x5000>;
2599 reg = <0 0xfe9a0000 0 0x8000>;
2610 reg = <0 0xfea80000 0 0x10000>;
2619 #size-cells = <0>;
2621 port@0 {
2622 reg = <0>;
2627 #size-cells = <0>;
2631 csi20vin0: endpoint@0 {
2632 reg = <0>;
2669 reg = <0 0xfeaa0000 0 0x10000>;
2678 #size-cells = <0>;
2680 port@0 {
2681 reg = <0>;
2686 #size-cells = <0>;
2690 csi40vin0: endpoint@0 {
2691 reg = <0>;
2729 reg = <0 0xfead0000 0 0x10000>;
2739 #size-cells = <0>;
2740 port@0 {
2741 reg = <0>;
2758 reg = <0 0xfeb00000 0 0x70000>;
2764 clock-names = "du.0", "du.1", "du.2";
2766 reset-names = "du.0", "du.2";
2768 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
2773 #size-cells = <0>;
2775 port@0 {
2776 reg = <0>;
2795 reg = <0 0xfeb90000 0 0x14>;
2803 #size-cells = <0>;
2805 port@0 {
2806 reg = <0>;
2819 reg = <0 0xfff00044 0 4>;
2827 thermal-sensors = <&tsc 0>;
2868 cooling-device = <&a53_0 0 2>;
2900 #clock-cells = <0>;
2901 clock-frequency = <0>;
2906 #clock-cells = <0>;
2907 clock-frequency = <0>;