Lines Matching +full:0 +full:xe6ef2000
19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
45 clock-frequency = <0>;
48 cluster0_opp: opp-table-0 {
93 #size-cells = <0>;
127 a57_0: cpu@0 {
129 reg = <0x0>;
144 reg = <0x1>;
158 reg = <0x2>;
172 reg = <0x3>;
186 reg = <0x100>;
201 reg = <0x101>;
214 reg = <0x102>;
227 reg = <0x103>;
238 L2_CA57: cache-controller-0 {
255 CPU_SLEEP_0: cpu-sleep-0 {
257 arm,psci-suspend-param = <0x0010000>;
266 arm,psci-suspend-param = <0x0010000>;
277 #clock-cells = <0>;
279 clock-frequency = <0>;
284 #clock-cells = <0>;
286 clock-frequency = <0>;
292 #clock-cells = <0>;
293 clock-frequency = <0>;
322 #clock-cells = <0>;
323 clock-frequency = <0>;
336 reg = <0 0xe6020000 0 0x0c>;
347 reg = <0 0xe6050000 0 0x50>;
351 gpio-ranges = <&pfc 0 0 16>;
362 reg = <0 0xe6051000 0 0x50>;
366 gpio-ranges = <&pfc 0 32 29>;
377 reg = <0 0xe6052000 0 0x50>;
381 gpio-ranges = <&pfc 0 64 15>;
392 reg = <0 0xe6053000 0 0x50>;
396 gpio-ranges = <&pfc 0 96 16>;
407 reg = <0 0xe6054000 0 0x50>;
411 gpio-ranges = <&pfc 0 128 18>;
422 reg = <0 0xe6055000 0 0x50>;
426 gpio-ranges = <&pfc 0 160 26>;
437 reg = <0 0xe6055400 0 0x50>;
441 gpio-ranges = <&pfc 0 192 32>;
452 reg = <0 0xe6055800 0 0x50>;
456 gpio-ranges = <&pfc 0 224 4>;
466 reg = <0 0xe6060000 0 0x50c>;
472 reg = <0 0xe60f0000 0 0x1004>;
485 reg = <0 0xe6130000 0 0x1004>;
504 reg = <0 0xe6140000 0 0x1004>;
523 reg = <0 0xe6148000 0 0x1004>;
541 reg = <0 0xe6150000 0 0x1000>;
545 #power-domain-cells = <0>;
551 reg = <0 0xe6160000 0 0x0200>;
556 reg = <0 0xe6180000 0 0x0400>;
562 reg = <0 0xe6198000 0 0x100>,
563 <0 0xe61a0000 0 0x100>,
564 <0 0xe61a8000 0 0x100>;
578 reg = <0 0xe61c0000 0 0x200>;
579 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
592 reg = <0 0xe61e0000 0 0x30>;
606 reg = <0 0xe6fc0000 0 0x30>;
621 reg = <0 0xe6fd0000 0 0x30>;
636 reg = <0 0xe6fe0000 0 0x30>;
650 reg = <0 0xffc00000 0 0x30>;
664 #size-cells = <0>;
667 reg = <0 0xe6500000 0 0x40>;
672 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
673 <&dmac2 0x91>, <&dmac2 0x90>;
681 #size-cells = <0>;
684 reg = <0 0xe6508000 0 0x40>;
689 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
690 <&dmac2 0x93>, <&dmac2 0x92>;
698 #size-cells = <0>;
701 reg = <0 0xe6510000 0 0x40>;
706 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
707 <&dmac2 0x95>, <&dmac2 0x94>;
715 #size-cells = <0>;
718 reg = <0 0xe66d0000 0 0x40>;
723 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
731 #size-cells = <0>;
734 reg = <0 0xe66d8000 0 0x40>;
739 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
747 #size-cells = <0>;
750 reg = <0 0xe66e0000 0 0x40>;
755 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
763 #size-cells = <0>;
766 reg = <0 0xe66e8000 0 0x40>;
771 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
779 #size-cells = <0>;
783 reg = <0 0xe60b0000 0 0x425>;
788 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
797 reg = <0 0xe6540000 0 0x60>;
803 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
804 <&dmac2 0x31>, <&dmac2 0x30>;
815 reg = <0 0xe6550000 0 0x60>;
821 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
822 <&dmac2 0x33>, <&dmac2 0x32>;
833 reg = <0 0xe6560000 0 0x60>;
839 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
840 <&dmac2 0x35>, <&dmac2 0x34>;
851 reg = <0 0xe66a0000 0 0x60>;
857 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
868 reg = <0 0xe66b0000 0 0x60>;
874 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
884 reg = <0 0xe6590000 0 0x200>;
887 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
888 <&usb_dmac1 0>, <&usb_dmac1 1>;
901 reg = <0 0xe6590630 0 0x02>;
906 #clock-cells = <0>;
916 reg = <0 0xe65a0000 0 0x100>;
930 reg = <0 0xe65b0000 0 0x100>;
944 reg = <0 0xe65ee000 0 0x90>;
950 #phy-cells = <0>;
957 reg = <0 0xe6700000 0 0x10000>;
986 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
999 reg = <0 0xe7300000 0 0x10000>;
1028 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1041 reg = <0 0xe7310000 0 0x10000>;
1082 reg = <0 0xe6740000 0 0x1000>;
1083 renesas,ipmmu-main = <&ipmmu_mm 0>;
1090 reg = <0 0xe7740000 0 0x1000>;
1098 reg = <0 0xe6570000 0 0x1000>;
1106 reg = <0 0xe67b0000 0 0x1000>;
1115 reg = <0 0xec670000 0 0x1000>;
1123 reg = <0 0xfd800000 0 0x1000>;
1131 reg = <0 0xfd950000 0 0x1000>;
1139 reg = <0 0xfd960000 0 0x1000>;
1147 reg = <0 0xfd970000 0 0x1000>;
1155 reg = <0 0xfe6b0000 0 0x1000>;
1163 reg = <0 0xfe6f0000 0 0x1000>;
1171 reg = <0 0xfebd0000 0 0x1000>;
1179 reg = <0 0xfebe0000 0 0x1000>;
1187 reg = <0 0xfe990000 0 0x1000>;
1195 reg = <0 0xfe980000 0 0x1000>;
1204 reg = <0 0xe6800000 0 0x800>;
1242 rx-internal-delay-ps = <0>;
1243 tx-internal-delay-ps = <0>;
1246 #size-cells = <0>;
1253 reg = <0 0xe6c30000 0 0x1000>;
1269 reg = <0 0xe6c38000 0 0x1000>;
1285 reg = <0 0xe66c0000 0 0x8000>;
1310 reg = <0 0xe6e30000 0 0x8>;
1320 reg = <0 0xe6e31000 0 0x8>;
1330 reg = <0 0xe6e32000 0 0x8>;
1340 reg = <0 0xe6e33000 0 0x8>;
1350 reg = <0 0xe6e34000 0 0x8>;
1360 reg = <0 0xe6e35000 0 0x8>;
1370 reg = <0 0xe6e36000 0 0x8>;
1381 reg = <0 0xe6e60000 0 0x40>;
1387 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1388 <&dmac2 0x51>, <&dmac2 0x50>;
1398 reg = <0 0xe6e68000 0 0x40>;
1404 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1405 <&dmac2 0x53>, <&dmac2 0x52>;
1415 reg = <0 0xe6e88000 0 0x40>;
1421 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1422 <&dmac2 0x13>, <&dmac2 0x12>;
1432 reg = <0 0xe6c50000 0 0x40>;
1438 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1448 reg = <0 0xe6c40000 0 0x40>;
1454 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1464 reg = <0 0xe6f30000 0 0x40>;
1470 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1471 <&dmac2 0x5b>, <&dmac2 0x5a>;
1481 reg = <0 0xe6e90000 0 0x0064>;
1484 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1485 <&dmac2 0x41>, <&dmac2 0x40>;
1490 #size-cells = <0>;
1497 reg = <0 0xe6ea0000 0 0x0064>;
1500 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1501 <&dmac2 0x43>, <&dmac2 0x42>;
1506 #size-cells = <0>;
1513 reg = <0 0xe6c00000 0 0x0064>;
1516 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1521 #size-cells = <0>;
1528 reg = <0 0xe6c10000 0 0x0064>;
1531 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1536 #size-cells = <0>;
1542 reg = <0 0xe6ef0000 0 0x1000>;
1547 renesas,id = <0>;
1552 #size-cells = <0>;
1556 #size-cells = <0>;
1560 vin0csi20: endpoint@0 {
1561 reg = <0>;
1574 reg = <0 0xe6ef1000 0 0x1000>;
1584 #size-cells = <0>;
1588 #size-cells = <0>;
1592 vin1csi20: endpoint@0 {
1593 reg = <0>;
1606 reg = <0 0xe6ef2000 0 0x1000>;
1616 #size-cells = <0>;
1620 #size-cells = <0>;
1624 vin2csi20: endpoint@0 {
1625 reg = <0>;
1638 reg = <0 0xe6ef3000 0 0x1000>;
1648 #size-cells = <0>;
1652 #size-cells = <0>;
1656 vin3csi20: endpoint@0 {
1657 reg = <0>;
1670 reg = <0 0xe6ef4000 0 0x1000>;
1680 #size-cells = <0>;
1684 #size-cells = <0>;
1688 vin4csi20: endpoint@0 {
1689 reg = <0>;
1698 reg = <0 0xe6ef5000 0 0x1000>;
1708 #size-cells = <0>;
1712 #size-cells = <0>;
1716 vin5csi20: endpoint@0 {
1717 reg = <0>;
1726 reg = <0 0xe6ef6000 0 0x1000>;
1736 #size-cells = <0>;
1740 #size-cells = <0>;
1744 vin6csi20: endpoint@0 {
1745 reg = <0>;
1754 reg = <0 0xe6ef7000 0 0x1000>;
1764 #size-cells = <0>;
1768 #size-cells = <0>;
1772 vin7csi20: endpoint@0 {
1773 reg = <0>;
1784 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1790 * clkout : #clock-cells = <0>; <&rcar_sound>;
1794 reg = <0 0xec500000 0 0x1000>, /* SCU */
1795 <0 0xec5a0000 0 0x100>, /* ADG */
1796 <0 0xec540000 0 0x1000>, /* SSIU */
1797 <0 0xec541000 0 0x280>, /* SSI */
1798 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1821 "ssi.1", "ssi.0",
1824 "src.1", "src.0",
1825 "mix.1", "mix.0",
1826 "ctu.1", "ctu.0",
1827 "dvc.0", "dvc.1",
1839 "ssi.1", "ssi.0";
1843 dvc0: dvc-0 {
1844 dmas = <&audma1 0xbc>;
1848 dmas = <&audma1 0xbe>;
1854 mix0: mix-0 { };
1859 ctu00: ctu-0 { };
1870 src0: src-0 {
1872 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1877 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1882 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1887 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1892 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1897 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1902 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1907 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1912 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1917 dmas = <&audma0 0x97>, <&audma1 0xba>;
1923 ssiu00: ssiu-0 {
1924 dmas = <&audma0 0x15>, <&audma1 0x16>;
1928 dmas = <&audma0 0x35>, <&audma1 0x36>;
1932 dmas = <&audma0 0x37>, <&audma1 0x38>;
1936 dmas = <&audma0 0x47>, <&audma1 0x48>;
1940 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1944 dmas = <&audma0 0x43>, <&audma1 0x44>;
1948 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1952 dmas = <&audma0 0x53>, <&audma1 0x54>;
1956 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1960 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1964 dmas = <&audma0 0x57>, <&audma1 0x58>;
1968 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1972 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1976 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1980 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1984 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1988 dmas = <&audma0 0x63>, <&audma1 0x64>;
1992 dmas = <&audma0 0x67>, <&audma1 0x68>;
1996 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
2000 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
2004 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
2008 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
2012 dmas = <&audma0 0xED>, <&audma1 0xEE>;
2016 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
2020 dmas = <&audma0 0x6f>, <&audma1 0x70>;
2024 dmas = <&audma0 0x21>, <&audma1 0x22>;
2028 dmas = <&audma0 0x23>, <&audma1 0x24>;
2032 dmas = <&audma0 0x25>, <&audma1 0x26>;
2036 dmas = <&audma0 0x27>, <&audma1 0x28>;
2040 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2044 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2048 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2052 dmas = <&audma0 0x71>, <&audma1 0x72>;
2056 dmas = <&audma0 0x17>, <&audma1 0x18>;
2060 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2064 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2068 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2072 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2076 dmas = <&audma0 0x31>, <&audma1 0x32>;
2080 dmas = <&audma0 0x33>, <&audma1 0x34>;
2084 dmas = <&audma0 0x73>, <&audma1 0x74>;
2088 dmas = <&audma0 0x75>, <&audma1 0x76>;
2092 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2096 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2100 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2104 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2108 dmas = <&audma0 0x81>, <&audma1 0x82>;
2112 dmas = <&audma0 0x83>, <&audma1 0x84>;
2116 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2120 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2124 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2128 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2134 ssi0: ssi-0 {
2136 dmas = <&audma0 0x01>, <&audma1 0x02>;
2141 dmas = <&audma0 0x03>, <&audma1 0x04>;
2146 dmas = <&audma0 0x05>, <&audma1 0x06>;
2151 dmas = <&audma0 0x07>, <&audma1 0x08>;
2156 dmas = <&audma0 0x09>, <&audma1 0x0a>;
2161 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
2166 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
2171 dmas = <&audma0 0x0f>, <&audma1 0x10>;
2176 dmas = <&audma0 0x11>, <&audma1 0x12>;
2181 dmas = <&audma0 0x13>, <&audma1 0x14>;
2190 reg = <0 0xec700000 0 0x10000>;
2219 iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>,
2232 reg = <0 0xec720000 0 0x10000>;
2274 reg = <0 0xee000000 0 0xc00>;
2285 reg = <0 0xee020000 0 0x400>;
2295 reg = <0 0xee080000 0 0x100>;
2307 reg = <0 0xee0a0000 0 0x100>;
2319 reg = <0 0xee080100 0 0x100>;
2332 reg = <0 0xee0a0100 0 0x100>;
2346 reg = <0 0xee080200 0 0x700>;
2358 reg = <0 0xee0a0200 0 0x700>;
2369 reg = <0 0xee100000 0 0x2000>;
2383 reg = <0 0xee120000 0 0x2000>;
2397 reg = <0 0xee140000 0 0x2000>;
2411 reg = <0 0xee160000 0 0x2000>;
2425 reg = <0 0xee200000 0 0x200>,
2426 <0 0x08000000 0 0x4000000>,
2427 <0 0xee208000 0 0x100>;
2434 #size-cells = <0>;
2441 reg = <0 0xee300000 0 0x200000>;
2453 #address-cells = <0>;
2455 reg = <0x0 0xf1010000 0 0x1000>,
2456 <0x0 0xf1020000 0 0x20000>,
2457 <0x0 0xf1040000 0 0x20000>,
2458 <0x0 0xf1060000 0 0x20000>;
2470 reg = <0 0xfe000000 0 0x80000>;
2473 bus-range = <0x00 0xff>;
2475 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2476 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2477 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2478 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2480 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2485 interrupt-map-mask = <0 0 0 0>;
2486 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2491 iommu-map = <0 &ipmmu_hc 0 1>;
2492 iommu-map-mask = <0>;
2499 reg = <0 0xee800000 0 0x80000>;
2502 bus-range = <0x00 0xff>;
2504 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2505 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2506 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2507 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2509 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2514 interrupt-map-mask = <0 0 0 0>;
2515 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2520 iommu-map = <0 &ipmmu_hc 1 1>;
2521 iommu-map-mask = <0>;
2528 reg = <0x0 0xfe000000 0 0x80000>,
2529 <0x0 0xfe100000 0 0x100000>,
2530 <0x0 0xfe200000 0 0x200000>,
2531 <0x0 0x30000000 0 0x8000000>,
2532 <0x0 0x38000000 0 0x8000000>;
2547 reg = <0x0 0xee800000 0 0x80000>,
2548 <0x0 0xee900000 0 0x100000>,
2549 <0x0 0xeea00000 0 0x200000>,
2550 <0x0 0xc0000000 0 0x8000000>,
2551 <0x0 0xc8000000 0 0x8000000>;
2565 reg = <0 0xfe920000 0 0x8000>;
2576 reg = <0 0xfe960000 0 0x8000>;
2587 reg = <0 0xfea20000 0 0x5000>;
2598 reg = <0 0xfea28000 0 0x5000>;
2609 reg = <0 0xfe9a0000 0 0x8000>;
2620 reg = <0 0xfe9b0000 0 0x8000>;
2631 reg = <0 0xfe940000 0 0x2400>;
2641 reg = <0 0xfe944000 0 0x2400>;
2651 reg = <0 0xfe950000 0 0x200>;
2655 iommus = <&ipmmu_vp0 0>;
2660 reg = <0 0xfe951000 0 0x200>;
2669 reg = <0 0xfe96f000 0 0x200>;
2678 reg = <0 0xfe92f000 0 0x200>;
2687 reg = <0 0xfe9af000 0 0x200>;
2696 reg = <0 0xfe9bf000 0 0x200>;
2705 reg = <0 0xfea27000 0 0x200>;
2714 reg = <0 0xfea2f000 0 0x200>;
2723 reg = <0 0xfea80000 0 0x10000>;
2732 #size-cells = <0>;
2734 port@0 {
2735 reg = <0>;
2740 #size-cells = <0>;
2744 csi20vin0: endpoint@0 {
2745 reg = <0>;
2782 reg = <0 0xfeaa0000 0 0x10000>;
2791 #size-cells = <0>;
2793 port@0 {
2794 reg = <0>;
2799 #size-cells = <0>;
2803 csi40vin0: endpoint@0 {
2804 reg = <0>;
2826 reg = <0 0xfead0000 0 0x10000>;
2837 #size-cells = <0>;
2839 port@0 {
2840 reg = <0>;
2857 reg = <0 0xfeb00000 0 0x80000>;
2864 clock-names = "du.0", "du.1", "du.3";
2866 reset-names = "du.0", "du.3";
2869 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
2873 #size-cells = <0>;
2875 port@0 {
2876 reg = <0>;
2895 reg = <0 0xfeb90000 0 0x14>;
2903 #size-cells = <0>;
2905 port@0 {
2906 reg = <0>;
2919 reg = <0 0xfff00044 0 4>;
2927 thermal-sensors = <&tsc 0>;
2977 cooling-device = <&a57_0 0 2>;
2983 cooling-device = <&a53_0 0 2>;
3002 #clock-cells = <0>;
3003 clock-frequency = <0>;
3008 #clock-cells = <0>;
3009 clock-frequency = <0>;