Lines Matching +full:0 +full:xe65ee000
19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
45 clock-frequency = <0>;
48 cluster0_opp: opp-table-0 {
93 #size-cells = <0>;
127 a57_0: cpu@0 {
129 reg = <0x0>;
144 reg = <0x1>;
158 reg = <0x2>;
172 reg = <0x3>;
186 reg = <0x100>;
201 reg = <0x101>;
214 reg = <0x102>;
227 reg = <0x103>;
238 L2_CA57: cache-controller-0 {
255 CPU_SLEEP_0: cpu-sleep-0 {
257 arm,psci-suspend-param = <0x0010000>;
266 arm,psci-suspend-param = <0x0010000>;
277 #clock-cells = <0>;
279 clock-frequency = <0>;
285 #clock-cells = <0>;
287 clock-frequency = <0>;
294 #clock-cells = <0>;
295 clock-frequency = <0>;
324 #clock-cells = <0>;
325 clock-frequency = <0>;
340 reg = <0 0xe6020000 0 0x0c>;
351 reg = <0 0xe6050000 0 0x50>;
355 gpio-ranges = <&pfc 0 0 16>;
366 reg = <0 0xe6051000 0 0x50>;
370 gpio-ranges = <&pfc 0 32 29>;
381 reg = <0 0xe6052000 0 0x50>;
385 gpio-ranges = <&pfc 0 64 15>;
396 reg = <0 0xe6053000 0 0x50>;
400 gpio-ranges = <&pfc 0 96 16>;
411 reg = <0 0xe6054000 0 0x50>;
415 gpio-ranges = <&pfc 0 128 18>;
426 reg = <0 0xe6055000 0 0x50>;
430 gpio-ranges = <&pfc 0 160 26>;
441 reg = <0 0xe6055400 0 0x50>;
445 gpio-ranges = <&pfc 0 192 32>;
456 reg = <0 0xe6055800 0 0x50>;
460 gpio-ranges = <&pfc 0 224 4>;
470 reg = <0 0xe6060000 0 0x50c>;
477 reg = <0 0xe60f0000 0 0x1004>;
490 reg = <0 0xe6130000 0 0x1004>;
509 reg = <0 0xe6140000 0 0x1004>;
528 reg = <0 0xe6148000 0 0x1004>;
546 reg = <0 0xe6150000 0 0x1000>;
550 #power-domain-cells = <0>;
557 reg = <0 0xe6160000 0 0x0200>;
563 reg = <0 0xe6180000 0 0x0400>;
569 reg = <0 0xe6198000 0 0x100>,
570 <0 0xe61a0000 0 0x100>,
571 <0 0xe61a8000 0 0x100>;
585 reg = <0 0xe61c0000 0 0x200>;
586 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
599 reg = <0 0xe61e0000 0 0x30>;
613 reg = <0 0xe6fc0000 0 0x30>;
628 reg = <0 0xe6fd0000 0 0x30>;
643 reg = <0 0xe6fe0000 0 0x30>;
657 reg = <0 0xffc00000 0 0x30>;
671 #size-cells = <0>;
674 reg = <0 0xe6500000 0 0x40>;
679 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
680 <&dmac2 0x91>, <&dmac2 0x90>;
688 #size-cells = <0>;
691 reg = <0 0xe6508000 0 0x40>;
696 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
697 <&dmac2 0x93>, <&dmac2 0x92>;
705 #size-cells = <0>;
708 reg = <0 0xe6510000 0 0x40>;
713 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
714 <&dmac2 0x95>, <&dmac2 0x94>;
722 #size-cells = <0>;
725 reg = <0 0xe66d0000 0 0x40>;
730 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
738 #size-cells = <0>;
741 reg = <0 0xe66d8000 0 0x40>;
746 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
754 #size-cells = <0>;
757 reg = <0 0xe66e0000 0 0x40>;
762 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
770 #size-cells = <0>;
773 reg = <0 0xe66e8000 0 0x40>;
778 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
786 #size-cells = <0>;
790 reg = <0 0xe60b0000 0 0x425>;
795 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
804 reg = <0 0xe6540000 0 0x60>;
810 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
811 <&dmac2 0x31>, <&dmac2 0x30>;
822 reg = <0 0xe6550000 0 0x60>;
828 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
829 <&dmac2 0x33>, <&dmac2 0x32>;
840 reg = <0 0xe6560000 0 0x60>;
846 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
847 <&dmac2 0x35>, <&dmac2 0x34>;
858 reg = <0 0xe66a0000 0 0x60>;
864 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
875 reg = <0 0xe66b0000 0 0x60>;
881 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
891 reg = <0 0xe6590000 0 0x200>;
894 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
895 <&usb_dmac1 0>, <&usb_dmac1 1>;
908 reg = <0 0xe6590630 0 0x02>;
913 #clock-cells = <0>;
923 reg = <0 0xe65a0000 0 0x100>;
937 reg = <0 0xe65b0000 0 0x100>;
951 reg = <0 0xe65ee000 0 0x90>;
957 #phy-cells = <0>;
964 reg = <0 0xe6700000 0 0x10000>;
993 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
1006 reg = <0 0xe7300000 0 0x10000>;
1035 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1048 reg = <0 0xe7310000 0 0x10000>;
1089 reg = <0 0xe6740000 0 0x1000>;
1090 renesas,ipmmu-main = <&ipmmu_mm 0>;
1097 reg = <0 0xe7740000 0 0x1000>;
1105 reg = <0 0xe6570000 0 0x1000>;
1113 reg = <0 0xe67b0000 0 0x1000>;
1122 reg = <0 0xec670000 0 0x1000>;
1130 reg = <0 0xfd800000 0 0x1000>;
1138 reg = <0 0xfd950000 0 0x1000>;
1146 reg = <0 0xfd960000 0 0x1000>;
1154 reg = <0 0xfd970000 0 0x1000>;
1162 reg = <0 0xfe6b0000 0 0x1000>;
1170 reg = <0 0xfe6f0000 0 0x1000>;
1178 reg = <0 0xfebd0000 0 0x1000>;
1186 reg = <0 0xfebe0000 0 0x1000>;
1194 reg = <0 0xfe990000 0 0x1000>;
1202 reg = <0 0xfe980000 0 0x1000>;
1211 reg = <0 0xe6800000 0 0x800>;
1249 rx-internal-delay-ps = <0>;
1250 tx-internal-delay-ps = <0>;
1253 #size-cells = <0>;
1260 reg = <0 0xe6c30000 0 0x1000>;
1276 reg = <0 0xe6c38000 0 0x1000>;
1292 reg = <0 0xe66c0000 0 0x8000>;
1317 reg = <0 0xe6e30000 0 0x8>;
1327 reg = <0 0xe6e31000 0 0x8>;
1337 reg = <0 0xe6e32000 0 0x8>;
1347 reg = <0 0xe6e33000 0 0x8>;
1357 reg = <0 0xe6e34000 0 0x8>;
1367 reg = <0 0xe6e35000 0 0x8>;
1377 reg = <0 0xe6e36000 0 0x8>;
1388 reg = <0 0xe6e60000 0 0x40>;
1394 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1395 <&dmac2 0x51>, <&dmac2 0x50>;
1405 reg = <0 0xe6e68000 0 0x40>;
1411 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1412 <&dmac2 0x53>, <&dmac2 0x52>;
1422 reg = <0 0xe6e88000 0 0x40>;
1428 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1429 <&dmac2 0x13>, <&dmac2 0x12>;
1439 reg = <0 0xe6c50000 0 0x40>;
1445 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1455 reg = <0 0xe6c40000 0 0x40>;
1461 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1471 reg = <0 0xe6f30000 0 0x40>;
1477 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1478 <&dmac2 0x5b>, <&dmac2 0x5a>;
1488 reg = <0 0xe6e90000 0 0x0064>;
1491 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1492 <&dmac2 0x41>, <&dmac2 0x40>;
1497 #size-cells = <0>;
1504 reg = <0 0xe6ea0000 0 0x0064>;
1507 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1508 <&dmac2 0x43>, <&dmac2 0x42>;
1513 #size-cells = <0>;
1520 reg = <0 0xe6c00000 0 0x0064>;
1523 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1528 #size-cells = <0>;
1535 reg = <0 0xe6c10000 0 0x0064>;
1538 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1543 #size-cells = <0>;
1549 reg = <0 0xe6ef0000 0 0x1000>;
1554 renesas,id = <0>;
1559 #size-cells = <0>;
1563 #size-cells = <0>;
1567 vin0csi20: endpoint@0 {
1568 reg = <0>;
1581 reg = <0 0xe6ef1000 0 0x1000>;
1591 #size-cells = <0>;
1595 #size-cells = <0>;
1599 vin1csi20: endpoint@0 {
1600 reg = <0>;
1613 reg = <0 0xe6ef2000 0 0x1000>;
1623 #size-cells = <0>;
1627 #size-cells = <0>;
1631 vin2csi20: endpoint@0 {
1632 reg = <0>;
1645 reg = <0 0xe6ef3000 0 0x1000>;
1655 #size-cells = <0>;
1659 #size-cells = <0>;
1663 vin3csi20: endpoint@0 {
1664 reg = <0>;
1677 reg = <0 0xe6ef4000 0 0x1000>;
1687 #size-cells = <0>;
1691 #size-cells = <0>;
1695 vin4csi20: endpoint@0 {
1696 reg = <0>;
1705 reg = <0 0xe6ef5000 0 0x1000>;
1715 #size-cells = <0>;
1719 #size-cells = <0>;
1723 vin5csi20: endpoint@0 {
1724 reg = <0>;
1733 reg = <0 0xe6ef6000 0 0x1000>;
1743 #size-cells = <0>;
1747 #size-cells = <0>;
1751 vin6csi20: endpoint@0 {
1752 reg = <0>;
1761 reg = <0 0xe6ef7000 0 0x1000>;
1771 #size-cells = <0>;
1775 #size-cells = <0>;
1779 vin7csi20: endpoint@0 {
1780 reg = <0>;
1791 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1797 * clkout : #clock-cells = <0>; <&rcar_sound>;
1801 reg = <0 0xec500000 0 0x1000>, /* SCU */
1802 <0 0xec5a0000 0 0x100>, /* ADG */
1803 <0 0xec540000 0 0x1000>, /* SSIU */
1804 <0 0xec541000 0 0x280>, /* SSI */
1805 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1828 "ssi.1", "ssi.0",
1831 "src.1", "src.0",
1832 "mix.1", "mix.0",
1833 "ctu.1", "ctu.0",
1834 "dvc.0", "dvc.1",
1846 "ssi.1", "ssi.0";
1850 dvc0: dvc-0 {
1851 dmas = <&audma1 0xbc>;
1855 dmas = <&audma1 0xbe>;
1861 mix0: mix-0 { };
1866 ctu00: ctu-0 { };
1877 src0: src-0 {
1879 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1884 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1889 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1894 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1899 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1904 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1909 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1914 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1919 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1924 dmas = <&audma0 0x97>, <&audma1 0xba>;
1930 ssiu00: ssiu-0 {
1931 dmas = <&audma0 0x15>, <&audma1 0x16>;
1935 dmas = <&audma0 0x35>, <&audma1 0x36>;
1939 dmas = <&audma0 0x37>, <&audma1 0x38>;
1943 dmas = <&audma0 0x47>, <&audma1 0x48>;
1947 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1951 dmas = <&audma0 0x43>, <&audma1 0x44>;
1955 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1959 dmas = <&audma0 0x53>, <&audma1 0x54>;
1963 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1967 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1971 dmas = <&audma0 0x57>, <&audma1 0x58>;
1975 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1979 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1983 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1987 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1991 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1995 dmas = <&audma0 0x63>, <&audma1 0x64>;
1999 dmas = <&audma0 0x67>, <&audma1 0x68>;
2003 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
2007 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
2011 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
2015 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
2019 dmas = <&audma0 0xED>, <&audma1 0xEE>;
2023 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
2027 dmas = <&audma0 0x6f>, <&audma1 0x70>;
2031 dmas = <&audma0 0x21>, <&audma1 0x22>;
2035 dmas = <&audma0 0x23>, <&audma1 0x24>;
2039 dmas = <&audma0 0x25>, <&audma1 0x26>;
2043 dmas = <&audma0 0x27>, <&audma1 0x28>;
2047 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2051 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2055 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2059 dmas = <&audma0 0x71>, <&audma1 0x72>;
2063 dmas = <&audma0 0x17>, <&audma1 0x18>;
2067 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2071 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2075 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2079 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2083 dmas = <&audma0 0x31>, <&audma1 0x32>;
2087 dmas = <&audma0 0x33>, <&audma1 0x34>;
2091 dmas = <&audma0 0x73>, <&audma1 0x74>;
2095 dmas = <&audma0 0x75>, <&audma1 0x76>;
2099 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2103 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2107 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2111 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2115 dmas = <&audma0 0x81>, <&audma1 0x82>;
2119 dmas = <&audma0 0x83>, <&audma1 0x84>;
2123 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2127 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2131 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2135 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2141 ssi0: ssi-0 {
2143 dmas = <&audma0 0x01>, <&audma1 0x02>;
2148 dmas = <&audma0 0x03>, <&audma1 0x04>;
2153 dmas = <&audma0 0x05>, <&audma1 0x06>;
2158 dmas = <&audma0 0x07>, <&audma1 0x08>;
2163 dmas = <&audma0 0x09>, <&audma1 0x0a>;
2168 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
2173 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
2178 dmas = <&audma0 0x0f>, <&audma1 0x10>;
2183 dmas = <&audma0 0x11>, <&audma1 0x12>;
2188 dmas = <&audma0 0x13>, <&audma1 0x14>;
2197 reg = <0 0xec700000 0 0x10000>;
2226 iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>,
2239 reg = <0 0xec720000 0 0x10000>;
2281 reg = <0 0xee000000 0 0xc00>;
2292 reg = <0 0xee020000 0 0x400>;
2302 reg = <0 0xee080000 0 0x100>;
2314 reg = <0 0xee0a0000 0 0x100>;
2326 reg = <0 0xee080100 0 0x100>;
2339 reg = <0 0xee0a0100 0 0x100>;
2353 reg = <0 0xee080200 0 0x700>;
2365 reg = <0 0xee0a0200 0 0x700>;
2376 reg = <0 0xee100000 0 0x2000>;
2390 reg = <0 0xee120000 0 0x2000>;
2404 reg = <0 0xee140000 0 0x2000>;
2418 reg = <0 0xee160000 0 0x2000>;
2432 reg = <0 0xee200000 0 0x200>,
2433 <0 0x08000000 0 0x4000000>,
2434 <0 0xee208000 0 0x100>;
2441 #size-cells = <0>;
2448 reg = <0 0xee300000 0 0x200000>;
2460 #address-cells = <0>;
2462 reg = <0x0 0xf1010000 0 0x1000>,
2463 <0x0 0xf1020000 0 0x20000>,
2464 <0x0 0xf1040000 0 0x20000>,
2465 <0x0 0xf1060000 0 0x20000>;
2477 reg = <0 0xfe000000 0 0x80000>;
2480 bus-range = <0x00 0xff>;
2482 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2483 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2484 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2485 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2487 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2492 interrupt-map-mask = <0 0 0 0>;
2493 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2498 iommu-map = <0 &ipmmu_hc 0 1>;
2499 iommu-map-mask = <0>;
2506 reg = <0 0xee800000 0 0x80000>;
2509 bus-range = <0x00 0xff>;
2511 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2512 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2513 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2514 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2516 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2521 interrupt-map-mask = <0 0 0 0>;
2522 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2527 iommu-map = <0 &ipmmu_hc 1 1>;
2528 iommu-map-mask = <0>;
2535 reg = <0x0 0xfe000000 0 0x80000>,
2536 <0x0 0xfe100000 0 0x100000>,
2537 <0x0 0xfe200000 0 0x200000>,
2538 <0x0 0x30000000 0 0x8000000>,
2539 <0x0 0x38000000 0 0x8000000>;
2554 reg = <0x0 0xee800000 0 0x80000>,
2555 <0x0 0xee900000 0 0x100000>,
2556 <0x0 0xeea00000 0 0x200000>,
2557 <0x0 0xc0000000 0 0x8000000>,
2558 <0x0 0xc8000000 0 0x8000000>;
2572 reg = <0 0xfe920000 0 0x8000>;
2583 reg = <0 0xfe960000 0 0x8000>;
2594 reg = <0 0xfea20000 0 0x5000>;
2605 reg = <0 0xfea28000 0 0x5000>;
2616 reg = <0 0xfe9a0000 0 0x8000>;
2627 reg = <0 0xfe9b0000 0 0x8000>;
2638 reg = <0 0xfe940000 0 0x2400>;
2648 reg = <0 0xfe944000 0 0x2400>;
2658 reg = <0 0xfe950000 0 0x200>;
2662 iommus = <&ipmmu_vp0 0>;
2667 reg = <0 0xfe951000 0 0x200>;
2676 reg = <0 0xfe96f000 0 0x200>;
2685 reg = <0 0xfe92f000 0 0x200>;
2694 reg = <0 0xfe9af000 0 0x200>;
2703 reg = <0 0xfe9bf000 0 0x200>;
2712 reg = <0 0xfea27000 0 0x200>;
2721 reg = <0 0xfea2f000 0 0x200>;
2730 reg = <0 0xfea80000 0 0x10000>;
2739 #size-cells = <0>;
2741 port@0 {
2742 reg = <0>;
2747 #size-cells = <0>;
2751 csi20vin0: endpoint@0 {
2752 reg = <0>;
2789 reg = <0 0xfeaa0000 0 0x10000>;
2798 #size-cells = <0>;
2800 port@0 {
2801 reg = <0>;
2806 #size-cells = <0>;
2810 csi40vin0: endpoint@0 {
2811 reg = <0>;
2833 reg = <0 0xfead0000 0 0x10000>;
2844 #size-cells = <0>;
2846 port@0 {
2847 reg = <0>;
2864 reg = <0 0xfeb00000 0 0x80000>;
2871 clock-names = "du.0", "du.1", "du.3";
2873 reset-names = "du.0", "du.3";
2876 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
2880 #size-cells = <0>;
2882 port@0 {
2883 reg = <0>;
2902 reg = <0 0xfeb90000 0 0x14>;
2910 #size-cells = <0>;
2912 port@0 {
2913 reg = <0>;
2926 reg = <0 0xfff00044 0 4>;
2935 thermal-sensors = <&tsc 0>;
2985 cooling-device = <&a57_0 0 2>;
2991 cooling-device = <&a53_0 0 2>;
3010 #clock-cells = <0>;
3011 clock-frequency = <0>;
3016 #clock-cells = <0>;
3017 clock-frequency = <0>;