Lines Matching +full:- +full:cpg
1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a774e1-cpg-mssr.h>
11 #include <dt-bindings/power/r8a774e1-sysc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <0>;
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <0>;
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <0>;
41 /* External CAN clock - to be overridden by boards that provide it */
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <0>;
48 cluster0_opp: opp-table-0 {
49 compatible = "operating-points-v2";
50 opp-shared;
52 opp-500000000 {
53 opp-hz = /bits/ 64 <500000000>;
54 opp-microvolt = <820000>;
55 clock-latency-ns = <300000>;
57 opp-1000000000 {
58 opp-hz = /bits/ 64 <1000000000>;
59 opp-microvolt = <820000>;
60 clock-latency-ns = <300000>;
62 opp-1500000000 {
63 opp-hz = /bits/ 64 <1500000000>;
64 opp-microvolt = <820000>;
65 clock-latency-ns = <300000>;
66 opp-suspend;
70 cluster1_opp: opp-table-1 {
71 compatible = "operating-points-v2";
72 opp-shared;
74 opp-800000000 {
75 opp-hz = /bits/ 64 <800000000>;
76 opp-microvolt = <820000>;
77 clock-latency-ns = <300000>;
79 opp-1000000000 {
80 opp-hz = /bits/ 64 <1000000000>;
81 opp-microvolt = <820000>;
82 clock-latency-ns = <300000>;
84 opp-1200000000 {
85 opp-hz = /bits/ 64 <1200000000>;
86 opp-microvolt = <820000>;
87 clock-latency-ns = <300000>;
92 #address-cells = <1>;
93 #size-cells = <0>;
95 cpu-map {
128 compatible = "arm,cortex-a57";
131 power-domains = <&sysc R8A774E1_PD_CA57_CPU0>;
132 next-level-cache = <&L2_CA57>;
133 enable-method = "psci";
134 cpu-idle-states = <&CPU_SLEEP_0>;
135 dynamic-power-coefficient = <854>;
136 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
137 operating-points-v2 = <&cluster0_opp>;
138 capacity-dmips-mhz = <1024>;
139 #cooling-cells = <2>;
143 compatible = "arm,cortex-a57";
146 power-domains = <&sysc R8A774E1_PD_CA57_CPU1>;
147 next-level-cache = <&L2_CA57>;
148 enable-method = "psci";
149 cpu-idle-states = <&CPU_SLEEP_0>;
150 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
151 operating-points-v2 = <&cluster0_opp>;
152 capacity-dmips-mhz = <1024>;
153 #cooling-cells = <2>;
157 compatible = "arm,cortex-a57";
160 power-domains = <&sysc R8A774E1_PD_CA57_CPU2>;
161 next-level-cache = <&L2_CA57>;
162 enable-method = "psci";
163 cpu-idle-states = <&CPU_SLEEP_0>;
164 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
165 operating-points-v2 = <&cluster0_opp>;
166 capacity-dmips-mhz = <1024>;
167 #cooling-cells = <2>;
171 compatible = "arm,cortex-a57";
174 power-domains = <&sysc R8A774E1_PD_CA57_CPU3>;
175 next-level-cache = <&L2_CA57>;
176 enable-method = "psci";
177 cpu-idle-states = <&CPU_SLEEP_0>;
178 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
179 operating-points-v2 = <&cluster0_opp>;
180 capacity-dmips-mhz = <1024>;
181 #cooling-cells = <2>;
185 compatible = "arm,cortex-a53";
188 power-domains = <&sysc R8A774E1_PD_CA53_CPU0>;
189 next-level-cache = <&L2_CA53>;
190 enable-method = "psci";
191 cpu-idle-states = <&CPU_SLEEP_1>;
192 #cooling-cells = <2>;
193 dynamic-power-coefficient = <277>;
194 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
195 operating-points-v2 = <&cluster1_opp>;
196 capacity-dmips-mhz = <535>;
200 compatible = "arm,cortex-a53";
203 power-domains = <&sysc R8A774E1_PD_CA53_CPU1>;
204 next-level-cache = <&L2_CA53>;
205 enable-method = "psci";
206 cpu-idle-states = <&CPU_SLEEP_1>;
207 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
208 operating-points-v2 = <&cluster1_opp>;
209 capacity-dmips-mhz = <535>;
213 compatible = "arm,cortex-a53";
216 power-domains = <&sysc R8A774E1_PD_CA53_CPU2>;
217 next-level-cache = <&L2_CA53>;
218 enable-method = "psci";
219 cpu-idle-states = <&CPU_SLEEP_1>;
220 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
221 operating-points-v2 = <&cluster1_opp>;
222 capacity-dmips-mhz = <535>;
226 compatible = "arm,cortex-a53";
229 power-domains = <&sysc R8A774E1_PD_CA53_CPU3>;
230 next-level-cache = <&L2_CA53>;
231 enable-method = "psci";
232 cpu-idle-states = <&CPU_SLEEP_1>;
233 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
234 operating-points-v2 = <&cluster1_opp>;
235 capacity-dmips-mhz = <535>;
238 L2_CA57: cache-controller-0 {
240 power-domains = <&sysc R8A774E1_PD_CA57_SCU>;
241 cache-unified;
242 cache-level = <2>;
245 L2_CA53: cache-controller-1 {
247 power-domains = <&sysc R8A774E1_PD_CA53_SCU>;
248 cache-unified;
249 cache-level = <2>;
252 idle-states {
253 entry-method = "psci";
255 CPU_SLEEP_0: cpu-sleep-0 {
256 compatible = "arm,idle-state";
257 arm,psci-suspend-param = <0x0010000>;
258 local-timer-stop;
259 entry-latency-us = <400>;
260 exit-latency-us = <500>;
261 min-residency-us = <4000>;
264 CPU_SLEEP_1: cpu-sleep-1 {
265 compatible = "arm,idle-state";
266 arm,psci-suspend-param = <0x0010000>;
267 local-timer-stop;
268 entry-latency-us = <700>;
269 exit-latency-us = <700>;
270 min-residency-us = <5000>;
276 compatible = "fixed-clock";
277 #clock-cells = <0>;
279 clock-frequency = <0>;
283 compatible = "fixed-clock";
284 #clock-cells = <0>;
286 clock-frequency = <0>;
289 /* External PCIe clock - can be overridden by the board */
291 compatible = "fixed-clock";
292 #clock-cells = <0>;
293 clock-frequency = <0>;
297 compatible = "arm,cortex-a53-pmu";
298 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
302 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
306 compatible = "arm,cortex-a57-pmu";
307 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
311 interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, <&a57_3>;
315 compatible = "arm,psci-1.0", "arm,psci-0.2";
319 /* External SCIF clock - to be overridden by boards that provide it */
321 compatible = "fixed-clock";
322 #clock-cells = <0>;
323 clock-frequency = <0>;
327 compatible = "simple-bus";
328 interrupt-parent = <&gic>;
329 #address-cells = <2>;
330 #size-cells = <2>;
334 compatible = "renesas,r8a774e1-wdt",
335 "renesas,rcar-gen3-wdt";
338 clocks = <&cpg CPG_MOD 402>;
339 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
340 resets = <&cpg 402>;
345 compatible = "renesas,gpio-r8a774e1",
346 "renesas,rcar-gen3-gpio";
349 #gpio-cells = <2>;
350 gpio-controller;
351 gpio-ranges = <&pfc 0 0 16>;
352 #interrupt-cells = <2>;
353 interrupt-controller;
354 clocks = <&cpg CPG_MOD 912>;
355 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
356 resets = <&cpg 912>;
360 compatible = "renesas,gpio-r8a774e1",
361 "renesas,rcar-gen3-gpio";
364 #gpio-cells = <2>;
365 gpio-controller;
366 gpio-ranges = <&pfc 0 32 29>;
367 #interrupt-cells = <2>;
368 interrupt-controller;
369 clocks = <&cpg CPG_MOD 911>;
370 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
371 resets = <&cpg 911>;
375 compatible = "renesas,gpio-r8a774e1",
376 "renesas,rcar-gen3-gpio";
379 #gpio-cells = <2>;
380 gpio-controller;
381 gpio-ranges = <&pfc 0 64 15>;
382 #interrupt-cells = <2>;
383 interrupt-controller;
384 clocks = <&cpg CPG_MOD 910>;
385 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
386 resets = <&cpg 910>;
390 compatible = "renesas,gpio-r8a774e1",
391 "renesas,rcar-gen3-gpio";
394 #gpio-cells = <2>;
395 gpio-controller;
396 gpio-ranges = <&pfc 0 96 16>;
397 #interrupt-cells = <2>;
398 interrupt-controller;
399 clocks = <&cpg CPG_MOD 909>;
400 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
401 resets = <&cpg 909>;
405 compatible = "renesas,gpio-r8a774e1",
406 "renesas,rcar-gen3-gpio";
409 #gpio-cells = <2>;
410 gpio-controller;
411 gpio-ranges = <&pfc 0 128 18>;
412 #interrupt-cells = <2>;
413 interrupt-controller;
414 clocks = <&cpg CPG_MOD 908>;
415 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
416 resets = <&cpg 908>;
420 compatible = "renesas,gpio-r8a774e1",
421 "renesas,rcar-gen3-gpio";
424 #gpio-cells = <2>;
425 gpio-controller;
426 gpio-ranges = <&pfc 0 160 26>;
427 #interrupt-cells = <2>;
428 interrupt-controller;
429 clocks = <&cpg CPG_MOD 907>;
430 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
431 resets = <&cpg 907>;
435 compatible = "renesas,gpio-r8a774e1",
436 "renesas,rcar-gen3-gpio";
439 #gpio-cells = <2>;
440 gpio-controller;
441 gpio-ranges = <&pfc 0 192 32>;
442 #interrupt-cells = <2>;
443 interrupt-controller;
444 clocks = <&cpg CPG_MOD 906>;
445 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
446 resets = <&cpg 906>;
450 compatible = "renesas,gpio-r8a774e1",
451 "renesas,rcar-gen3-gpio";
454 #gpio-cells = <2>;
455 gpio-controller;
456 gpio-ranges = <&pfc 0 224 4>;
457 #interrupt-cells = <2>;
458 interrupt-controller;
459 clocks = <&cpg CPG_MOD 905>;
460 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
461 resets = <&cpg 905>;
465 compatible = "renesas,pfc-r8a774e1";
470 compatible = "renesas,r8a774e1-cmt0",
471 "renesas,rcar-gen3-cmt0";
475 clocks = <&cpg CPG_MOD 303>;
476 clock-names = "fck";
477 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
478 resets = <&cpg 303>;
483 compatible = "renesas,r8a774e1-cmt1",
484 "renesas,rcar-gen3-cmt1";
494 clocks = <&cpg CPG_MOD 302>;
495 clock-names = "fck";
496 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
497 resets = <&cpg 302>;
502 compatible = "renesas,r8a774e1-cmt1",
503 "renesas,rcar-gen3-cmt1";
513 clocks = <&cpg CPG_MOD 301>;
514 clock-names = "fck";
515 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
516 resets = <&cpg 301>;
521 compatible = "renesas,r8a774e1-cmt1",
522 "renesas,rcar-gen3-cmt1";
532 clocks = <&cpg CPG_MOD 300>;
533 clock-names = "fck";
534 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
535 resets = <&cpg 300>;
539 cpg: clock-controller@e6150000 { label
540 compatible = "renesas,r8a774e1-cpg-mssr";
543 clock-names = "extal", "extalr";
544 #clock-cells = <2>;
545 #power-domain-cells = <0>;
546 #reset-cells = <1>;
549 rst: reset-controller@e6160000 {
550 compatible = "renesas,r8a774e1-rst";
554 sysc: system-controller@e6180000 {
555 compatible = "renesas,r8a774e1-sysc";
557 #power-domain-cells = <1>;
561 compatible = "renesas,r8a774e1-thermal";
568 clocks = <&cpg CPG_MOD 522>;
569 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
570 resets = <&cpg 522>;
571 #thermal-sensor-cells = <1>;
574 intc_ex: interrupt-controller@e61c0000 {
575 compatible = "renesas,intc-ex-r8a774e1", "renesas,irqc";
576 #interrupt-cells = <2>;
577 interrupt-controller;
585 clocks = <&cpg CPG_MOD 407>;
586 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
587 resets = <&cpg 407>;
591 compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
596 interrupt-names = "tuni0", "tuni1", "tuni2";
597 clocks = <&cpg CPG_MOD 125>;
598 clock-names = "fck";
599 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
600 resets = <&cpg 125>;
605 compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
611 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
612 clocks = <&cpg CPG_MOD 124>;
613 clock-names = "fck";
614 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
615 resets = <&cpg 124>;
620 compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
626 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
627 clocks = <&cpg CPG_MOD 123>;
628 clock-names = "fck";
629 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
630 resets = <&cpg 123>;
635 compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
640 interrupt-names = "tuni0", "tuni1", "tuni2";
641 clocks = <&cpg CPG_MOD 122>;
642 clock-names = "fck";
643 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
644 resets = <&cpg 122>;
649 compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
654 interrupt-names = "tuni0", "tuni1", "tuni2";
655 clocks = <&cpg CPG_MOD 121>;
656 clock-names = "fck";
657 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
658 resets = <&cpg 121>;
663 #address-cells = <1>;
664 #size-cells = <0>;
665 compatible = "renesas,i2c-r8a774e1",
666 "renesas,rcar-gen3-i2c";
669 clocks = <&cpg CPG_MOD 931>;
670 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
671 resets = <&cpg 931>;
674 dma-names = "tx", "rx", "tx", "rx";
675 i2c-scl-internal-delay-ns = <110>;
680 #address-cells = <1>;
681 #size-cells = <0>;
682 compatible = "renesas,i2c-r8a774e1",
683 "renesas,rcar-gen3-i2c";
686 clocks = <&cpg CPG_MOD 930>;
687 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
688 resets = <&cpg 930>;
691 dma-names = "tx", "rx", "tx", "rx";
692 i2c-scl-internal-delay-ns = <6>;
697 #address-cells = <1>;
698 #size-cells = <0>;
699 compatible = "renesas,i2c-r8a774e1",
700 "renesas,rcar-gen3-i2c";
703 clocks = <&cpg CPG_MOD 929>;
704 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
705 resets = <&cpg 929>;
708 dma-names = "tx", "rx", "tx", "rx";
709 i2c-scl-internal-delay-ns = <6>;
714 #address-cells = <1>;
715 #size-cells = <0>;
716 compatible = "renesas,i2c-r8a774e1",
717 "renesas,rcar-gen3-i2c";
720 clocks = <&cpg CPG_MOD 928>;
721 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
722 resets = <&cpg 928>;
724 dma-names = "tx", "rx";
725 i2c-scl-internal-delay-ns = <110>;
730 #address-cells = <1>;
731 #size-cells = <0>;
732 compatible = "renesas,i2c-r8a774e1",
733 "renesas,rcar-gen3-i2c";
736 clocks = <&cpg CPG_MOD 927>;
737 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
738 resets = <&cpg 927>;
740 dma-names = "tx", "rx";
741 i2c-scl-internal-delay-ns = <110>;
746 #address-cells = <1>;
747 #size-cells = <0>;
748 compatible = "renesas,i2c-r8a774e1",
749 "renesas,rcar-gen3-i2c";
752 clocks = <&cpg CPG_MOD 919>;
753 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
754 resets = <&cpg 919>;
756 dma-names = "tx", "rx";
757 i2c-scl-internal-delay-ns = <110>;
762 #address-cells = <1>;
763 #size-cells = <0>;
764 compatible = "renesas,i2c-r8a774e1",
765 "renesas,rcar-gen3-i2c";
768 clocks = <&cpg CPG_MOD 918>;
769 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
770 resets = <&cpg 918>;
772 dma-names = "tx", "rx";
773 i2c-scl-internal-delay-ns = <6>;
778 #address-cells = <1>;
779 #size-cells = <0>;
780 compatible = "renesas,iic-r8a774e1",
781 "renesas,rcar-gen3-iic",
782 "renesas,rmobile-iic";
785 clocks = <&cpg CPG_MOD 926>;
786 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
787 resets = <&cpg 926>;
789 dma-names = "tx", "rx";
794 compatible = "renesas,hscif-r8a774e1",
795 "renesas,rcar-gen3-hscif",
799 clocks = <&cpg CPG_MOD 520>,
800 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
802 clock-names = "fck", "brg_int", "scif_clk";
805 dma-names = "tx", "rx", "tx", "rx";
806 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
807 resets = <&cpg 520>;
812 compatible = "renesas,hscif-r8a774e1",
813 "renesas,rcar-gen3-hscif",
817 clocks = <&cpg CPG_MOD 519>,
818 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
820 clock-names = "fck", "brg_int", "scif_clk";
823 dma-names = "tx", "rx", "tx", "rx";
824 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
825 resets = <&cpg 519>;
830 compatible = "renesas,hscif-r8a774e1",
831 "renesas,rcar-gen3-hscif",
835 clocks = <&cpg CPG_MOD 518>,
836 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
838 clock-names = "fck", "brg_int", "scif_clk";
841 dma-names = "tx", "rx", "tx", "rx";
842 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
843 resets = <&cpg 518>;
848 compatible = "renesas,hscif-r8a774e1",
849 "renesas,rcar-gen3-hscif",
853 clocks = <&cpg CPG_MOD 517>,
854 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
856 clock-names = "fck", "brg_int", "scif_clk";
858 dma-names = "tx", "rx";
859 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
860 resets = <&cpg 517>;
865 compatible = "renesas,hscif-r8a774e1",
866 "renesas,rcar-gen3-hscif",
870 clocks = <&cpg CPG_MOD 516>,
871 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
873 clock-names = "fck", "brg_int", "scif_clk";
875 dma-names = "tx", "rx";
876 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
877 resets = <&cpg 516>;
882 compatible = "renesas,usbhs-r8a774e1",
883 "renesas,rcar-gen3-usbhs";
886 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
889 dma-names = "ch0", "ch1", "ch2", "ch3";
892 phy-names = "usb";
893 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
894 resets = <&cpg 704>, <&cpg 703>;
898 usb2_clksel: clock-controller@e6590630 {
899 compatible = "renesas,r8a774e1-rcar-usb2-clock-sel",
900 "renesas,rcar-gen3-usb2-clock-sel";
902 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
904 clock-names = "ehci_ohci", "hs-usb-if",
906 #clock-cells = <0>;
907 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
908 resets = <&cpg 703>, <&cpg 704>;
909 reset-names = "ehci_ohci", "hs-usb-if";
913 usb_dmac0: dma-controller@e65a0000 {
914 compatible = "renesas,r8a774e1-usb-dmac",
915 "renesas,usb-dmac";
919 interrupt-names = "ch0", "ch1";
920 clocks = <&cpg CPG_MOD 330>;
921 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
922 resets = <&cpg 330>;
923 #dma-cells = <1>;
924 dma-channels = <2>;
927 usb_dmac1: dma-controller@e65b0000 {
928 compatible = "renesas,r8a774e1-usb-dmac",
929 "renesas,usb-dmac";
933 interrupt-names = "ch0", "ch1";
934 clocks = <&cpg CPG_MOD 331>;
935 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
936 resets = <&cpg 331>;
937 #dma-cells = <1>;
938 dma-channels = <2>;
941 usb3_phy0: usb-phy@e65ee000 {
942 compatible = "renesas,r8a774e1-usb3-phy",
943 "renesas,rcar-gen3-usb3-phy";
945 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
947 clock-names = "usb3-if", "usb3s_clk", "usb_extal";
948 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
949 resets = <&cpg 328>;
950 #phy-cells = <0>;
954 dmac0: dma-controller@e6700000 {
955 compatible = "renesas,dmac-r8a774e1",
956 "renesas,rcar-dmac";
975 interrupt-names = "error",
980 clocks = <&cpg CPG_MOD 219>;
981 clock-names = "fck";
982 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
983 resets = <&cpg 219>;
984 #dma-cells = <1>;
985 dma-channels = <16>;
996 dmac1: dma-controller@e7300000 {
997 compatible = "renesas,dmac-r8a774e1",
998 "renesas,rcar-dmac";
1017 interrupt-names = "error",
1022 clocks = <&cpg CPG_MOD 218>;
1023 clock-names = "fck";
1024 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1025 resets = <&cpg 218>;
1026 #dma-cells = <1>;
1027 dma-channels = <16>;
1038 dmac2: dma-controller@e7310000 {
1039 compatible = "renesas,dmac-r8a774e1",
1040 "renesas,rcar-dmac";
1059 interrupt-names = "error",
1064 clocks = <&cpg CPG_MOD 217>;
1065 clock-names = "fck";
1066 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1067 resets = <&cpg 217>;
1068 #dma-cells = <1>;
1069 dma-channels = <16>;
1081 compatible = "renesas,ipmmu-r8a774e1";
1083 renesas,ipmmu-main = <&ipmmu_mm 0>;
1084 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1085 #iommu-cells = <1>;
1089 compatible = "renesas,ipmmu-r8a774e1";
1091 renesas,ipmmu-main = <&ipmmu_mm 1>;
1092 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1093 #iommu-cells = <1>;
1097 compatible = "renesas,ipmmu-r8a774e1";
1099 renesas,ipmmu-main = <&ipmmu_mm 2>;
1100 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1101 #iommu-cells = <1>;
1105 compatible = "renesas,ipmmu-r8a774e1";
1109 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1110 #iommu-cells = <1>;
1114 compatible = "renesas,ipmmu-r8a774e1";
1116 renesas,ipmmu-main = <&ipmmu_mm 4>;
1117 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1118 #iommu-cells = <1>;
1122 compatible = "renesas,ipmmu-r8a774e1";
1124 renesas,ipmmu-main = <&ipmmu_mm 6>;
1125 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1126 #iommu-cells = <1>;
1130 compatible = "renesas,ipmmu-r8a774e1";
1132 renesas,ipmmu-main = <&ipmmu_mm 7>;
1133 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1134 #iommu-cells = <1>;
1138 compatible = "renesas,ipmmu-r8a774e1";
1140 renesas,ipmmu-main = <&ipmmu_mm 8>;
1141 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1142 #iommu-cells = <1>;
1146 compatible = "renesas,ipmmu-r8a774e1";
1148 renesas,ipmmu-main = <&ipmmu_mm 9>;
1149 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1150 #iommu-cells = <1>;
1154 compatible = "renesas,ipmmu-r8a774e1";
1156 renesas,ipmmu-main = <&ipmmu_mm 12>;
1157 power-domains = <&sysc R8A774E1_PD_A3VC>;
1158 #iommu-cells = <1>;
1162 compatible = "renesas,ipmmu-r8a774e1";
1164 renesas,ipmmu-main = <&ipmmu_mm 13>;
1165 power-domains = <&sysc R8A774E1_PD_A3VC>;
1166 #iommu-cells = <1>;
1170 compatible = "renesas,ipmmu-r8a774e1";
1172 renesas,ipmmu-main = <&ipmmu_mm 14>;
1173 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1174 #iommu-cells = <1>;
1178 compatible = "renesas,ipmmu-r8a774e1";
1180 renesas,ipmmu-main = <&ipmmu_mm 15>;
1181 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1182 #iommu-cells = <1>;
1186 compatible = "renesas,ipmmu-r8a774e1";
1188 renesas,ipmmu-main = <&ipmmu_mm 16>;
1189 power-domains = <&sysc R8A774E1_PD_A3VP>;
1190 #iommu-cells = <1>;
1194 compatible = "renesas,ipmmu-r8a774e1";
1196 renesas,ipmmu-main = <&ipmmu_mm 17>;
1197 power-domains = <&sysc R8A774E1_PD_A3VP>;
1198 #iommu-cells = <1>;
1202 compatible = "renesas,etheravb-r8a774e1",
1203 "renesas,etheravb-rcar-gen3";
1230 interrupt-names = "ch0", "ch1", "ch2", "ch3",
1237 clocks = <&cpg CPG_MOD 812>;
1238 clock-names = "fck";
1239 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1240 resets = <&cpg 812>;
1241 phy-mode = "rgmii";
1242 rx-internal-delay-ps = <0>;
1243 tx-internal-delay-ps = <0>;
1245 #address-cells = <1>;
1246 #size-cells = <0>;
1251 compatible = "renesas,can-r8a774e1",
1252 "renesas,rcar-gen3-can";
1255 clocks = <&cpg CPG_MOD 916>,
1256 <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
1258 clock-names = "clkp1", "clkp2", "can_clk";
1259 assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
1260 assigned-clock-rates = <40000000>;
1261 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1262 resets = <&cpg 916>;
1267 compatible = "renesas,can-r8a774e1",
1268 "renesas,rcar-gen3-can";
1271 clocks = <&cpg CPG_MOD 915>,
1272 <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
1274 clock-names = "clkp1", "clkp2", "can_clk";
1275 assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
1276 assigned-clock-rates = <40000000>;
1277 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1278 resets = <&cpg 915>;
1283 compatible = "renesas,r8a774e1-canfd",
1284 "renesas,rcar-gen3-canfd";
1288 interrupt-names = "ch_int", "g_int";
1289 clocks = <&cpg CPG_MOD 914>,
1290 <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
1292 clock-names = "fck", "canfd", "can_clk";
1293 assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
1294 assigned-clock-rates = <40000000>;
1295 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1296 resets = <&cpg 914>;
1309 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1311 clocks = <&cpg CPG_MOD 523>;
1312 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1313 resets = <&cpg 523>;
1314 #pwm-cells = <2>;
1319 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1321 clocks = <&cpg CPG_MOD 523>;
1322 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1323 resets = <&cpg 523>;
1324 #pwm-cells = <2>;
1329 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1331 clocks = <&cpg CPG_MOD 523>;
1332 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1333 resets = <&cpg 523>;
1334 #pwm-cells = <2>;
1339 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1341 clocks = <&cpg CPG_MOD 523>;
1342 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1343 resets = <&cpg 523>;
1344 #pwm-cells = <2>;
1349 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1351 clocks = <&cpg CPG_MOD 523>;
1352 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1353 resets = <&cpg 523>;
1354 #pwm-cells = <2>;
1359 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1361 clocks = <&cpg CPG_MOD 523>;
1362 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1363 resets = <&cpg 523>;
1364 #pwm-cells = <2>;
1369 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1371 clocks = <&cpg CPG_MOD 523>;
1372 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1373 resets = <&cpg 523>;
1374 #pwm-cells = <2>;
1379 compatible = "renesas,scif-r8a774e1",
1380 "renesas,rcar-gen3-scif", "renesas,scif";
1383 clocks = <&cpg CPG_MOD 207>,
1384 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1386 clock-names = "fck", "brg_int", "scif_clk";
1389 dma-names = "tx", "rx", "tx", "rx";
1390 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1391 resets = <&cpg 207>;
1396 compatible = "renesas,scif-r8a774e1",
1397 "renesas,rcar-gen3-scif", "renesas,scif";
1400 clocks = <&cpg CPG_MOD 206>,
1401 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1403 clock-names = "fck", "brg_int", "scif_clk";
1406 dma-names = "tx", "rx", "tx", "rx";
1407 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1408 resets = <&cpg 206>;
1413 compatible = "renesas,scif-r8a774e1",
1414 "renesas,rcar-gen3-scif", "renesas,scif";
1417 clocks = <&cpg CPG_MOD 310>,
1418 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1420 clock-names = "fck", "brg_int", "scif_clk";
1423 dma-names = "tx", "rx", "tx", "rx";
1424 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1425 resets = <&cpg 310>;
1430 compatible = "renesas,scif-r8a774e1",
1431 "renesas,rcar-gen3-scif", "renesas,scif";
1434 clocks = <&cpg CPG_MOD 204>,
1435 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1437 clock-names = "fck", "brg_int", "scif_clk";
1439 dma-names = "tx", "rx";
1440 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1441 resets = <&cpg 204>;
1446 compatible = "renesas,scif-r8a774e1",
1447 "renesas,rcar-gen3-scif", "renesas,scif";
1450 clocks = <&cpg CPG_MOD 203>,
1451 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1453 clock-names = "fck", "brg_int", "scif_clk";
1455 dma-names = "tx", "rx";
1456 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1457 resets = <&cpg 203>;
1462 compatible = "renesas,scif-r8a774e1",
1463 "renesas,rcar-gen3-scif", "renesas,scif";
1466 clocks = <&cpg CPG_MOD 202>,
1467 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1469 clock-names = "fck", "brg_int", "scif_clk";
1472 dma-names = "tx", "rx", "tx", "rx";
1473 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1474 resets = <&cpg 202>;
1479 compatible = "renesas,msiof-r8a774e1",
1480 "renesas,rcar-gen3-msiof";
1483 clocks = <&cpg CPG_MOD 211>;
1486 dma-names = "tx", "rx", "tx", "rx";
1487 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1488 resets = <&cpg 211>;
1489 #address-cells = <1>;
1490 #size-cells = <0>;
1495 compatible = "renesas,msiof-r8a774e1",
1496 "renesas,rcar-gen3-msiof";
1499 clocks = <&cpg CPG_MOD 210>;
1502 dma-names = "tx", "rx", "tx", "rx";
1503 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1504 resets = <&cpg 210>;
1505 #address-cells = <1>;
1506 #size-cells = <0>;
1511 compatible = "renesas,msiof-r8a774e1",
1512 "renesas,rcar-gen3-msiof";
1515 clocks = <&cpg CPG_MOD 209>;
1517 dma-names = "tx", "rx";
1518 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1519 resets = <&cpg 209>;
1520 #address-cells = <1>;
1521 #size-cells = <0>;
1526 compatible = "renesas,msiof-r8a774e1",
1527 "renesas,rcar-gen3-msiof";
1530 clocks = <&cpg CPG_MOD 208>;
1532 dma-names = "tx", "rx";
1533 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1534 resets = <&cpg 208>;
1535 #address-cells = <1>;
1536 #size-cells = <0>;
1541 compatible = "renesas,vin-r8a774e1";
1544 clocks = <&cpg CPG_MOD 811>;
1545 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1546 resets = <&cpg 811>;
1551 #address-cells = <1>;
1552 #size-cells = <0>;
1555 #address-cells = <1>;
1556 #size-cells = <0>;
1562 remote-endpoint = <&csi20vin0>;
1566 remote-endpoint = <&csi40vin0>;
1573 compatible = "renesas,vin-r8a774e1";
1576 clocks = <&cpg CPG_MOD 810>;
1577 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1578 resets = <&cpg 810>;
1583 #address-cells = <1>;
1584 #size-cells = <0>;
1587 #address-cells = <1>;
1588 #size-cells = <0>;
1594 remote-endpoint = <&csi20vin1>;
1598 remote-endpoint = <&csi40vin1>;
1605 compatible = "renesas,vin-r8a774e1";
1608 clocks = <&cpg CPG_MOD 809>;
1609 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1610 resets = <&cpg 809>;
1615 #address-cells = <1>;
1616 #size-cells = <0>;
1619 #address-cells = <1>;
1620 #size-cells = <0>;
1626 remote-endpoint = <&csi20vin2>;
1630 remote-endpoint = <&csi40vin2>;
1637 compatible = "renesas,vin-r8a774e1";
1640 clocks = <&cpg CPG_MOD 808>;
1641 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1642 resets = <&cpg 808>;
1647 #address-cells = <1>;
1648 #size-cells = <0>;
1651 #address-cells = <1>;
1652 #size-cells = <0>;
1658 remote-endpoint = <&csi20vin3>;
1662 remote-endpoint = <&csi40vin3>;
1669 compatible = "renesas,vin-r8a774e1";
1672 clocks = <&cpg CPG_MOD 807>;
1673 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1674 resets = <&cpg 807>;
1679 #address-cells = <1>;
1680 #size-cells = <0>;
1683 #address-cells = <1>;
1684 #size-cells = <0>;
1690 remote-endpoint = <&csi20vin4>;
1697 compatible = "renesas,vin-r8a774e1";
1700 clocks = <&cpg CPG_MOD 806>;
1701 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1702 resets = <&cpg 806>;
1707 #address-cells = <1>;
1708 #size-cells = <0>;
1711 #address-cells = <1>;
1712 #size-cells = <0>;
1718 remote-endpoint = <&csi20vin5>;
1725 compatible = "renesas,vin-r8a774e1";
1728 clocks = <&cpg CPG_MOD 805>;
1729 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1730 resets = <&cpg 805>;
1735 #address-cells = <1>;
1736 #size-cells = <0>;
1739 #address-cells = <1>;
1740 #size-cells = <0>;
1746 remote-endpoint = <&csi20vin6>;
1753 compatible = "renesas,vin-r8a774e1";
1756 clocks = <&cpg CPG_MOD 804>;
1757 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1758 resets = <&cpg 804>;
1763 #address-cells = <1>;
1764 #size-cells = <0>;
1767 #address-cells = <1>;
1768 #size-cells = <0>;
1774 remote-endpoint = <&csi20vin7>;
1782 * #sound-dai-cells is required if simple-card
1784 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1785 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1788 * #clock-cells is required for audio_clkout0/1/2/3
1790 * clkout : #clock-cells = <0>; <&rcar_sound>;
1791 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1793 compatible = "renesas,rcar_sound-r8a774e1", "renesas,rcar_sound-gen3";
1799 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1801 clocks = <&cpg CPG_MOD 1005>,
1802 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1803 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1804 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1805 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1806 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1807 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1808 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1809 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1810 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1811 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1812 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1813 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1814 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1817 <&cpg CPG_MOD 922>;
1818 clock-names = "ssi-all",
1829 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1830 resets = <&cpg 1005>,
1831 <&cpg 1006>, <&cpg 1007>,
1832 <&cpg 1008>, <&cpg 1009>,
1833 <&cpg 1010>, <&cpg 1011>,
1834 <&cpg 1012>, <&cpg 1013>,
1835 <&cpg 1014>, <&cpg 1015>;
1836 reset-names = "ssi-all",
1843 dvc0: dvc-0 {
1845 dma-names = "tx";
1847 dvc1: dvc-1 {
1849 dma-names = "tx";
1854 mix0: mix-0 { };
1855 mix1: mix-1 { };
1859 ctu00: ctu-0 { };
1860 ctu01: ctu-1 { };
1861 ctu02: ctu-2 { };
1862 ctu03: ctu-3 { };
1863 ctu10: ctu-4 { };
1864 ctu11: ctu-5 { };
1865 ctu12: ctu-6 { };
1866 ctu13: ctu-7 { };
1870 src0: src-0 {
1873 dma-names = "rx", "tx";
1875 src1: src-1 {
1878 dma-names = "rx", "tx";
1880 src2: src-2 {
1883 dma-names = "rx", "tx";
1885 src3: src-3 {
1888 dma-names = "rx", "tx";
1890 src4: src-4 {
1893 dma-names = "rx", "tx";
1895 src5: src-5 {
1898 dma-names = "rx", "tx";
1900 src6: src-6 {
1903 dma-names = "rx", "tx";
1905 src7: src-7 {
1908 dma-names = "rx", "tx";
1910 src8: src-8 {
1913 dma-names = "rx", "tx";
1915 src9: src-9 {
1918 dma-names = "rx", "tx";
1923 ssiu00: ssiu-0 {
1925 dma-names = "rx", "tx";
1927 ssiu01: ssiu-1 {
1929 dma-names = "rx", "tx";
1931 ssiu02: ssiu-2 {
1933 dma-names = "rx", "tx";
1935 ssiu03: ssiu-3 {
1937 dma-names = "rx", "tx";
1939 ssiu04: ssiu-4 {
1941 dma-names = "rx", "tx";
1943 ssiu05: ssiu-5 {
1945 dma-names = "rx", "tx";
1947 ssiu06: ssiu-6 {
1949 dma-names = "rx", "tx";
1951 ssiu07: ssiu-7 {
1953 dma-names = "rx", "tx";
1955 ssiu10: ssiu-8 {
1957 dma-names = "rx", "tx";
1959 ssiu11: ssiu-9 {
1961 dma-names = "rx", "tx";
1963 ssiu12: ssiu-10 {
1965 dma-names = "rx", "tx";
1967 ssiu13: ssiu-11 {
1969 dma-names = "rx", "tx";
1971 ssiu14: ssiu-12 {
1973 dma-names = "rx", "tx";
1975 ssiu15: ssiu-13 {
1977 dma-names = "rx", "tx";
1979 ssiu16: ssiu-14 {
1981 dma-names = "rx", "tx";
1983 ssiu17: ssiu-15 {
1985 dma-names = "rx", "tx";
1987 ssiu20: ssiu-16 {
1989 dma-names = "rx", "tx";
1991 ssiu21: ssiu-17 {
1993 dma-names = "rx", "tx";
1995 ssiu22: ssiu-18 {
1997 dma-names = "rx", "tx";
1999 ssiu23: ssiu-19 {
2001 dma-names = "rx", "tx";
2003 ssiu24: ssiu-20 {
2005 dma-names = "rx", "tx";
2007 ssiu25: ssiu-21 {
2009 dma-names = "rx", "tx";
2011 ssiu26: ssiu-22 {
2013 dma-names = "rx", "tx";
2015 ssiu27: ssiu-23 {
2017 dma-names = "rx", "tx";
2019 ssiu30: ssiu-24 {
2021 dma-names = "rx", "tx";
2023 ssiu31: ssiu-25 {
2025 dma-names = "rx", "tx";
2027 ssiu32: ssiu-26 {
2029 dma-names = "rx", "tx";
2031 ssiu33: ssiu-27 {
2033 dma-names = "rx", "tx";
2035 ssiu34: ssiu-28 {
2037 dma-names = "rx", "tx";
2039 ssiu35: ssiu-29 {
2041 dma-names = "rx", "tx";
2043 ssiu36: ssiu-30 {
2045 dma-names = "rx", "tx";
2047 ssiu37: ssiu-31 {
2049 dma-names = "rx", "tx";
2051 ssiu40: ssiu-32 {
2053 dma-names = "rx", "tx";
2055 ssiu41: ssiu-33 {
2057 dma-names = "rx", "tx";
2059 ssiu42: ssiu-34 {
2061 dma-names = "rx", "tx";
2063 ssiu43: ssiu-35 {
2065 dma-names = "rx", "tx";
2067 ssiu44: ssiu-36 {
2069 dma-names = "rx", "tx";
2071 ssiu45: ssiu-37 {
2073 dma-names = "rx", "tx";
2075 ssiu46: ssiu-38 {
2077 dma-names = "rx", "tx";
2079 ssiu47: ssiu-39 {
2081 dma-names = "rx", "tx";
2083 ssiu50: ssiu-40 {
2085 dma-names = "rx", "tx";
2087 ssiu60: ssiu-41 {
2089 dma-names = "rx", "tx";
2091 ssiu70: ssiu-42 {
2093 dma-names = "rx", "tx";
2095 ssiu80: ssiu-43 {
2097 dma-names = "rx", "tx";
2099 ssiu90: ssiu-44 {
2101 dma-names = "rx", "tx";
2103 ssiu91: ssiu-45 {
2105 dma-names = "rx", "tx";
2107 ssiu92: ssiu-46 {
2109 dma-names = "rx", "tx";
2111 ssiu93: ssiu-47 {
2113 dma-names = "rx", "tx";
2115 ssiu94: ssiu-48 {
2117 dma-names = "rx", "tx";
2119 ssiu95: ssiu-49 {
2121 dma-names = "rx", "tx";
2123 ssiu96: ssiu-50 {
2125 dma-names = "rx", "tx";
2127 ssiu97: ssiu-51 {
2129 dma-names = "rx", "tx";
2134 ssi0: ssi-0 {
2137 dma-names = "rx", "tx";
2139 ssi1: ssi-1 {
2142 dma-names = "rx", "tx";
2144 ssi2: ssi-2 {
2147 dma-names = "rx", "tx";
2149 ssi3: ssi-3 {
2152 dma-names = "rx", "tx";
2154 ssi4: ssi-4 {
2157 dma-names = "rx", "tx";
2159 ssi5: ssi-5 {
2162 dma-names = "rx", "tx";
2164 ssi6: ssi-6 {
2167 dma-names = "rx", "tx";
2169 ssi7: ssi-7 {
2172 dma-names = "rx", "tx";
2174 ssi8: ssi-8 {
2177 dma-names = "rx", "tx";
2179 ssi9: ssi-9 {
2182 dma-names = "rx", "tx";
2187 audma0: dma-controller@ec700000 {
2188 compatible = "renesas,dmac-r8a774e1",
2189 "renesas,rcar-dmac";
2208 interrupt-names = "error",
2213 clocks = <&cpg CPG_MOD 502>;
2214 clock-names = "fck";
2215 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2216 resets = <&cpg 502>;
2217 #dma-cells = <1>;
2218 dma-channels = <16>;
2229 audma1: dma-controller@ec720000 {
2230 compatible = "renesas,dmac-r8a774e1",
2231 "renesas,rcar-dmac";
2250 interrupt-names = "error",
2255 clocks = <&cpg CPG_MOD 501>;
2256 clock-names = "fck";
2257 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2258 resets = <&cpg 501>;
2259 #dma-cells = <1>;
2260 dma-channels = <16>;
2272 compatible = "renesas,xhci-r8a774e1",
2273 "renesas,rcar-gen3-xhci";
2276 clocks = <&cpg CPG_MOD 328>;
2277 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2278 resets = <&cpg 328>;
2283 compatible = "renesas,r8a774e1-usb3-peri",
2284 "renesas,rcar-gen3-usb3-peri";
2287 clocks = <&cpg CPG_MOD 328>;
2288 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2289 resets = <&cpg 328>;
2294 compatible = "generic-ohci";
2297 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2299 phy-names = "usb";
2300 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2301 resets = <&cpg 703>, <&cpg 704>;
2306 compatible = "generic-ohci";
2309 clocks = <&cpg CPG_MOD 702>;
2311 phy-names = "usb";
2312 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2313 resets = <&cpg 702>;
2318 compatible = "generic-ehci";
2321 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2323 phy-names = "usb";
2325 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2326 resets = <&cpg 703>, <&cpg 704>;
2331 compatible = "generic-ehci";
2334 clocks = <&cpg CPG_MOD 702>;
2336 phy-names = "usb";
2338 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2339 resets = <&cpg 702>;
2343 usb2_phy0: usb-phy@ee080200 {
2344 compatible = "renesas,usb2-phy-r8a774e1",
2345 "renesas,rcar-gen3-usb2-phy";
2348 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2349 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2350 resets = <&cpg 703>, <&cpg 704>;
2351 #phy-cells = <1>;
2355 usb2_phy1: usb-phy@ee0a0200 {
2356 compatible = "renesas,usb2-phy-r8a774e1",
2357 "renesas,rcar-gen3-usb2-phy";
2359 clocks = <&cpg CPG_MOD 702>;
2360 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2361 resets = <&cpg 702>;
2362 #phy-cells = <1>;
2367 compatible = "renesas,sdhi-r8a774e1",
2368 "renesas,rcar-gen3-sdhi";
2371 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774E1_CLK_SD0H>;
2372 clock-names = "core", "clkh";
2373 max-frequency = <200000000>;
2374 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2375 resets = <&cpg 314>;
2381 compatible = "renesas,sdhi-r8a774e1",
2382 "renesas,rcar-gen3-sdhi";
2385 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774E1_CLK_SD1H>;
2386 clock-names = "core", "clkh";
2387 max-frequency = <200000000>;
2388 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2389 resets = <&cpg 313>;
2395 compatible = "renesas,sdhi-r8a774e1",
2396 "renesas,rcar-gen3-sdhi";
2399 clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774E1_CLK_SD2H>;
2400 clock-names = "core", "clkh";
2401 max-frequency = <200000000>;
2402 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2403 resets = <&cpg 312>;
2409 compatible = "renesas,sdhi-r8a774e1",
2410 "renesas,rcar-gen3-sdhi";
2413 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774E1_CLK_SD3H>;
2414 clock-names = "core", "clkh";
2415 max-frequency = <200000000>;
2416 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2417 resets = <&cpg 311>;
2423 compatible = "renesas,r8a774e1-rpc-if",
2424 "renesas,rcar-gen3-rpc-if";
2428 reg-names = "regs", "dirmap", "wbuf";
2430 clocks = <&cpg CPG_MOD 917>;
2431 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2432 resets = <&cpg 917>;
2433 #address-cells = <1>;
2434 #size-cells = <0>;
2439 compatible = "renesas,sata-r8a774e1",
2440 "renesas,rcar-gen3-sata";
2443 clocks = <&cpg CPG_MOD 815>;
2444 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2445 resets = <&cpg 815>;
2450 gic: interrupt-controller@f1010000 {
2451 compatible = "arm,gic-400";
2452 #interrupt-cells = <3>;
2453 #address-cells = <0>;
2454 interrupt-controller;
2461 clocks = <&cpg CPG_MOD 408>;
2462 clock-names = "clk";
2463 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2464 resets = <&cpg 408>;
2468 compatible = "renesas,pcie-r8a774e1",
2469 "renesas,pcie-rcar-gen3";
2471 #address-cells = <3>;
2472 #size-cells = <2>;
2473 bus-range = <0x00 0xff>;
2480 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2484 #interrupt-cells = <1>;
2485 interrupt-map-mask = <0 0 0 0>;
2486 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2487 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
2488 clock-names = "pcie", "pcie_bus";
2489 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2490 resets = <&cpg 319>;
2491 iommu-map = <0 &ipmmu_hc 0 1>;
2492 iommu-map-mask = <0>;
2497 compatible = "renesas,pcie-r8a774e1",
2498 "renesas,pcie-rcar-gen3";
2500 #address-cells = <3>;
2501 #size-cells = <2>;
2502 bus-range = <0x00 0xff>;
2509 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2513 #interrupt-cells = <1>;
2514 interrupt-map-mask = <0 0 0 0>;
2515 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2516 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
2517 clock-names = "pcie", "pcie_bus";
2518 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2519 resets = <&cpg 318>;
2520 iommu-map = <0 &ipmmu_hc 1 1>;
2521 iommu-map-mask = <0>;
2525 pciec0_ep: pcie-ep@fe000000 {
2526 compatible = "renesas,r8a774e1-pcie-ep",
2527 "renesas,rcar-gen3-pcie-ep";
2533 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
2537 clocks = <&cpg CPG_MOD 319>;
2538 clock-names = "pcie";
2539 resets = <&cpg 319>;
2540 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2544 pciec1_ep: pcie-ep@ee800000 {
2545 compatible = "renesas,r8a774e1-pcie-ep",
2546 "renesas,rcar-gen3-pcie-ep";
2552 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
2556 clocks = <&cpg CPG_MOD 318>;
2557 clock-names = "pcie";
2558 resets = <&cpg 318>;
2559 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2567 clocks = <&cpg CPG_MOD 624>;
2568 power-domains = <&sysc R8A774E1_PD_A3VP>;
2569 resets = <&cpg 624>;
2578 clocks = <&cpg CPG_MOD 626>;
2579 power-domains = <&sysc R8A774E1_PD_A3VP>;
2580 resets = <&cpg 626>;
2589 clocks = <&cpg CPG_MOD 623>;
2590 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2591 resets = <&cpg 623>;
2600 clocks = <&cpg CPG_MOD 622>;
2601 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2602 resets = <&cpg 622>;
2611 clocks = <&cpg CPG_MOD 631>;
2612 power-domains = <&sysc R8A774E1_PD_A3VP>;
2613 resets = <&cpg 631>;
2622 clocks = <&cpg CPG_MOD 630>;
2623 power-domains = <&sysc R8A774E1_PD_A3VP>;
2624 resets = <&cpg 630>;
2633 clocks = <&cpg CPG_MOD 119>;
2634 power-domains = <&sysc R8A774E1_PD_A3VP>;
2635 resets = <&cpg 119>;
2643 clocks = <&cpg CPG_MOD 118>;
2644 power-domains = <&sysc R8A774E1_PD_A3VP>;
2645 resets = <&cpg 118>;
2652 clocks = <&cpg CPG_MOD 615>;
2653 power-domains = <&sysc R8A774E1_PD_A3VP>;
2654 resets = <&cpg 615>;
2661 clocks = <&cpg CPG_MOD 614>;
2662 power-domains = <&sysc R8A774E1_PD_A3VP>;
2663 resets = <&cpg 614>;
2670 clocks = <&cpg CPG_MOD 607>;
2671 power-domains = <&sysc R8A774E1_PD_A3VP>;
2672 resets = <&cpg 607>;
2679 clocks = <&cpg CPG_MOD 606>;
2680 power-domains = <&sysc R8A774E1_PD_A3VP>;
2681 resets = <&cpg 606>;
2688 clocks = <&cpg CPG_MOD 611>;
2689 power-domains = <&sysc R8A774E1_PD_A3VP>;
2690 resets = <&cpg 611>;
2697 clocks = <&cpg CPG_MOD 610>;
2698 power-domains = <&sysc R8A774E1_PD_A3VP>;
2699 resets = <&cpg 610>;
2706 clocks = <&cpg CPG_MOD 603>;
2707 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2708 resets = <&cpg 603>;
2715 clocks = <&cpg CPG_MOD 602>;
2716 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2717 resets = <&cpg 602>;
2722 compatible = "renesas,r8a774e1-csi2";
2725 clocks = <&cpg CPG_MOD 714>;
2726 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2727 resets = <&cpg 714>;
2731 #address-cells = <1>;
2732 #size-cells = <0>;
2739 #address-cells = <1>;
2740 #size-cells = <0>;
2746 remote-endpoint = <&vin0csi20>;
2750 remote-endpoint = <&vin1csi20>;
2754 remote-endpoint = <&vin2csi20>;
2758 remote-endpoint = <&vin3csi20>;
2762 remote-endpoint = <&vin4csi20>;
2766 remote-endpoint = <&vin5csi20>;
2770 remote-endpoint = <&vin6csi20>;
2774 remote-endpoint = <&vin7csi20>;
2781 compatible = "renesas,r8a774e1-csi2";
2784 clocks = <&cpg CPG_MOD 716>;
2785 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2786 resets = <&cpg 716>;
2790 #address-cells = <1>;
2791 #size-cells = <0>;
2798 #address-cells = <1>;
2799 #size-cells = <0>;
2805 remote-endpoint = <&vin0csi40>;
2809 remote-endpoint = <&vin1csi40>;
2813 remote-endpoint = <&vin2csi40>;
2817 remote-endpoint = <&vin3csi40>;
2824 compatible = "renesas,r8a774e1-hdmi",
2825 "renesas,rcar-gen3-hdmi";
2828 clocks = <&cpg CPG_MOD 729>,
2829 <&cpg CPG_CORE R8A774E1_CLK_HDMI>;
2830 clock-names = "iahb", "isfr";
2831 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2832 resets = <&cpg 729>;
2836 #address-cells = <1>;
2837 #size-cells = <0>;
2842 remote-endpoint = <&du_out_hdmi0>;
2856 compatible = "renesas,du-r8a774e1";
2861 clocks = <&cpg CPG_MOD 724>,
2862 <&cpg CPG_MOD 723>,
2863 <&cpg CPG_MOD 721>;
2864 clock-names = "du.0", "du.1", "du.3";
2865 resets = <&cpg 724>, <&cpg 722>;
2866 reset-names = "du.0", "du.3";
2872 #address-cells = <1>;
2873 #size-cells = <0>;
2881 remote-endpoint = <&dw_hdmi0_in>;
2887 remote-endpoint = <&lvds0_in>;
2894 compatible = "renesas,r8a774e1-lvds";
2896 clocks = <&cpg CPG_MOD 727>;
2897 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2898 resets = <&cpg 727>;
2902 #address-cells = <1>;
2903 #size-cells = <0>;
2908 remote-endpoint = <&du_out_lvds0>;
2923 thermal-zones {
2924 sensor1_thermal: sensor1-thermal {
2925 polling-delay-passive = <250>;
2926 polling-delay = <1000>;
2927 thermal-sensors = <&tsc 0>;
2928 sustainable-power = <6313>;
2931 sensor1_crit: sensor1-crit {
2939 sensor2_thermal: sensor2-thermal {
2940 polling-delay-passive = <250>;
2941 polling-delay = <1000>;
2942 thermal-sensors = <&tsc 1>;
2943 sustainable-power = <6313>;
2946 sensor2_crit: sensor2-crit {
2954 sensor3_thermal: sensor3-thermal {
2955 polling-delay-passive = <250>;
2956 polling-delay = <1000>;
2957 thermal-sensors = <&tsc 2>;
2958 sustainable-power = <6313>;
2961 target: trip-point1 {
2967 sensor3_crit: sensor3-crit {
2974 cooling-maps {
2977 cooling-device = <&a57_0 0 2>;
2983 cooling-device = <&a53_0 0 2>;
2991 compatible = "arm,armv8-timer";
2992 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2996 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
2999 /* External USB clocks - can be overridden by the board */
3001 compatible = "fixed-clock";
3002 #clock-cells = <0>;
3003 clock-frequency = <0>;
3007 compatible = "fixed-clock";
3008 #clock-cells = <0>;
3009 clock-frequency = <0>;