Lines Matching +full:0 +full:xfeb00000
18 * The external audio clocks are configured as 0 Hz fixed frequency
24 #clock-cells = <0>;
25 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
36 #clock-cells = <0>;
37 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
67 #size-cells = <0>;
69 a53_0: cpu@0 {
71 reg = <0>;
93 L2_CA53: cache-controller-0 {
103 #clock-cells = <0>;
105 clock-frequency = <0>;
111 #clock-cells = <0>;
112 clock-frequency = <0>;
130 #clock-cells = <0>;
131 clock-frequency = <0>;
144 reg = <0 0xe6020000 0 0x0c>;
155 reg = <0 0xe6050000 0 0x50>;
159 gpio-ranges = <&pfc 0 0 18>;
170 reg = <0 0xe6051000 0 0x50>;
174 gpio-ranges = <&pfc 0 32 23>;
185 reg = <0 0xe6052000 0 0x50>;
189 gpio-ranges = <&pfc 0 64 26>;
200 reg = <0 0xe6053000 0 0x50>;
204 gpio-ranges = <&pfc 0 96 16>;
215 reg = <0 0xe6054000 0 0x50>;
219 gpio-ranges = <&pfc 0 128 11>;
230 reg = <0 0xe6055000 0 0x50>;
234 gpio-ranges = <&pfc 0 160 20>;
245 reg = <0 0xe6055400 0 0x50>;
249 gpio-ranges = <&pfc 0 192 18>;
259 reg = <0 0xe6060000 0 0x508>;
265 reg = <0 0xe60f0000 0 0x1004>;
278 reg = <0 0xe6130000 0 0x1004>;
297 reg = <0 0xe6140000 0 0x1004>;
316 reg = <0 0xe6148000 0 0x1004>;
334 reg = <0 0xe6150000 0 0x1000>;
338 #power-domain-cells = <0>;
344 reg = <0 0xe6160000 0 0x0200>;
349 reg = <0 0xe6180000 0 0x0400>;
355 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
362 #thermal-sensor-cells = <0>;
369 reg = <0 0xe61c0000 0 0x200>;
370 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
383 reg = <0 0xe61e0000 0 0x30>;
397 reg = <0 0xe6fc0000 0 0x30>;
412 reg = <0 0xe6fd0000 0 0x30>;
427 reg = <0 0xe6fe0000 0 0x30>;
441 reg = <0 0xffc00000 0 0x30>;
455 #size-cells = <0>;
458 reg = <0 0xe6500000 0 0x40>;
463 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
464 <&dmac2 0x91>, <&dmac2 0x90>;
472 #size-cells = <0>;
475 reg = <0 0xe6508000 0 0x40>;
480 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
481 <&dmac2 0x93>, <&dmac2 0x92>;
489 #size-cells = <0>;
492 reg = <0 0xe6510000 0 0x40>;
497 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
498 <&dmac2 0x95>, <&dmac2 0x94>;
506 #size-cells = <0>;
509 reg = <0 0xe66d0000 0 0x40>;
514 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
522 #size-cells = <0>;
525 reg = <0 0xe66d8000 0 0x40>;
530 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
538 #size-cells = <0>;
541 reg = <0 0xe66e0000 0 0x40>;
546 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
554 #size-cells = <0>;
557 reg = <0 0xe66e8000 0 0x40>;
562 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
570 #size-cells = <0>;
573 reg = <0 0xe6690000 0 0x40>;
584 #size-cells = <0>;
588 reg = <0 0xe60b0000 0 0x425>;
593 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
602 reg = <0 0xe6540000 0 0x60>;
608 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
609 <&dmac2 0x31>, <&dmac2 0x30>;
620 reg = <0 0xe6550000 0 0x60>;
626 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
627 <&dmac2 0x33>, <&dmac2 0x32>;
638 reg = <0 0xe6560000 0 0x60>;
644 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
645 <&dmac2 0x35>, <&dmac2 0x34>;
656 reg = <0 0xe66a0000 0 0x60>;
662 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
673 reg = <0 0xe66b0000 0 0x60>;
679 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
689 reg = <0 0xe6590000 0 0x200>;
692 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
693 <&usb_dmac1 0>, <&usb_dmac1 1>;
706 reg = <0 0xe65a0000 0 0x100>;
720 reg = <0 0xe65b0000 0 0x100>;
734 reg = <0 0xe6700000 0 0x10000>;
763 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
776 reg = <0 0xe7300000 0 0x10000>;
805 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
818 reg = <0 0xe7310000 0 0x10000>;
859 reg = <0 0xe6740000 0 0x1000>;
860 renesas,ipmmu-main = <&ipmmu_mm 0>;
867 reg = <0 0xe7740000 0 0x1000>;
875 reg = <0 0xe6570000 0 0x1000>;
883 reg = <0 0xe67b0000 0 0x1000>;
892 reg = <0 0xec670000 0 0x1000>;
900 reg = <0 0xfd800000 0 0x1000>;
908 reg = <0 0xfe6b0000 0 0x1000>;
916 reg = <0 0xfebd0000 0 0x1000>;
924 reg = <0 0xfe990000 0 0x1000>;
933 reg = <0 0xe6800000 0 0x800>;
971 rx-internal-delay-ps = <0>;
974 #size-cells = <0>;
981 reg = <0 0xe6c30000 0 0x1000>;
997 reg = <0 0xe6c38000 0 0x1000>;
1013 reg = <0 0xe66c0000 0 0x8000>;
1038 reg = <0 0xe6e30000 0 0x8>;
1048 reg = <0 0xe6e31000 0 0x8>;
1058 reg = <0 0xe6e32000 0 0x8>;
1068 reg = <0 0xe6e33000 0 0x8>;
1078 reg = <0 0xe6e34000 0 0x8>;
1088 reg = <0 0xe6e35000 0 0x8>;
1098 reg = <0 0xe6e36000 0 0x8>;
1109 reg = <0 0xe6e60000 0 64>;
1115 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1116 <&dmac2 0x51>, <&dmac2 0x50>;
1126 reg = <0 0xe6e68000 0 64>;
1132 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1133 <&dmac2 0x53>, <&dmac2 0x52>;
1143 reg = <0 0xe6e88000 0 64>;
1149 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1150 <&dmac2 0x13>, <&dmac2 0x12>;
1160 reg = <0 0xe6c50000 0 64>;
1166 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1176 reg = <0 0xe6c40000 0 64>;
1182 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1192 reg = <0 0xe6f30000 0 64>;
1198 dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
1208 reg = <0 0xe6e90000 0 0x0064>;
1211 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1212 <&dmac2 0x41>, <&dmac2 0x40>;
1217 #size-cells = <0>;
1224 reg = <0 0xe6ea0000 0 0x0064>;
1227 dmas = <&dmac0 0x43>, <&dmac0 0x42>;
1232 #size-cells = <0>;
1239 reg = <0 0xe6c00000 0 0x0064>;
1242 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1247 #size-cells = <0>;
1254 reg = <0 0xe6c10000 0 0x0064>;
1257 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1262 #size-cells = <0>;
1268 reg = <0 0xe6ef4000 0 0x1000>;
1278 #size-cells = <0>;
1282 #size-cells = <0>;
1296 reg = <0 0xe6ef5000 0 0x1000>;
1306 #size-cells = <0>;
1310 #size-cells = <0>;
1326 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1332 * clkout : #clock-cells = <0>; <&rcar_sound>;
1337 reg = <0 0xec500000 0 0x1000>, /* SCU */
1338 <0 0xec5a0000 0 0x100>, /* ADG */
1339 <0 0xec540000 0 0x1000>, /* SSIU */
1340 <0 0xec541000 0 0x280>, /* SSI */
1341 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1364 "ssi.1", "ssi.0",
1367 "src.1", "src.0",
1368 "mix.1", "mix.0",
1369 "ctu.1", "ctu.0",
1370 "dvc.0", "dvc.1",
1382 "ssi.1", "ssi.0";
1386 ctu00: ctu-0 { };
1397 dvc0: dvc-0 {
1398 dmas = <&audma0 0xbc>;
1402 dmas = <&audma0 0xbe>;
1408 mix0: mix-0 { };
1413 src0: src-0 {
1415 dmas = <&audma0 0x85>, <&audma0 0x9a>;
1420 dmas = <&audma0 0x87>, <&audma0 0x9c>;
1425 dmas = <&audma0 0x89>, <&audma0 0x9e>;
1430 dmas = <&audma0 0x8b>, <&audma0 0xa0>;
1435 dmas = <&audma0 0x8d>, <&audma0 0xb0>;
1440 dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1445 dmas = <&audma0 0x91>, <&audma0 0xb4>;
1450 dmas = <&audma0 0x93>, <&audma0 0xb6>;
1455 dmas = <&audma0 0x95>, <&audma0 0xb8>;
1460 dmas = <&audma0 0x97>, <&audma0 0xba>;
1466 ssi0: ssi-0 {
1468 dmas = <&audma0 0x01>, <&audma0 0x02>,
1469 <&audma0 0x15>, <&audma0 0x16>;
1474 dmas = <&audma0 0x03>, <&audma0 0x04>,
1475 <&audma0 0x49>, <&audma0 0x4a>;
1480 dmas = <&audma0 0x05>, <&audma0 0x06>,
1481 <&audma0 0x63>, <&audma0 0x64>;
1486 dmas = <&audma0 0x07>, <&audma0 0x08>,
1487 <&audma0 0x6f>, <&audma0 0x70>;
1492 dmas = <&audma0 0x09>, <&audma0 0x0a>,
1493 <&audma0 0x71>, <&audma0 0x72>;
1498 dmas = <&audma0 0x0b>, <&audma0 0x0c>,
1499 <&audma0 0x73>, <&audma0 0x74>;
1504 dmas = <&audma0 0x0d>, <&audma0 0x0e>,
1505 <&audma0 0x75>, <&audma0 0x76>;
1510 dmas = <&audma0 0x0f>, <&audma0 0x10>,
1511 <&audma0 0x79>, <&audma0 0x7a>;
1516 dmas = <&audma0 0x11>, <&audma0 0x12>,
1517 <&audma0 0x7b>, <&audma0 0x7c>;
1522 dmas = <&audma0 0x13>, <&audma0 0x14>,
1523 <&audma0 0x7d>, <&audma0 0x7e>;
1532 reg = <0 0xec700000 0 0x10000>;
1561 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
1574 reg = <0 0xee000000 0 0xc00>;
1585 reg = <0 0xee020000 0 0x400>;
1595 reg = <0 0xee080000 0 0x100>;
1607 reg = <0 0xee080100 0 0x100>;
1621 reg = <0 0xee080200 0 0x700>;
1633 reg = <0 0xee100000 0 0x2000>;
1647 reg = <0 0xee120000 0 0x2000>;
1661 reg = <0 0xee160000 0 0x2000>;
1675 reg = <0 0xee200000 0 0x200>,
1676 <0 0x08000000 0 0x4000000>,
1677 <0 0xee208000 0 0x100>;
1684 #size-cells = <0>;
1691 #address-cells = <0>;
1693 reg = <0x0 0xf1010000 0 0x1000>,
1694 <0x0 0xf1020000 0 0x20000>,
1695 <0x0 0xf1040000 0 0x20000>,
1696 <0x0 0xf1060000 0 0x20000>;
1708 reg = <0 0xfe000000 0 0x80000>;
1711 bus-range = <0x00 0xff>;
1713 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
1714 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
1715 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
1716 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1718 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
1723 interrupt-map-mask = <0 0 0 0>;
1724 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1729 iommu-map = <0 &ipmmu_hc 0 1>;
1730 iommu-map-mask = <0>;
1737 reg = <0x0 0xfe000000 0 0x80000>,
1738 <0x0 0xfe100000 0 0x100000>,
1739 <0x0 0xfe200000 0 0x200000>,
1740 <0x0 0x30000000 0 0x8000000>,
1741 <0x0 0x38000000 0 0x8000000>;
1755 reg = <0 0xfe960000 0 0x8000>;
1765 reg = <0 0xfea20000 0 0x7000>;
1775 reg = <0 0xfea28000 0 0x7000>;
1785 reg = <0 0xfe9a0000 0 0x8000>;
1795 reg = <0 0xfe96f000 0 0x200>;
1804 reg = <0 0xfea27000 0 0x200>;
1813 reg = <0 0xfea2f000 0 0x200>;
1822 reg = <0 0xfe9af000 0 0x200>;
1831 reg = <0 0xfeaa0000 0 0x10000>;
1840 #size-cells = <0>;
1842 port@0 {
1843 reg = <0>;
1848 #size-cells = <0>;
1852 csi40vin4: endpoint@0 {
1853 reg = <0>;
1866 reg = <0 0xfeb00000 0 0x40000>;
1870 clock-names = "du.0", "du.1";
1872 reset-names = "du.0";
1873 renesas,vsps = <&vspd0 0>, <&vspd1 0>;
1879 #size-cells = <0>;
1881 port@0 {
1882 reg = <0>;
1903 reg = <0 0xfeb90000 0 0x20>;
1913 #size-cells = <0>;
1915 port@0 {
1916 reg = <0>;
1930 reg = <0 0xfeb90100 0 0x20>;
1938 #size-cells = <0>;
1940 port@0 {
1941 reg = <0>;
1955 reg = <0 0xfff00044 0 4>;
1962 polling-delay = <0>;
1969 cooling-device = <&a53_0 0 2>;
2002 #clock-cells = <0>;
2003 clock-frequency = <0>;
2008 #clock-cells = <0>;
2009 clock-frequency = <0>;