Lines Matching +full:0 +full:xee200000
18 * The external audio clocks are configured as 0 Hz fixed frequency
24 #clock-cells = <0>;
25 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
36 #clock-cells = <0>;
37 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
71 #size-cells = <0>;
73 a53_0: cpu@0 {
75 reg = <0>;
97 L2_CA53: cache-controller-0 {
107 #clock-cells = <0>;
109 clock-frequency = <0>;
116 #clock-cells = <0>;
117 clock-frequency = <0>;
135 #clock-cells = <0>;
136 clock-frequency = <0>;
151 reg = <0 0xe6020000 0 0x0c>;
162 reg = <0 0xe6050000 0 0x50>;
166 gpio-ranges = <&pfc 0 0 18>;
177 reg = <0 0xe6051000 0 0x50>;
181 gpio-ranges = <&pfc 0 32 23>;
192 reg = <0 0xe6052000 0 0x50>;
196 gpio-ranges = <&pfc 0 64 26>;
207 reg = <0 0xe6053000 0 0x50>;
211 gpio-ranges = <&pfc 0 96 16>;
222 reg = <0 0xe6054000 0 0x50>;
226 gpio-ranges = <&pfc 0 128 11>;
237 reg = <0 0xe6055000 0 0x50>;
241 gpio-ranges = <&pfc 0 160 20>;
252 reg = <0 0xe6055400 0 0x50>;
256 gpio-ranges = <&pfc 0 192 18>;
266 reg = <0 0xe6060000 0 0x508>;
273 reg = <0 0xe60f0000 0 0x1004>;
286 reg = <0 0xe6130000 0 0x1004>;
305 reg = <0 0xe6140000 0 0x1004>;
324 reg = <0 0xe6148000 0 0x1004>;
342 reg = <0 0xe6150000 0 0x1000>;
346 #power-domain-cells = <0>;
353 reg = <0 0xe6160000 0 0x0200>;
359 reg = <0 0xe6180000 0 0x0400>;
365 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
372 #thermal-sensor-cells = <0>;
379 reg = <0 0xe61c0000 0 0x200>;
380 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
393 reg = <0 0xe61e0000 0 0x30>;
407 reg = <0 0xe6fc0000 0 0x30>;
422 reg = <0 0xe6fd0000 0 0x30>;
437 reg = <0 0xe6fe0000 0 0x30>;
451 reg = <0 0xffc00000 0 0x30>;
465 #size-cells = <0>;
468 reg = <0 0xe6500000 0 0x40>;
473 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
474 <&dmac2 0x91>, <&dmac2 0x90>;
482 #size-cells = <0>;
485 reg = <0 0xe6508000 0 0x40>;
490 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
491 <&dmac2 0x93>, <&dmac2 0x92>;
499 #size-cells = <0>;
502 reg = <0 0xe6510000 0 0x40>;
507 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
508 <&dmac2 0x95>, <&dmac2 0x94>;
516 #size-cells = <0>;
519 reg = <0 0xe66d0000 0 0x40>;
524 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
532 #size-cells = <0>;
535 reg = <0 0xe66d8000 0 0x40>;
540 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
548 #size-cells = <0>;
551 reg = <0 0xe66e0000 0 0x40>;
556 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
564 #size-cells = <0>;
567 reg = <0 0xe66e8000 0 0x40>;
572 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
580 #size-cells = <0>;
583 reg = <0 0xe6690000 0 0x40>;
594 #size-cells = <0>;
598 reg = <0 0xe60b0000 0 0x425>;
603 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
612 reg = <0 0xe6540000 0 0x60>;
618 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
619 <&dmac2 0x31>, <&dmac2 0x30>;
630 reg = <0 0xe6550000 0 0x60>;
636 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
637 <&dmac2 0x33>, <&dmac2 0x32>;
648 reg = <0 0xe6560000 0 0x60>;
654 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
655 <&dmac2 0x35>, <&dmac2 0x34>;
666 reg = <0 0xe66a0000 0 0x60>;
672 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
683 reg = <0 0xe66b0000 0 0x60>;
689 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
699 reg = <0 0xe6590000 0 0x200>;
702 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
703 <&usb_dmac1 0>, <&usb_dmac1 1>;
716 reg = <0 0xe65a0000 0 0x100>;
730 reg = <0 0xe65b0000 0 0x100>;
744 reg = <0 0xe6700000 0 0x10000>;
773 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
786 reg = <0 0xe7300000 0 0x10000>;
815 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
828 reg = <0 0xe7310000 0 0x10000>;
869 reg = <0 0xe6740000 0 0x1000>;
870 renesas,ipmmu-main = <&ipmmu_mm 0>;
877 reg = <0 0xe7740000 0 0x1000>;
885 reg = <0 0xe6570000 0 0x1000>;
893 reg = <0 0xe67b0000 0 0x1000>;
902 reg = <0 0xec670000 0 0x1000>;
910 reg = <0 0xfd800000 0 0x1000>;
918 reg = <0 0xfe6b0000 0 0x1000>;
926 reg = <0 0xfebd0000 0 0x1000>;
934 reg = <0 0xfe990000 0 0x1000>;
943 reg = <0 0xe6800000 0 0x800>;
981 rx-internal-delay-ps = <0>;
984 #size-cells = <0>;
991 reg = <0 0xe6c30000 0 0x1000>;
1007 reg = <0 0xe6c38000 0 0x1000>;
1023 reg = <0 0xe66c0000 0 0x8000>;
1048 reg = <0 0xe6e30000 0 0x8>;
1058 reg = <0 0xe6e31000 0 0x8>;
1068 reg = <0 0xe6e32000 0 0x8>;
1078 reg = <0 0xe6e33000 0 0x8>;
1088 reg = <0 0xe6e34000 0 0x8>;
1098 reg = <0 0xe6e35000 0 0x8>;
1108 reg = <0 0xe6e36000 0 0x8>;
1119 reg = <0 0xe6e60000 0 64>;
1125 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1126 <&dmac2 0x51>, <&dmac2 0x50>;
1136 reg = <0 0xe6e68000 0 64>;
1142 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1143 <&dmac2 0x53>, <&dmac2 0x52>;
1153 reg = <0 0xe6e88000 0 64>;
1159 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1160 <&dmac2 0x13>, <&dmac2 0x12>;
1170 reg = <0 0xe6c50000 0 64>;
1176 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1186 reg = <0 0xe6c40000 0 64>;
1192 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1202 reg = <0 0xe6f30000 0 64>;
1208 dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
1218 reg = <0 0xe6e90000 0 0x0064>;
1221 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1222 <&dmac2 0x41>, <&dmac2 0x40>;
1227 #size-cells = <0>;
1234 reg = <0 0xe6ea0000 0 0x0064>;
1237 dmas = <&dmac0 0x43>, <&dmac0 0x42>;
1242 #size-cells = <0>;
1249 reg = <0 0xe6c00000 0 0x0064>;
1252 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1257 #size-cells = <0>;
1264 reg = <0 0xe6c10000 0 0x0064>;
1267 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1272 #size-cells = <0>;
1278 reg = <0 0xe6ef4000 0 0x1000>;
1288 #size-cells = <0>;
1292 #size-cells = <0>;
1306 reg = <0 0xe6ef5000 0 0x1000>;
1316 #size-cells = <0>;
1320 #size-cells = <0>;
1336 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1342 * clkout : #clock-cells = <0>; <&rcar_sound>;
1347 reg = <0 0xec500000 0 0x1000>, /* SCU */
1348 <0 0xec5a0000 0 0x100>, /* ADG */
1349 <0 0xec540000 0 0x1000>, /* SSIU */
1350 <0 0xec541000 0 0x280>, /* SSI */
1351 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1374 "ssi.1", "ssi.0",
1377 "src.1", "src.0",
1378 "mix.1", "mix.0",
1379 "ctu.1", "ctu.0",
1380 "dvc.0", "dvc.1",
1392 "ssi.1", "ssi.0";
1396 ctu00: ctu-0 { };
1407 dvc0: dvc-0 {
1408 dmas = <&audma0 0xbc>;
1412 dmas = <&audma0 0xbe>;
1418 mix0: mix-0 { };
1423 src0: src-0 {
1425 dmas = <&audma0 0x85>, <&audma0 0x9a>;
1430 dmas = <&audma0 0x87>, <&audma0 0x9c>;
1435 dmas = <&audma0 0x89>, <&audma0 0x9e>;
1440 dmas = <&audma0 0x8b>, <&audma0 0xa0>;
1445 dmas = <&audma0 0x8d>, <&audma0 0xb0>;
1450 dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1455 dmas = <&audma0 0x91>, <&audma0 0xb4>;
1460 dmas = <&audma0 0x93>, <&audma0 0xb6>;
1465 dmas = <&audma0 0x95>, <&audma0 0xb8>;
1470 dmas = <&audma0 0x97>, <&audma0 0xba>;
1476 ssi0: ssi-0 {
1478 dmas = <&audma0 0x01>, <&audma0 0x02>,
1479 <&audma0 0x15>, <&audma0 0x16>;
1484 dmas = <&audma0 0x03>, <&audma0 0x04>,
1485 <&audma0 0x49>, <&audma0 0x4a>;
1490 dmas = <&audma0 0x05>, <&audma0 0x06>,
1491 <&audma0 0x63>, <&audma0 0x64>;
1496 dmas = <&audma0 0x07>, <&audma0 0x08>,
1497 <&audma0 0x6f>, <&audma0 0x70>;
1502 dmas = <&audma0 0x09>, <&audma0 0x0a>,
1503 <&audma0 0x71>, <&audma0 0x72>;
1508 dmas = <&audma0 0x0b>, <&audma0 0x0c>,
1509 <&audma0 0x73>, <&audma0 0x74>;
1514 dmas = <&audma0 0x0d>, <&audma0 0x0e>,
1515 <&audma0 0x75>, <&audma0 0x76>;
1520 dmas = <&audma0 0x0f>, <&audma0 0x10>,
1521 <&audma0 0x79>, <&audma0 0x7a>;
1526 dmas = <&audma0 0x11>, <&audma0 0x12>,
1527 <&audma0 0x7b>, <&audma0 0x7c>;
1532 dmas = <&audma0 0x13>, <&audma0 0x14>,
1533 <&audma0 0x7d>, <&audma0 0x7e>;
1542 reg = <0 0xec700000 0 0x10000>;
1571 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
1584 reg = <0 0xee000000 0 0xc00>;
1595 reg = <0 0xee020000 0 0x400>;
1605 reg = <0 0xee080000 0 0x100>;
1617 reg = <0 0xee080100 0 0x100>;
1631 reg = <0 0xee080200 0 0x700>;
1643 reg = <0 0xee100000 0 0x2000>;
1657 reg = <0 0xee120000 0 0x2000>;
1671 reg = <0 0xee160000 0 0x2000>;
1685 reg = <0 0xee200000 0 0x200>,
1686 <0 0x08000000 0 0x4000000>,
1687 <0 0xee208000 0 0x100>;
1694 #size-cells = <0>;
1701 #address-cells = <0>;
1703 reg = <0x0 0xf1010000 0 0x1000>,
1704 <0x0 0xf1020000 0 0x20000>,
1705 <0x0 0xf1040000 0 0x20000>,
1706 <0x0 0xf1060000 0 0x20000>;
1718 reg = <0 0xfe000000 0 0x80000>;
1721 bus-range = <0x00 0xff>;
1723 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
1724 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
1725 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
1726 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1728 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
1733 interrupt-map-mask = <0 0 0 0>;
1734 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1739 iommu-map = <0 &ipmmu_hc 0 1>;
1740 iommu-map-mask = <0>;
1747 reg = <0x0 0xfe000000 0 0x80000>,
1748 <0x0 0xfe100000 0 0x100000>,
1749 <0x0 0xfe200000 0 0x200000>,
1750 <0x0 0x30000000 0 0x8000000>,
1751 <0x0 0x38000000 0 0x8000000>;
1765 reg = <0 0xfe960000 0 0x8000>;
1775 reg = <0 0xfea20000 0 0x7000>;
1785 reg = <0 0xfea28000 0 0x7000>;
1795 reg = <0 0xfe9a0000 0 0x8000>;
1805 reg = <0 0xfe96f000 0 0x200>;
1814 reg = <0 0xfea27000 0 0x200>;
1823 reg = <0 0xfea2f000 0 0x200>;
1832 reg = <0 0xfe9af000 0 0x200>;
1841 reg = <0 0xfeaa0000 0 0x10000>;
1850 #size-cells = <0>;
1852 port@0 {
1853 reg = <0>;
1858 #size-cells = <0>;
1862 csi40vin4: endpoint@0 {
1863 reg = <0>;
1876 reg = <0 0xfeb00000 0 0x40000>;
1880 clock-names = "du.0", "du.1";
1882 reset-names = "du.0";
1883 renesas,vsps = <&vspd0 0>, <&vspd1 0>;
1889 #size-cells = <0>;
1891 port@0 {
1892 reg = <0>;
1913 reg = <0 0xfeb90000 0 0x20>;
1923 #size-cells = <0>;
1925 port@0 {
1926 reg = <0>;
1940 reg = <0 0xfeb90100 0 0x20>;
1948 #size-cells = <0>;
1950 port@0 {
1951 reg = <0>;
1965 reg = <0 0xfff00044 0 4>;
1973 polling-delay = <0>;
1980 cooling-device = <&a53_0 0 2>;
2013 #clock-cells = <0>;
2014 clock-frequency = <0>;
2019 #clock-cells = <0>;
2020 clock-frequency = <0>;