Lines Matching +full:- +full:resets
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
8 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a774c0-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <0>;
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <0>;
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <0>;
40 /* External CAN clock - to be overridden by boards that provide it */
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
44 clock-frequency = <0>;
47 cluster1_opp: opp-table-1 {
48 compatible = "operating-points-v2";
49 opp-shared;
50 opp-800000000 {
51 opp-hz = /bits/ 64 <800000000>;
52 clock-latency-ns = <300000>;
54 opp-1000000000 {
55 opp-hz = /bits/ 64 <1000000000>;
56 clock-latency-ns = <300000>;
58 opp-1200000000 {
59 opp-hz = /bits/ 64 <1200000000>;
60 clock-latency-ns = <300000>;
61 opp-suspend;
66 #address-cells = <1>;
67 #size-cells = <0>;
70 compatible = "arm,cortex-a53";
73 #cooling-cells = <2>;
74 power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
75 next-level-cache = <&L2_CA53>;
76 enable-method = "psci";
77 dynamic-power-coefficient = <277>;
79 operating-points-v2 = <&cluster1_opp>;
83 compatible = "arm,cortex-a53";
86 power-domains = <&sysc R8A774C0_PD_CA53_CPU1>;
87 next-level-cache = <&L2_CA53>;
88 enable-method = "psci";
90 operating-points-v2 = <&cluster1_opp>;
93 L2_CA53: cache-controller-0 {
95 power-domains = <&sysc R8A774C0_PD_CA53_SCU>;
96 cache-unified;
97 cache-level = <2>;
102 compatible = "fixed-clock";
103 #clock-cells = <0>;
105 clock-frequency = <0>;
108 /* External PCIe clock - can be overridden by the board */
110 compatible = "fixed-clock";
111 #clock-cells = <0>;
112 clock-frequency = <0>;
116 compatible = "arm,cortex-a53-pmu";
117 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
119 interrupt-affinity = <&a53_0>, <&a53_1>;
123 compatible = "arm,psci-1.0", "arm,psci-0.2";
127 /* External SCIF clock - to be overridden by boards that provide it */
129 compatible = "fixed-clock";
130 #clock-cells = <0>;
131 clock-frequency = <0>;
135 compatible = "simple-bus";
136 interrupt-parent = <&gic>;
137 #address-cells = <2>;
138 #size-cells = <2>;
142 compatible = "renesas,r8a774c0-wdt",
143 "renesas,rcar-gen3-wdt";
147 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
148 resets = <&cpg 402>;
153 compatible = "renesas,gpio-r8a774c0",
154 "renesas,rcar-gen3-gpio";
157 #gpio-cells = <2>;
158 gpio-controller;
159 gpio-ranges = <&pfc 0 0 18>;
160 #interrupt-cells = <2>;
161 interrupt-controller;
163 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
164 resets = <&cpg 912>;
168 compatible = "renesas,gpio-r8a774c0",
169 "renesas,rcar-gen3-gpio";
172 #gpio-cells = <2>;
173 gpio-controller;
174 gpio-ranges = <&pfc 0 32 23>;
175 #interrupt-cells = <2>;
176 interrupt-controller;
178 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
179 resets = <&cpg 911>;
183 compatible = "renesas,gpio-r8a774c0",
184 "renesas,rcar-gen3-gpio";
187 #gpio-cells = <2>;
188 gpio-controller;
189 gpio-ranges = <&pfc 0 64 26>;
190 #interrupt-cells = <2>;
191 interrupt-controller;
193 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
194 resets = <&cpg 910>;
198 compatible = "renesas,gpio-r8a774c0",
199 "renesas,rcar-gen3-gpio";
202 #gpio-cells = <2>;
203 gpio-controller;
204 gpio-ranges = <&pfc 0 96 16>;
205 #interrupt-cells = <2>;
206 interrupt-controller;
208 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
209 resets = <&cpg 909>;
213 compatible = "renesas,gpio-r8a774c0",
214 "renesas,rcar-gen3-gpio";
217 #gpio-cells = <2>;
218 gpio-controller;
219 gpio-ranges = <&pfc 0 128 11>;
220 #interrupt-cells = <2>;
221 interrupt-controller;
223 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
224 resets = <&cpg 908>;
228 compatible = "renesas,gpio-r8a774c0",
229 "renesas,rcar-gen3-gpio";
232 #gpio-cells = <2>;
233 gpio-controller;
234 gpio-ranges = <&pfc 0 160 20>;
235 #interrupt-cells = <2>;
236 interrupt-controller;
238 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
239 resets = <&cpg 907>;
243 compatible = "renesas,gpio-r8a774c0",
244 "renesas,rcar-gen3-gpio";
247 #gpio-cells = <2>;
248 gpio-controller;
249 gpio-ranges = <&pfc 0 192 18>;
250 #interrupt-cells = <2>;
251 interrupt-controller;
253 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
254 resets = <&cpg 906>;
258 compatible = "renesas,pfc-r8a774c0";
263 compatible = "renesas,r8a774c0-cmt0",
264 "renesas,rcar-gen3-cmt0";
269 clock-names = "fck";
270 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
271 resets = <&cpg 303>;
276 compatible = "renesas,r8a774c0-cmt1",
277 "renesas,rcar-gen3-cmt1";
288 clock-names = "fck";
289 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
290 resets = <&cpg 302>;
295 compatible = "renesas,r8a774c0-cmt1",
296 "renesas,rcar-gen3-cmt1";
307 clock-names = "fck";
308 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
309 resets = <&cpg 301>;
314 compatible = "renesas,r8a774c0-cmt1",
315 "renesas,rcar-gen3-cmt1";
326 clock-names = "fck";
327 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
328 resets = <&cpg 300>;
332 cpg: clock-controller@e6150000 {
333 compatible = "renesas,r8a774c0-cpg-mssr";
336 clock-names = "extal";
337 #clock-cells = <2>;
338 #power-domain-cells = <0>;
339 #reset-cells = <1>;
342 rst: reset-controller@e6160000 {
343 compatible = "renesas,r8a774c0-rst";
347 sysc: system-controller@e6180000 {
348 compatible = "renesas,r8a774c0-sysc";
350 #power-domain-cells = <1>;
354 compatible = "renesas,thermal-r8a774c0";
360 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
361 resets = <&cpg 522>;
362 #thermal-sensor-cells = <0>;
365 intc_ex: interrupt-controller@e61c0000 {
366 compatible = "renesas,intc-ex-r8a774c0", "renesas,irqc";
367 #interrupt-cells = <2>;
368 interrupt-controller;
377 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
378 resets = <&cpg 407>;
382 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
387 interrupt-names = "tuni0", "tuni1", "tuni2";
389 clock-names = "fck";
390 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
391 resets = <&cpg 125>;
396 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
402 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
404 clock-names = "fck";
405 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
406 resets = <&cpg 124>;
411 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
417 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
419 clock-names = "fck";
420 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
421 resets = <&cpg 123>;
426 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
431 interrupt-names = "tuni0", "tuni1", "tuni2";
433 clock-names = "fck";
434 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
435 resets = <&cpg 122>;
440 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
445 interrupt-names = "tuni0", "tuni1", "tuni2";
447 clock-names = "fck";
448 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
449 resets = <&cpg 121>;
454 #address-cells = <1>;
455 #size-cells = <0>;
456 compatible = "renesas,i2c-r8a774c0",
457 "renesas,rcar-gen3-i2c";
461 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
462 resets = <&cpg 931>;
465 dma-names = "tx", "rx", "tx", "rx";
466 i2c-scl-internal-delay-ns = <110>;
471 #address-cells = <1>;
472 #size-cells = <0>;
473 compatible = "renesas,i2c-r8a774c0",
474 "renesas,rcar-gen3-i2c";
478 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
479 resets = <&cpg 930>;
482 dma-names = "tx", "rx", "tx", "rx";
483 i2c-scl-internal-delay-ns = <6>;
488 #address-cells = <1>;
489 #size-cells = <0>;
490 compatible = "renesas,i2c-r8a774c0",
491 "renesas,rcar-gen3-i2c";
495 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
496 resets = <&cpg 929>;
499 dma-names = "tx", "rx", "tx", "rx";
500 i2c-scl-internal-delay-ns = <6>;
505 #address-cells = <1>;
506 #size-cells = <0>;
507 compatible = "renesas,i2c-r8a774c0",
508 "renesas,rcar-gen3-i2c";
512 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
513 resets = <&cpg 928>;
515 dma-names = "tx", "rx";
516 i2c-scl-internal-delay-ns = <110>;
521 #address-cells = <1>;
522 #size-cells = <0>;
523 compatible = "renesas,i2c-r8a774c0",
524 "renesas,rcar-gen3-i2c";
528 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
529 resets = <&cpg 927>;
531 dma-names = "tx", "rx";
532 i2c-scl-internal-delay-ns = <6>;
537 #address-cells = <1>;
538 #size-cells = <0>;
539 compatible = "renesas,i2c-r8a774c0",
540 "renesas,rcar-gen3-i2c";
544 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
545 resets = <&cpg 919>;
547 dma-names = "tx", "rx";
548 i2c-scl-internal-delay-ns = <6>;
553 #address-cells = <1>;
554 #size-cells = <0>;
555 compatible = "renesas,i2c-r8a774c0",
556 "renesas,rcar-gen3-i2c";
560 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
561 resets = <&cpg 918>;
563 dma-names = "tx", "rx";
564 i2c-scl-internal-delay-ns = <6>;
569 #address-cells = <1>;
570 #size-cells = <0>;
571 compatible = "renesas,i2c-r8a774c0",
572 "renesas,rcar-gen3-i2c";
576 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
577 resets = <&cpg 1003>;
578 i2c-scl-internal-delay-ns = <6>;
583 #address-cells = <1>;
584 #size-cells = <0>;
585 compatible = "renesas,iic-r8a774c0",
586 "renesas,rcar-gen3-iic",
587 "renesas,rmobile-iic";
591 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
592 resets = <&cpg 926>;
594 dma-names = "tx", "rx";
599 compatible = "renesas,hscif-r8a774c0",
600 "renesas,rcar-gen3-hscif",
607 clock-names = "fck", "brg_int", "scif_clk";
610 dma-names = "tx", "rx", "tx", "rx";
611 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
612 resets = <&cpg 520>;
617 compatible = "renesas,hscif-r8a774c0",
618 "renesas,rcar-gen3-hscif",
625 clock-names = "fck", "brg_int", "scif_clk";
628 dma-names = "tx", "rx", "tx", "rx";
629 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
630 resets = <&cpg 519>;
635 compatible = "renesas,hscif-r8a774c0",
636 "renesas,rcar-gen3-hscif",
643 clock-names = "fck", "brg_int", "scif_clk";
646 dma-names = "tx", "rx", "tx", "rx";
647 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
648 resets = <&cpg 518>;
653 compatible = "renesas,hscif-r8a774c0",
654 "renesas,rcar-gen3-hscif",
661 clock-names = "fck", "brg_int", "scif_clk";
663 dma-names = "tx", "rx";
664 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
665 resets = <&cpg 517>;
670 compatible = "renesas,hscif-r8a774c0",
671 "renesas,rcar-gen3-hscif",
678 clock-names = "fck", "brg_int", "scif_clk";
680 dma-names = "tx", "rx";
681 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
682 resets = <&cpg 516>;
687 compatible = "renesas,usbhs-r8a774c0",
688 "renesas,rcar-gen3-usbhs";
694 dma-names = "ch0", "ch1", "ch2", "ch3";
697 phy-names = "usb";
698 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
699 resets = <&cpg 704>, <&cpg 703>;
703 usb_dmac0: dma-controller@e65a0000 {
704 compatible = "renesas,r8a774c0-usb-dmac",
705 "renesas,usb-dmac";
709 interrupt-names = "ch0", "ch1";
711 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
712 resets = <&cpg 330>;
713 #dma-cells = <1>;
714 dma-channels = <2>;
717 usb_dmac1: dma-controller@e65b0000 {
718 compatible = "renesas,r8a774c0-usb-dmac",
719 "renesas,usb-dmac";
723 interrupt-names = "ch0", "ch1";
725 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
726 resets = <&cpg 331>;
727 #dma-cells = <1>;
728 dma-channels = <2>;
731 dmac0: dma-controller@e6700000 {
732 compatible = "renesas,dmac-r8a774c0",
733 "renesas,rcar-dmac";
752 interrupt-names = "error",
758 clock-names = "fck";
759 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
760 resets = <&cpg 219>;
761 #dma-cells = <1>;
762 dma-channels = <16>;
773 dmac1: dma-controller@e7300000 {
774 compatible = "renesas,dmac-r8a774c0",
775 "renesas,rcar-dmac";
794 interrupt-names = "error",
800 clock-names = "fck";
801 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
802 resets = <&cpg 218>;
803 #dma-cells = <1>;
804 dma-channels = <16>;
815 dmac2: dma-controller@e7310000 {
816 compatible = "renesas,dmac-r8a774c0",
817 "renesas,rcar-dmac";
836 interrupt-names = "error",
842 clock-names = "fck";
843 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
844 resets = <&cpg 217>;
845 #dma-cells = <1>;
846 dma-channels = <16>;
858 compatible = "renesas,ipmmu-r8a774c0";
860 renesas,ipmmu-main = <&ipmmu_mm 0>;
861 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
862 #iommu-cells = <1>;
866 compatible = "renesas,ipmmu-r8a774c0";
868 renesas,ipmmu-main = <&ipmmu_mm 1>;
869 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
870 #iommu-cells = <1>;
874 compatible = "renesas,ipmmu-r8a774c0";
876 renesas,ipmmu-main = <&ipmmu_mm 2>;
877 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
878 #iommu-cells = <1>;
882 compatible = "renesas,ipmmu-r8a774c0";
886 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
887 #iommu-cells = <1>;
891 compatible = "renesas,ipmmu-r8a774c0";
893 renesas,ipmmu-main = <&ipmmu_mm 4>;
894 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
895 #iommu-cells = <1>;
899 compatible = "renesas,ipmmu-r8a774c0";
901 renesas,ipmmu-main = <&ipmmu_mm 6>;
902 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
903 #iommu-cells = <1>;
907 compatible = "renesas,ipmmu-r8a774c0";
909 renesas,ipmmu-main = <&ipmmu_mm 12>;
910 power-domains = <&sysc R8A774C0_PD_A3VC>;
911 #iommu-cells = <1>;
915 compatible = "renesas,ipmmu-r8a774c0";
917 renesas,ipmmu-main = <&ipmmu_mm 14>;
918 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
919 #iommu-cells = <1>;
923 compatible = "renesas,ipmmu-r8a774c0";
925 renesas,ipmmu-main = <&ipmmu_mm 16>;
926 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
927 #iommu-cells = <1>;
931 compatible = "renesas,etheravb-r8a774c0",
932 "renesas,etheravb-rcar-gen3";
959 interrupt-names = "ch0", "ch1", "ch2", "ch3",
967 clock-names = "fck";
968 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
969 resets = <&cpg 812>;
970 phy-mode = "rgmii";
971 rx-internal-delay-ps = <0>;
973 #address-cells = <1>;
974 #size-cells = <0>;
979 compatible = "renesas,can-r8a774c0",
980 "renesas,rcar-gen3-can";
986 clock-names = "clkp1", "clkp2", "can_clk";
987 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
988 assigned-clock-rates = <40000000>;
989 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
990 resets = <&cpg 916>;
995 compatible = "renesas,can-r8a774c0",
996 "renesas,rcar-gen3-can";
1002 clock-names = "clkp1", "clkp2", "can_clk";
1003 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
1004 assigned-clock-rates = <40000000>;
1005 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1006 resets = <&cpg 915>;
1011 compatible = "renesas,r8a774c0-canfd",
1012 "renesas,rcar-gen3-canfd";
1016 interrupt-names = "ch_int", "g_int";
1020 clock-names = "fck", "canfd", "can_clk";
1021 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
1022 assigned-clock-rates = <40000000>;
1023 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1024 resets = <&cpg 914>;
1037 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1040 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1041 resets = <&cpg 523>;
1042 #pwm-cells = <2>;
1047 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1050 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1051 resets = <&cpg 523>;
1052 #pwm-cells = <2>;
1057 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1060 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1061 resets = <&cpg 523>;
1062 #pwm-cells = <2>;
1067 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1070 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1071 resets = <&cpg 523>;
1072 #pwm-cells = <2>;
1077 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1080 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1081 resets = <&cpg 523>;
1082 #pwm-cells = <2>;
1087 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1090 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1091 resets = <&cpg 523>;
1092 #pwm-cells = <2>;
1097 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1100 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1101 resets = <&cpg 523>;
1102 #pwm-cells = <2>;
1107 compatible = "renesas,scif-r8a774c0",
1108 "renesas,rcar-gen3-scif", "renesas,scif";
1114 clock-names = "fck", "brg_int", "scif_clk";
1117 dma-names = "tx", "rx", "tx", "rx";
1118 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1119 resets = <&cpg 207>;
1124 compatible = "renesas,scif-r8a774c0",
1125 "renesas,rcar-gen3-scif", "renesas,scif";
1131 clock-names = "fck", "brg_int", "scif_clk";
1134 dma-names = "tx", "rx", "tx", "rx";
1135 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1136 resets = <&cpg 206>;
1141 compatible = "renesas,scif-r8a774c0",
1142 "renesas,rcar-gen3-scif", "renesas,scif";
1148 clock-names = "fck", "brg_int", "scif_clk";
1151 dma-names = "tx", "rx", "tx", "rx";
1152 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1153 resets = <&cpg 310>;
1158 compatible = "renesas,scif-r8a774c0",
1159 "renesas,rcar-gen3-scif", "renesas,scif";
1165 clock-names = "fck", "brg_int", "scif_clk";
1167 dma-names = "tx", "rx";
1168 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1169 resets = <&cpg 204>;
1174 compatible = "renesas,scif-r8a774c0",
1175 "renesas,rcar-gen3-scif", "renesas,scif";
1181 clock-names = "fck", "brg_int", "scif_clk";
1183 dma-names = "tx", "rx";
1184 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1185 resets = <&cpg 203>;
1190 compatible = "renesas,scif-r8a774c0",
1191 "renesas,rcar-gen3-scif", "renesas,scif";
1197 clock-names = "fck", "brg_int", "scif_clk";
1199 dma-names = "tx", "rx";
1200 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1201 resets = <&cpg 202>;
1206 compatible = "renesas,msiof-r8a774c0",
1207 "renesas,rcar-gen3-msiof";
1213 dma-names = "tx", "rx", "tx", "rx";
1214 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1215 resets = <&cpg 211>;
1216 #address-cells = <1>;
1217 #size-cells = <0>;
1222 compatible = "renesas,msiof-r8a774c0",
1223 "renesas,rcar-gen3-msiof";
1228 dma-names = "tx", "rx";
1229 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1230 resets = <&cpg 210>;
1231 #address-cells = <1>;
1232 #size-cells = <0>;
1237 compatible = "renesas,msiof-r8a774c0",
1238 "renesas,rcar-gen3-msiof";
1243 dma-names = "tx", "rx";
1244 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1245 resets = <&cpg 209>;
1246 #address-cells = <1>;
1247 #size-cells = <0>;
1252 compatible = "renesas,msiof-r8a774c0",
1253 "renesas,rcar-gen3-msiof";
1258 dma-names = "tx", "rx";
1259 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1260 resets = <&cpg 208>;
1261 #address-cells = <1>;
1262 #size-cells = <0>;
1267 compatible = "renesas,vin-r8a774c0";
1271 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1272 resets = <&cpg 807>;
1277 #address-cells = <1>;
1278 #size-cells = <0>;
1281 #address-cells = <1>;
1282 #size-cells = <0>;
1288 remote-endpoint = <&csi40vin4>;
1295 compatible = "renesas,vin-r8a774c0";
1299 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1300 resets = <&cpg 806>;
1305 #address-cells = <1>;
1306 #size-cells = <0>;
1309 #address-cells = <1>;
1310 #size-cells = <0>;
1316 remote-endpoint = <&csi40vin5>;
1324 * #sound-dai-cells is required if simple-card
1326 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1327 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1330 * #clock-cells is required for audio_clkout0/1/2/3
1332 * clkout : #clock-cells = <0>; <&rcar_sound>;
1333 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1335 compatible = "renesas,rcar_sound-r8a774c0",
1336 "renesas,rcar_sound-gen3";
1342 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1361 clock-names = "ssi-all",
1372 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1373 resets = <&cpg 1005>,
1379 reset-names = "ssi-all",
1386 ctu00: ctu-0 { };
1387 ctu01: ctu-1 { };
1388 ctu02: ctu-2 { };
1389 ctu03: ctu-3 { };
1390 ctu10: ctu-4 { };
1391 ctu11: ctu-5 { };
1392 ctu12: ctu-6 { };
1393 ctu13: ctu-7 { };
1397 dvc0: dvc-0 {
1399 dma-names = "tx";
1401 dvc1: dvc-1 {
1403 dma-names = "tx";
1408 mix0: mix-0 { };
1409 mix1: mix-1 { };
1413 src0: src-0 {
1416 dma-names = "rx", "tx";
1418 src1: src-1 {
1421 dma-names = "rx", "tx";
1423 src2: src-2 {
1426 dma-names = "rx", "tx";
1428 src3: src-3 {
1431 dma-names = "rx", "tx";
1433 src4: src-4 {
1436 dma-names = "rx", "tx";
1438 src5: src-5 {
1441 dma-names = "rx", "tx";
1443 src6: src-6 {
1446 dma-names = "rx", "tx";
1448 src7: src-7 {
1451 dma-names = "rx", "tx";
1453 src8: src-8 {
1456 dma-names = "rx", "tx";
1458 src9: src-9 {
1461 dma-names = "rx", "tx";
1466 ssi0: ssi-0 {
1470 dma-names = "rx", "tx", "rxu", "txu";
1472 ssi1: ssi-1 {
1476 dma-names = "rx", "tx", "rxu", "txu";
1478 ssi2: ssi-2 {
1482 dma-names = "rx", "tx", "rxu", "txu";
1484 ssi3: ssi-3 {
1488 dma-names = "rx", "tx", "rxu", "txu";
1490 ssi4: ssi-4 {
1494 dma-names = "rx", "tx", "rxu", "txu";
1496 ssi5: ssi-5 {
1500 dma-names = "rx", "tx", "rxu", "txu";
1502 ssi6: ssi-6 {
1506 dma-names = "rx", "tx", "rxu", "txu";
1508 ssi7: ssi-7 {
1512 dma-names = "rx", "tx", "rxu", "txu";
1514 ssi8: ssi-8 {
1518 dma-names = "rx", "tx", "rxu", "txu";
1520 ssi9: ssi-9 {
1524 dma-names = "rx", "tx", "rxu", "txu";
1529 audma0: dma-controller@ec700000 {
1530 compatible = "renesas,dmac-r8a774c0",
1531 "renesas,rcar-dmac";
1550 interrupt-names = "error",
1556 clock-names = "fck";
1557 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1558 resets = <&cpg 502>;
1559 #dma-cells = <1>;
1560 dma-channels = <16>;
1572 compatible = "renesas,xhci-r8a774c0",
1573 "renesas,rcar-gen3-xhci";
1577 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1578 resets = <&cpg 328>;
1583 compatible = "renesas,r8a774c0-usb3-peri",
1584 "renesas,rcar-gen3-usb3-peri";
1588 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1589 resets = <&cpg 328>;
1594 compatible = "generic-ohci";
1599 phy-names = "usb";
1600 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1601 resets = <&cpg 703>, <&cpg 704>;
1606 compatible = "generic-ehci";
1611 phy-names = "usb";
1613 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1614 resets = <&cpg 703>, <&cpg 704>;
1618 usb2_phy0: usb-phy@ee080200 {
1619 compatible = "renesas,usb2-phy-r8a774c0",
1620 "renesas,rcar-gen3-usb2-phy";
1624 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1625 resets = <&cpg 703>, <&cpg 704>;
1626 #phy-cells = <1>;
1631 compatible = "renesas,sdhi-r8a774c0",
1632 "renesas,rcar-gen3-sdhi";
1636 clock-names = "core", "clkh";
1637 max-frequency = <200000000>;
1638 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1639 resets = <&cpg 314>;
1645 compatible = "renesas,sdhi-r8a774c0",
1646 "renesas,rcar-gen3-sdhi";
1650 clock-names = "core", "clkh";
1651 max-frequency = <200000000>;
1652 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1653 resets = <&cpg 313>;
1659 compatible = "renesas,sdhi-r8a774c0",
1660 "renesas,rcar-gen3-sdhi";
1664 clock-names = "core", "clkh";
1665 max-frequency = <200000000>;
1666 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1667 resets = <&cpg 311>;
1673 compatible = "renesas,r8a774c0-rpc-if",
1674 "renesas,rcar-gen3-rpc-if";
1678 reg-names = "regs", "dirmap", "wbuf";
1681 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1682 resets = <&cpg 917>;
1683 #address-cells = <1>;
1684 #size-cells = <0>;
1688 gic: interrupt-controller@f1010000 {
1689 compatible = "arm,gic-400";
1690 #interrupt-cells = <3>;
1691 #address-cells = <0>;
1692 interrupt-controller;
1700 clock-names = "clk";
1701 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1702 resets = <&cpg 408>;
1706 compatible = "renesas,pcie-r8a774c0",
1707 "renesas,pcie-rcar-gen3";
1709 #address-cells = <3>;
1710 #size-cells = <2>;
1711 bus-range = <0x00 0xff>;
1718 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
1722 #interrupt-cells = <1>;
1723 interrupt-map-mask = <0 0 0 0>;
1724 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1726 clock-names = "pcie", "pcie_bus";
1727 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1728 resets = <&cpg 319>;
1729 iommu-map = <0 &ipmmu_hc 0 1>;
1730 iommu-map-mask = <0>;
1734 pciec0_ep: pcie-ep@fe000000 {
1735 compatible = "renesas,r8a774c0-pcie-ep",
1736 "renesas,rcar-gen3-pcie-ep";
1742 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
1747 clock-names = "pcie";
1748 resets = <&cpg 319>;
1749 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1758 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1759 resets = <&cpg 626>;
1768 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1769 resets = <&cpg 623>;
1778 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1779 resets = <&cpg 622>;
1788 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1789 resets = <&cpg 631>;
1797 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1798 resets = <&cpg 607>;
1806 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1807 resets = <&cpg 603>;
1815 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1816 resets = <&cpg 602>;
1824 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1825 resets = <&cpg 611>;
1830 compatible = "renesas,r8a774c0-csi2";
1834 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1835 resets = <&cpg 716>;
1839 #address-cells = <1>;
1840 #size-cells = <0>;
1847 #address-cells = <1>;
1848 #size-cells = <0>;
1854 remote-endpoint = <&vin4csi40>;
1858 remote-endpoint = <&vin5csi40>;
1865 compatible = "renesas,du-r8a774c0";
1870 clock-names = "du.0", "du.1";
1871 resets = <&cpg 724>;
1872 reset-names = "du.0";
1878 #address-cells = <1>;
1879 #size-cells = <0>;
1888 remote-endpoint = <&lvds0_in>;
1895 remote-endpoint = <&lvds1_in>;
1901 lvds0: lvds-encoder@feb90000 {
1902 compatible = "renesas,r8a774c0-lvds";
1905 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1906 resets = <&cpg 727>;
1912 #address-cells = <1>;
1913 #size-cells = <0>;
1918 remote-endpoint = <&du_out_lvds0>;
1928 lvds1: lvds-encoder@feb90100 {
1929 compatible = "renesas,r8a774c0-lvds";
1932 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1933 resets = <&cpg 726>;
1937 #address-cells = <1>;
1938 #size-cells = <0>;
1943 remote-endpoint = <&du_out_lvds1>;
1959 thermal-zones {
1960 cpu-thermal {
1961 polling-delay-passive = <250>;
1962 polling-delay = <0>;
1963 thermal-sensors = <&thermal>;
1964 sustainable-power = <717>;
1966 cooling-maps {
1969 cooling-device = <&a53_0 0 2>;
1975 sensor1_crit: sensor1-crit {
1981 target: trip-point1 {
1991 compatible = "arm,armv8-timer";
1992 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1996 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
1999 /* External USB clocks - can be overridden by the board */
2001 compatible = "fixed-clock";
2002 #clock-cells = <0>;
2003 clock-frequency = <0>;
2007 compatible = "fixed-clock";
2008 #clock-cells = <0>;
2009 clock-frequency = <0>;