Lines Matching +full:0 +full:xfead0000
19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
45 clock-frequency = <0>;
48 cluster0_opp: opp-table-0 {
72 #size-cells = <0>;
74 a57_0: cpu@0 {
76 reg = <0x0>;
89 reg = <0x1>;
98 L2_CA57: cache-controller-0 {
108 #clock-cells = <0>;
110 clock-frequency = <0>;
116 #clock-cells = <0>;
118 clock-frequency = <0>;
125 #clock-cells = <0>;
126 clock-frequency = <0>;
144 #clock-cells = <0>;
145 clock-frequency = <0>;
160 reg = <0 0xe6020000 0 0x0c>;
171 reg = <0 0xe6050000 0 0x50>;
175 gpio-ranges = <&pfc 0 0 16>;
186 reg = <0 0xe6051000 0 0x50>;
190 gpio-ranges = <&pfc 0 32 29>;
201 reg = <0 0xe6052000 0 0x50>;
205 gpio-ranges = <&pfc 0 64 15>;
216 reg = <0 0xe6053000 0 0x50>;
220 gpio-ranges = <&pfc 0 96 16>;
231 reg = <0 0xe6054000 0 0x50>;
235 gpio-ranges = <&pfc 0 128 18>;
246 reg = <0 0xe6055000 0 0x50>;
250 gpio-ranges = <&pfc 0 160 26>;
261 reg = <0 0xe6055400 0 0x50>;
265 gpio-ranges = <&pfc 0 192 32>;
276 reg = <0 0xe6055800 0 0x50>;
280 gpio-ranges = <&pfc 0 224 4>;
290 reg = <0 0xe6060000 0 0x50c>;
297 reg = <0 0xe60f0000 0 0x1004>;
310 reg = <0 0xe6130000 0 0x1004>;
329 reg = <0 0xe6140000 0 0x1004>;
348 reg = <0 0xe6148000 0 0x1004>;
366 reg = <0 0xe6150000 0 0x1000>;
370 #power-domain-cells = <0>;
377 reg = <0 0xe6160000 0 0x0200>;
383 reg = <0 0xe6180000 0 0x0400>;
389 reg = <0 0xe6198000 0 0x100>,
390 <0 0xe61a0000 0 0x100>,
391 <0 0xe61a8000 0 0x100>;
405 reg = <0 0xe61c0000 0 0x200>;
406 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
419 reg = <0 0xe61e0000 0 0x30>;
433 reg = <0 0xe6fc0000 0 0x30>;
448 reg = <0 0xe6fd0000 0 0x30>;
463 reg = <0 0xe6fe0000 0 0x30>;
477 reg = <0 0xffc00000 0 0x30>;
491 #size-cells = <0>;
494 reg = <0 0xe6500000 0 0x40>;
499 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
500 <&dmac2 0x91>, <&dmac2 0x90>;
508 #size-cells = <0>;
511 reg = <0 0xe6508000 0 0x40>;
516 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
517 <&dmac2 0x93>, <&dmac2 0x92>;
525 #size-cells = <0>;
528 reg = <0 0xe6510000 0 0x40>;
533 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
534 <&dmac2 0x95>, <&dmac2 0x94>;
542 #size-cells = <0>;
545 reg = <0 0xe66d0000 0 0x40>;
550 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
558 #size-cells = <0>;
561 reg = <0 0xe66d8000 0 0x40>;
566 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
574 #size-cells = <0>;
577 reg = <0 0xe66e0000 0 0x40>;
582 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
590 #size-cells = <0>;
593 reg = <0 0xe66e8000 0 0x40>;
598 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
606 #size-cells = <0>;
610 reg = <0 0xe60b0000 0 0x425>;
615 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
624 reg = <0 0xe6540000 0 0x60>;
630 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
631 <&dmac2 0x31>, <&dmac2 0x30>;
642 reg = <0 0xe6550000 0 0x60>;
648 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
649 <&dmac2 0x33>, <&dmac2 0x32>;
660 reg = <0 0xe6560000 0 0x60>;
666 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
667 <&dmac2 0x35>, <&dmac2 0x34>;
678 reg = <0 0xe66a0000 0 0x60>;
684 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
695 reg = <0 0xe66b0000 0 0x60>;
701 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
711 reg = <0 0xe6590000 0 0x200>;
714 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
715 <&usb_dmac1 0>, <&usb_dmac1 1>;
728 reg = <0 0xe6590630 0 0x02>;
733 #clock-cells = <0>;
743 reg = <0 0xe65a0000 0 0x100>;
757 reg = <0 0xe65b0000 0 0x100>;
771 reg = <0 0xe65ee000 0 0x90>;
777 #phy-cells = <0>;
784 reg = <0 0xe6700000 0 0x10000>;
813 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
826 reg = <0 0xe7300000 0 0x10000>;
855 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
868 reg = <0 0xe7310000 0 0x10000>;
909 reg = <0 0xe6740000 0 0x1000>;
910 renesas,ipmmu-main = <&ipmmu_mm 0>;
917 reg = <0 0xe7740000 0 0x1000>;
925 reg = <0 0xe6570000 0 0x1000>;
933 reg = <0 0xe67b0000 0 0x1000>;
942 reg = <0 0xec670000 0 0x1000>;
950 reg = <0 0xfd800000 0 0x1000>;
958 reg = <0 0xfe6b0000 0 0x1000>;
966 reg = <0 0xfebd0000 0 0x1000>;
974 reg = <0 0xfe990000 0 0x1000>;
983 reg = <0 0xe6800000 0 0x800>;
1021 rx-internal-delay-ps = <0>;
1022 tx-internal-delay-ps = <0>;
1025 #size-cells = <0>;
1032 reg = <0 0xe6c30000 0 0x1000>;
1048 reg = <0 0xe6c38000 0 0x1000>;
1064 reg = <0 0xe66c0000 0 0x8000>;
1089 reg = <0 0xe6e30000 0 0x8>;
1099 reg = <0 0xe6e31000 0 0x8>;
1109 reg = <0 0xe6e32000 0 0x8>;
1119 reg = <0 0xe6e33000 0 0x8>;
1129 reg = <0 0xe6e34000 0 0x8>;
1139 reg = <0 0xe6e35000 0 0x8>;
1149 reg = <0 0xe6e36000 0 0x8>;
1160 reg = <0 0xe6e60000 0 0x40>;
1166 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1167 <&dmac2 0x51>, <&dmac2 0x50>;
1177 reg = <0 0xe6e68000 0 0x40>;
1183 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1184 <&dmac2 0x53>, <&dmac2 0x52>;
1194 reg = <0 0xe6e88000 0 0x40>;
1200 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1201 <&dmac2 0x13>, <&dmac2 0x12>;
1211 reg = <0 0xe6c50000 0 0x40>;
1217 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1227 reg = <0 0xe6c40000 0 0x40>;
1233 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1243 reg = <0 0xe6f30000 0 0x40>;
1249 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1250 <&dmac2 0x5b>, <&dmac2 0x5a>;
1260 reg = <0 0xe6e90000 0 0x0064>;
1263 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1264 <&dmac2 0x41>, <&dmac2 0x40>;
1269 #size-cells = <0>;
1276 reg = <0 0xe6ea0000 0 0x0064>;
1279 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1280 <&dmac2 0x43>, <&dmac2 0x42>;
1285 #size-cells = <0>;
1292 reg = <0 0xe6c00000 0 0x0064>;
1295 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1300 #size-cells = <0>;
1307 reg = <0 0xe6c10000 0 0x0064>;
1310 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1315 #size-cells = <0>;
1321 reg = <0 0xe6ef0000 0 0x1000>;
1326 renesas,id = <0>;
1331 #size-cells = <0>;
1335 #size-cells = <0>;
1339 vin0csi20: endpoint@0 {
1340 reg = <0>;
1353 reg = <0 0xe6ef1000 0 0x1000>;
1363 #size-cells = <0>;
1367 #size-cells = <0>;
1371 vin1csi20: endpoint@0 {
1372 reg = <0>;
1385 reg = <0 0xe6ef2000 0 0x1000>;
1395 #size-cells = <0>;
1399 #size-cells = <0>;
1403 vin2csi20: endpoint@0 {
1404 reg = <0>;
1417 reg = <0 0xe6ef3000 0 0x1000>;
1427 #size-cells = <0>;
1431 #size-cells = <0>;
1435 vin3csi20: endpoint@0 {
1436 reg = <0>;
1449 reg = <0 0xe6ef4000 0 0x1000>;
1459 #size-cells = <0>;
1463 #size-cells = <0>;
1467 vin4csi20: endpoint@0 {
1468 reg = <0>;
1481 reg = <0 0xe6ef5000 0 0x1000>;
1491 #size-cells = <0>;
1495 #size-cells = <0>;
1499 vin5csi20: endpoint@0 {
1500 reg = <0>;
1513 reg = <0 0xe6ef6000 0 0x1000>;
1523 #size-cells = <0>;
1527 #size-cells = <0>;
1531 vin6csi20: endpoint@0 {
1532 reg = <0>;
1545 reg = <0 0xe6ef7000 0 0x1000>;
1555 #size-cells = <0>;
1559 #size-cells = <0>;
1563 vin7csi20: endpoint@0 {
1564 reg = <0>;
1579 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1585 * clkout : #clock-cells = <0>; <&rcar_sound>;
1589 reg = <0 0xec500000 0 0x1000>, /* SCU */
1590 <0 0xec5a0000 0 0x100>, /* ADG */
1591 <0 0xec540000 0 0x1000>, /* SSIU */
1592 <0 0xec541000 0 0x280>, /* SSI */
1593 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1616 "ssi.1", "ssi.0",
1619 "src.1", "src.0",
1620 "mix.1", "mix.0",
1621 "ctu.1", "ctu.0",
1622 "dvc.0", "dvc.1",
1634 "ssi.1", "ssi.0";
1638 ctu00: ctu-0 { };
1649 dvc0: dvc-0 {
1650 dmas = <&audma1 0xbc>;
1654 dmas = <&audma1 0xbe>;
1660 mix0: mix-0 { };
1665 src0: src-0 {
1667 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1672 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1677 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1682 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1687 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1692 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1697 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1702 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1707 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1712 dmas = <&audma0 0x97>, <&audma1 0xba>;
1718 ssi0: ssi-0 {
1720 dmas = <&audma0 0x01>, <&audma1 0x02>;
1725 dmas = <&audma0 0x03>, <&audma1 0x04>;
1730 dmas = <&audma0 0x05>, <&audma1 0x06>;
1735 dmas = <&audma0 0x07>, <&audma1 0x08>;
1740 dmas = <&audma0 0x09>, <&audma1 0x0a>;
1745 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
1750 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
1755 dmas = <&audma0 0x0f>, <&audma1 0x10>;
1760 dmas = <&audma0 0x11>, <&audma1 0x12>;
1765 dmas = <&audma0 0x13>, <&audma1 0x14>;
1771 ssiu00: ssiu-0 {
1772 dmas = <&audma0 0x15>, <&audma1 0x16>;
1776 dmas = <&audma0 0x35>, <&audma1 0x36>;
1780 dmas = <&audma0 0x37>, <&audma1 0x38>;
1784 dmas = <&audma0 0x47>, <&audma1 0x48>;
1788 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1792 dmas = <&audma0 0x43>, <&audma1 0x44>;
1796 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1800 dmas = <&audma0 0x53>, <&audma1 0x54>;
1804 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1808 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1812 dmas = <&audma0 0x57>, <&audma1 0x58>;
1816 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1820 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1824 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1828 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1832 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1836 dmas = <&audma0 0x63>, <&audma1 0x64>;
1840 dmas = <&audma0 0x67>, <&audma1 0x68>;
1844 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
1848 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
1852 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
1856 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
1860 dmas = <&audma0 0xED>, <&audma1 0xEE>;
1864 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
1868 dmas = <&audma0 0x6f>, <&audma1 0x70>;
1872 dmas = <&audma0 0x21>, <&audma1 0x22>;
1876 dmas = <&audma0 0x23>, <&audma1 0x24>;
1880 dmas = <&audma0 0x25>, <&audma1 0x26>;
1884 dmas = <&audma0 0x27>, <&audma1 0x28>;
1888 dmas = <&audma0 0x29>, <&audma1 0x2A>;
1892 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
1896 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
1900 dmas = <&audma0 0x71>, <&audma1 0x72>;
1904 dmas = <&audma0 0x17>, <&audma1 0x18>;
1908 dmas = <&audma0 0x19>, <&audma1 0x1A>;
1912 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
1916 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
1920 dmas = <&audma0 0x1F>, <&audma1 0x20>;
1924 dmas = <&audma0 0x31>, <&audma1 0x32>;
1928 dmas = <&audma0 0x33>, <&audma1 0x34>;
1932 dmas = <&audma0 0x73>, <&audma1 0x74>;
1936 dmas = <&audma0 0x75>, <&audma1 0x76>;
1940 dmas = <&audma0 0x79>, <&audma1 0x7a>;
1944 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
1948 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
1952 dmas = <&audma0 0x7F>, <&audma1 0x80>;
1956 dmas = <&audma0 0x81>, <&audma1 0x82>;
1960 dmas = <&audma0 0x83>, <&audma1 0x84>;
1964 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
1968 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
1972 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
1976 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
1985 reg = <0 0xec700000 0 0x10000>;
2014 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
2027 reg = <0 0xec720000 0 0x10000>;
2069 reg = <0 0xee000000 0 0xc00>;
2080 reg = <0 0xee020000 0 0x400>;
2090 reg = <0 0xee080000 0 0x100>;
2102 reg = <0 0xee0a0000 0 0x100>;
2114 reg = <0 0xee080100 0 0x100>;
2127 reg = <0 0xee0a0100 0 0x100>;
2141 reg = <0 0xee080200 0 0x700>;
2153 reg = <0 0xee0a0200 0 0x700>;
2164 reg = <0 0xee100000 0 0x2000>;
2178 reg = <0 0xee120000 0 0x2000>;
2192 reg = <0 0xee140000 0 0x2000>;
2206 reg = <0 0xee160000 0 0x2000>;
2220 reg = <0 0xee200000 0 0x200>,
2221 <0 0x08000000 0 0x4000000>,
2222 <0 0xee208000 0 0x100>;
2229 #size-cells = <0>;
2236 reg = <0 0xee300000 0 0x200000>;
2248 #address-cells = <0>;
2250 reg = <0x0 0xf1010000 0 0x1000>,
2251 <0x0 0xf1020000 0 0x20000>,
2252 <0x0 0xf1040000 0 0x20000>,
2253 <0x0 0xf1060000 0 0x20000>;
2265 reg = <0 0xfe000000 0 0x80000>;
2268 bus-range = <0x00 0xff>;
2270 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2271 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2272 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2273 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2275 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2280 interrupt-map-mask = <0 0 0 0>;
2281 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2286 iommu-map = <0 &ipmmu_hc 0 1>;
2287 iommu-map-mask = <0>;
2294 reg = <0 0xee800000 0 0x80000>;
2297 bus-range = <0x00 0xff>;
2299 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2300 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2301 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2302 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2304 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2309 interrupt-map-mask = <0 0 0 0>;
2310 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2315 iommu-map = <0 &ipmmu_hc 1 1>;
2316 iommu-map-mask = <0>;
2323 reg = <0x0 0xfe000000 0 0x80000>,
2324 <0x0 0xfe100000 0 0x100000>,
2325 <0x0 0xfe200000 0 0x200000>,
2326 <0x0 0x30000000 0 0x8000000>,
2327 <0x0 0x38000000 0 0x8000000>;
2342 reg = <0x0 0xee800000 0 0x80000>,
2343 <0x0 0xee900000 0 0x100000>,
2344 <0x0 0xeea00000 0 0x200000>,
2345 <0x0 0xc0000000 0 0x8000000>,
2346 <0x0 0xc8000000 0 0x8000000>;
2360 reg = <0 0xfe940000 0 0x2400>;
2370 reg = <0 0xfe950000 0 0x200>;
2374 iommus = <&ipmmu_vp0 0>;
2379 reg = <0 0xfe960000 0 0x8000>;
2390 reg = <0 0xfe9a0000 0 0x8000>;
2401 reg = <0 0xfea20000 0 0x5000>;
2412 reg = <0 0xfea28000 0 0x5000>;
2423 reg = <0 0xfe96f000 0 0x200>;
2432 reg = <0 0xfea27000 0 0x200>;
2441 reg = <0 0xfea2f000 0 0x200>;
2450 reg = <0 0xfe9af000 0 0x200>;
2459 reg = <0 0xfea80000 0 0x10000>;
2468 #size-cells = <0>;
2470 port@0 {
2471 reg = <0>;
2476 #size-cells = <0>;
2480 csi20vin0: endpoint@0 {
2481 reg = <0>;
2518 reg = <0 0xfeaa0000 0 0x10000>;
2527 #size-cells = <0>;
2529 port@0 {
2530 reg = <0>;
2535 #size-cells = <0>;
2539 csi40vin0: endpoint@0 {
2540 reg = <0>;
2578 reg = <0 0xfead0000 0 0x10000>;
2589 #size-cells = <0>;
2591 port@0 {
2592 reg = <0>;
2609 reg = <0 0xfeb00000 0 0x80000>;
2615 clock-names = "du.0", "du.1", "du.3";
2617 reset-names = "du.0", "du.3";
2620 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
2624 #size-cells = <0>;
2626 port@0 {
2627 reg = <0>;
2646 reg = <0 0xfeb90000 0 0x14>;
2654 #size-cells = <0>;
2656 port@0 {
2657 reg = <0>;
2670 reg = <0 0xfff00044 0 4>;
2679 thermal-sensors = <&tsc 0>;
2715 cooling-device = <&a57_0 0 2>;
2747 #clock-cells = <0>;
2748 clock-frequency = <0>;
2753 #clock-cells = <0>;
2754 clock-frequency = <0>;