Lines Matching +full:0 +full:xe6ef2000
19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
45 clock-frequency = <0>;
48 cluster0_opp: opp-table-0 {
72 #size-cells = <0>;
74 a57_0: cpu@0 {
76 reg = <0x0>;
89 reg = <0x1>;
98 L2_CA57: cache-controller-0 {
108 #clock-cells = <0>;
110 clock-frequency = <0>;
115 #clock-cells = <0>;
117 clock-frequency = <0>;
123 #clock-cells = <0>;
124 clock-frequency = <0>;
142 #clock-cells = <0>;
143 clock-frequency = <0>;
156 reg = <0 0xe6020000 0 0x0c>;
167 reg = <0 0xe6050000 0 0x50>;
171 gpio-ranges = <&pfc 0 0 16>;
182 reg = <0 0xe6051000 0 0x50>;
186 gpio-ranges = <&pfc 0 32 29>;
197 reg = <0 0xe6052000 0 0x50>;
201 gpio-ranges = <&pfc 0 64 15>;
212 reg = <0 0xe6053000 0 0x50>;
216 gpio-ranges = <&pfc 0 96 16>;
227 reg = <0 0xe6054000 0 0x50>;
231 gpio-ranges = <&pfc 0 128 18>;
242 reg = <0 0xe6055000 0 0x50>;
246 gpio-ranges = <&pfc 0 160 26>;
257 reg = <0 0xe6055400 0 0x50>;
261 gpio-ranges = <&pfc 0 192 32>;
272 reg = <0 0xe6055800 0 0x50>;
276 gpio-ranges = <&pfc 0 224 4>;
286 reg = <0 0xe6060000 0 0x50c>;
292 reg = <0 0xe60f0000 0 0x1004>;
305 reg = <0 0xe6130000 0 0x1004>;
324 reg = <0 0xe6140000 0 0x1004>;
343 reg = <0 0xe6148000 0 0x1004>;
361 reg = <0 0xe6150000 0 0x1000>;
365 #power-domain-cells = <0>;
371 reg = <0 0xe6160000 0 0x0200>;
376 reg = <0 0xe6180000 0 0x0400>;
382 reg = <0 0xe6198000 0 0x100>,
383 <0 0xe61a0000 0 0x100>,
384 <0 0xe61a8000 0 0x100>;
398 reg = <0 0xe61c0000 0 0x200>;
399 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
412 reg = <0 0xe61e0000 0 0x30>;
426 reg = <0 0xe6fc0000 0 0x30>;
441 reg = <0 0xe6fd0000 0 0x30>;
456 reg = <0 0xe6fe0000 0 0x30>;
470 reg = <0 0xffc00000 0 0x30>;
484 #size-cells = <0>;
487 reg = <0 0xe6500000 0 0x40>;
492 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
493 <&dmac2 0x91>, <&dmac2 0x90>;
501 #size-cells = <0>;
504 reg = <0 0xe6508000 0 0x40>;
509 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
510 <&dmac2 0x93>, <&dmac2 0x92>;
518 #size-cells = <0>;
521 reg = <0 0xe6510000 0 0x40>;
526 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
527 <&dmac2 0x95>, <&dmac2 0x94>;
535 #size-cells = <0>;
538 reg = <0 0xe66d0000 0 0x40>;
543 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
551 #size-cells = <0>;
554 reg = <0 0xe66d8000 0 0x40>;
559 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
567 #size-cells = <0>;
570 reg = <0 0xe66e0000 0 0x40>;
575 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
583 #size-cells = <0>;
586 reg = <0 0xe66e8000 0 0x40>;
591 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
599 #size-cells = <0>;
603 reg = <0 0xe60b0000 0 0x425>;
608 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
617 reg = <0 0xe6540000 0 0x60>;
623 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
624 <&dmac2 0x31>, <&dmac2 0x30>;
635 reg = <0 0xe6550000 0 0x60>;
641 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
642 <&dmac2 0x33>, <&dmac2 0x32>;
653 reg = <0 0xe6560000 0 0x60>;
659 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
660 <&dmac2 0x35>, <&dmac2 0x34>;
671 reg = <0 0xe66a0000 0 0x60>;
677 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
688 reg = <0 0xe66b0000 0 0x60>;
694 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
704 reg = <0 0xe6590000 0 0x200>;
707 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
708 <&usb_dmac1 0>, <&usb_dmac1 1>;
721 reg = <0 0xe6590630 0 0x02>;
726 #clock-cells = <0>;
736 reg = <0 0xe65a0000 0 0x100>;
750 reg = <0 0xe65b0000 0 0x100>;
764 reg = <0 0xe65ee000 0 0x90>;
770 #phy-cells = <0>;
777 reg = <0 0xe6700000 0 0x10000>;
806 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
819 reg = <0 0xe7300000 0 0x10000>;
848 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
861 reg = <0 0xe7310000 0 0x10000>;
902 reg = <0 0xe6740000 0 0x1000>;
903 renesas,ipmmu-main = <&ipmmu_mm 0>;
910 reg = <0 0xe7740000 0 0x1000>;
918 reg = <0 0xe6570000 0 0x1000>;
926 reg = <0 0xe67b0000 0 0x1000>;
935 reg = <0 0xec670000 0 0x1000>;
943 reg = <0 0xfd800000 0 0x1000>;
951 reg = <0 0xfe6b0000 0 0x1000>;
959 reg = <0 0xfebd0000 0 0x1000>;
967 reg = <0 0xfe990000 0 0x1000>;
976 reg = <0 0xe6800000 0 0x800>;
1014 rx-internal-delay-ps = <0>;
1015 tx-internal-delay-ps = <0>;
1018 #size-cells = <0>;
1025 reg = <0 0xe6c30000 0 0x1000>;
1041 reg = <0 0xe6c38000 0 0x1000>;
1057 reg = <0 0xe66c0000 0 0x8000>;
1082 reg = <0 0xe6e30000 0 0x8>;
1092 reg = <0 0xe6e31000 0 0x8>;
1102 reg = <0 0xe6e32000 0 0x8>;
1112 reg = <0 0xe6e33000 0 0x8>;
1122 reg = <0 0xe6e34000 0 0x8>;
1132 reg = <0 0xe6e35000 0 0x8>;
1142 reg = <0 0xe6e36000 0 0x8>;
1153 reg = <0 0xe6e60000 0 0x40>;
1159 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1160 <&dmac2 0x51>, <&dmac2 0x50>;
1170 reg = <0 0xe6e68000 0 0x40>;
1176 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1177 <&dmac2 0x53>, <&dmac2 0x52>;
1187 reg = <0 0xe6e88000 0 0x40>;
1193 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1194 <&dmac2 0x13>, <&dmac2 0x12>;
1204 reg = <0 0xe6c50000 0 0x40>;
1210 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1220 reg = <0 0xe6c40000 0 0x40>;
1226 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1236 reg = <0 0xe6f30000 0 0x40>;
1242 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1243 <&dmac2 0x5b>, <&dmac2 0x5a>;
1253 reg = <0 0xe6e90000 0 0x0064>;
1256 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1257 <&dmac2 0x41>, <&dmac2 0x40>;
1262 #size-cells = <0>;
1269 reg = <0 0xe6ea0000 0 0x0064>;
1272 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1273 <&dmac2 0x43>, <&dmac2 0x42>;
1278 #size-cells = <0>;
1285 reg = <0 0xe6c00000 0 0x0064>;
1288 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1293 #size-cells = <0>;
1300 reg = <0 0xe6c10000 0 0x0064>;
1303 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1308 #size-cells = <0>;
1314 reg = <0 0xe6ef0000 0 0x1000>;
1319 renesas,id = <0>;
1324 #size-cells = <0>;
1328 #size-cells = <0>;
1332 vin0csi20: endpoint@0 {
1333 reg = <0>;
1346 reg = <0 0xe6ef1000 0 0x1000>;
1356 #size-cells = <0>;
1360 #size-cells = <0>;
1364 vin1csi20: endpoint@0 {
1365 reg = <0>;
1378 reg = <0 0xe6ef2000 0 0x1000>;
1388 #size-cells = <0>;
1392 #size-cells = <0>;
1396 vin2csi20: endpoint@0 {
1397 reg = <0>;
1410 reg = <0 0xe6ef3000 0 0x1000>;
1420 #size-cells = <0>;
1424 #size-cells = <0>;
1428 vin3csi20: endpoint@0 {
1429 reg = <0>;
1442 reg = <0 0xe6ef4000 0 0x1000>;
1452 #size-cells = <0>;
1456 #size-cells = <0>;
1460 vin4csi20: endpoint@0 {
1461 reg = <0>;
1474 reg = <0 0xe6ef5000 0 0x1000>;
1484 #size-cells = <0>;
1488 #size-cells = <0>;
1492 vin5csi20: endpoint@0 {
1493 reg = <0>;
1506 reg = <0 0xe6ef6000 0 0x1000>;
1516 #size-cells = <0>;
1520 #size-cells = <0>;
1524 vin6csi20: endpoint@0 {
1525 reg = <0>;
1538 reg = <0 0xe6ef7000 0 0x1000>;
1548 #size-cells = <0>;
1552 #size-cells = <0>;
1556 vin7csi20: endpoint@0 {
1557 reg = <0>;
1572 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1578 * clkout : #clock-cells = <0>; <&rcar_sound>;
1582 reg = <0 0xec500000 0 0x1000>, /* SCU */
1583 <0 0xec5a0000 0 0x100>, /* ADG */
1584 <0 0xec540000 0 0x1000>, /* SSIU */
1585 <0 0xec541000 0 0x280>, /* SSI */
1586 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1609 "ssi.1", "ssi.0",
1612 "src.1", "src.0",
1613 "mix.1", "mix.0",
1614 "ctu.1", "ctu.0",
1615 "dvc.0", "dvc.1",
1627 "ssi.1", "ssi.0";
1631 ctu00: ctu-0 { };
1642 dvc0: dvc-0 {
1643 dmas = <&audma1 0xbc>;
1647 dmas = <&audma1 0xbe>;
1653 mix0: mix-0 { };
1658 src0: src-0 {
1660 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1665 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1670 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1675 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1680 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1685 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1690 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1695 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1700 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1705 dmas = <&audma0 0x97>, <&audma1 0xba>;
1711 ssi0: ssi-0 {
1713 dmas = <&audma0 0x01>, <&audma1 0x02>;
1718 dmas = <&audma0 0x03>, <&audma1 0x04>;
1723 dmas = <&audma0 0x05>, <&audma1 0x06>;
1728 dmas = <&audma0 0x07>, <&audma1 0x08>;
1733 dmas = <&audma0 0x09>, <&audma1 0x0a>;
1738 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
1743 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
1748 dmas = <&audma0 0x0f>, <&audma1 0x10>;
1753 dmas = <&audma0 0x11>, <&audma1 0x12>;
1758 dmas = <&audma0 0x13>, <&audma1 0x14>;
1764 ssiu00: ssiu-0 {
1765 dmas = <&audma0 0x15>, <&audma1 0x16>;
1769 dmas = <&audma0 0x35>, <&audma1 0x36>;
1773 dmas = <&audma0 0x37>, <&audma1 0x38>;
1777 dmas = <&audma0 0x47>, <&audma1 0x48>;
1781 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1785 dmas = <&audma0 0x43>, <&audma1 0x44>;
1789 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1793 dmas = <&audma0 0x53>, <&audma1 0x54>;
1797 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1801 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1805 dmas = <&audma0 0x57>, <&audma1 0x58>;
1809 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1813 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1817 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1821 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1825 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1829 dmas = <&audma0 0x63>, <&audma1 0x64>;
1833 dmas = <&audma0 0x67>, <&audma1 0x68>;
1837 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
1841 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
1845 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
1849 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
1853 dmas = <&audma0 0xED>, <&audma1 0xEE>;
1857 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
1861 dmas = <&audma0 0x6f>, <&audma1 0x70>;
1865 dmas = <&audma0 0x21>, <&audma1 0x22>;
1869 dmas = <&audma0 0x23>, <&audma1 0x24>;
1873 dmas = <&audma0 0x25>, <&audma1 0x26>;
1877 dmas = <&audma0 0x27>, <&audma1 0x28>;
1881 dmas = <&audma0 0x29>, <&audma1 0x2A>;
1885 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
1889 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
1893 dmas = <&audma0 0x71>, <&audma1 0x72>;
1897 dmas = <&audma0 0x17>, <&audma1 0x18>;
1901 dmas = <&audma0 0x19>, <&audma1 0x1A>;
1905 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
1909 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
1913 dmas = <&audma0 0x1F>, <&audma1 0x20>;
1917 dmas = <&audma0 0x31>, <&audma1 0x32>;
1921 dmas = <&audma0 0x33>, <&audma1 0x34>;
1925 dmas = <&audma0 0x73>, <&audma1 0x74>;
1929 dmas = <&audma0 0x75>, <&audma1 0x76>;
1933 dmas = <&audma0 0x79>, <&audma1 0x7a>;
1937 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
1941 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
1945 dmas = <&audma0 0x7F>, <&audma1 0x80>;
1949 dmas = <&audma0 0x81>, <&audma1 0x82>;
1953 dmas = <&audma0 0x83>, <&audma1 0x84>;
1957 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
1961 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
1965 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
1969 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
1978 reg = <0 0xec700000 0 0x10000>;
2007 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
2020 reg = <0 0xec720000 0 0x10000>;
2062 reg = <0 0xee000000 0 0xc00>;
2073 reg = <0 0xee020000 0 0x400>;
2083 reg = <0 0xee080000 0 0x100>;
2095 reg = <0 0xee0a0000 0 0x100>;
2107 reg = <0 0xee080100 0 0x100>;
2120 reg = <0 0xee0a0100 0 0x100>;
2134 reg = <0 0xee080200 0 0x700>;
2146 reg = <0 0xee0a0200 0 0x700>;
2157 reg = <0 0xee100000 0 0x2000>;
2171 reg = <0 0xee120000 0 0x2000>;
2185 reg = <0 0xee140000 0 0x2000>;
2199 reg = <0 0xee160000 0 0x2000>;
2213 reg = <0 0xee200000 0 0x200>,
2214 <0 0x08000000 0 0x4000000>,
2215 <0 0xee208000 0 0x100>;
2222 #size-cells = <0>;
2229 reg = <0 0xee300000 0 0x200000>;
2241 #address-cells = <0>;
2243 reg = <0x0 0xf1010000 0 0x1000>,
2244 <0x0 0xf1020000 0 0x20000>,
2245 <0x0 0xf1040000 0 0x20000>,
2246 <0x0 0xf1060000 0 0x20000>;
2258 reg = <0 0xfe000000 0 0x80000>;
2261 bus-range = <0x00 0xff>;
2263 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2264 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2265 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2266 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2268 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2273 interrupt-map-mask = <0 0 0 0>;
2274 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2279 iommu-map = <0 &ipmmu_hc 0 1>;
2280 iommu-map-mask = <0>;
2287 reg = <0 0xee800000 0 0x80000>;
2290 bus-range = <0x00 0xff>;
2292 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2293 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2294 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2295 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2297 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2302 interrupt-map-mask = <0 0 0 0>;
2303 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2308 iommu-map = <0 &ipmmu_hc 1 1>;
2309 iommu-map-mask = <0>;
2316 reg = <0x0 0xfe000000 0 0x80000>,
2317 <0x0 0xfe100000 0 0x100000>,
2318 <0x0 0xfe200000 0 0x200000>,
2319 <0x0 0x30000000 0 0x8000000>,
2320 <0x0 0x38000000 0 0x8000000>;
2335 reg = <0x0 0xee800000 0 0x80000>,
2336 <0x0 0xee900000 0 0x100000>,
2337 <0x0 0xeea00000 0 0x200000>,
2338 <0x0 0xc0000000 0 0x8000000>,
2339 <0x0 0xc8000000 0 0x8000000>;
2353 reg = <0 0xfe940000 0 0x2400>;
2363 reg = <0 0xfe950000 0 0x200>;
2367 iommus = <&ipmmu_vp0 0>;
2372 reg = <0 0xfe960000 0 0x8000>;
2383 reg = <0 0xfe9a0000 0 0x8000>;
2394 reg = <0 0xfea20000 0 0x5000>;
2405 reg = <0 0xfea28000 0 0x5000>;
2416 reg = <0 0xfe96f000 0 0x200>;
2425 reg = <0 0xfea27000 0 0x200>;
2434 reg = <0 0xfea2f000 0 0x200>;
2443 reg = <0 0xfe9af000 0 0x200>;
2452 reg = <0 0xfea80000 0 0x10000>;
2461 #size-cells = <0>;
2463 port@0 {
2464 reg = <0>;
2469 #size-cells = <0>;
2473 csi20vin0: endpoint@0 {
2474 reg = <0>;
2511 reg = <0 0xfeaa0000 0 0x10000>;
2520 #size-cells = <0>;
2522 port@0 {
2523 reg = <0>;
2528 #size-cells = <0>;
2532 csi40vin0: endpoint@0 {
2533 reg = <0>;
2571 reg = <0 0xfead0000 0 0x10000>;
2582 #size-cells = <0>;
2584 port@0 {
2585 reg = <0>;
2602 reg = <0 0xfeb00000 0 0x80000>;
2608 clock-names = "du.0", "du.1", "du.3";
2610 reset-names = "du.0", "du.3";
2613 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
2617 #size-cells = <0>;
2619 port@0 {
2620 reg = <0>;
2639 reg = <0 0xfeb90000 0 0x14>;
2647 #size-cells = <0>;
2649 port@0 {
2650 reg = <0>;
2663 reg = <0 0xfff00044 0 4>;
2671 thermal-sensors = <&tsc 0>;
2707 cooling-device = <&a57_0 0 2>;
2739 #clock-cells = <0>;
2740 clock-frequency = <0>;
2745 #clock-cells = <0>;
2746 clock-frequency = <0>;