Lines Matching +full:0 +full:xe6160000
19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
45 clock-frequency = <0>;
48 cluster0_opp: opp-table-0 {
93 #size-cells = <0>;
121 a57_0: cpu@0 {
123 reg = <0x0>;
137 reg = <0x1>;
150 reg = <0x100>;
164 reg = <0x101>;
176 reg = <0x102>;
188 reg = <0x103>;
198 L2_CA57: cache-controller-0 {
215 #clock-cells = <0>;
217 clock-frequency = <0>;
222 #clock-cells = <0>;
224 clock-frequency = <0>;
230 #clock-cells = <0>;
231 clock-frequency = <0>;
258 #clock-cells = <0>;
259 clock-frequency = <0>;
272 reg = <0 0xe6020000 0 0x0c>;
283 reg = <0 0xe6050000 0 0x50>;
287 gpio-ranges = <&pfc 0 0 16>;
298 reg = <0 0xe6051000 0 0x50>;
302 gpio-ranges = <&pfc 0 32 29>;
313 reg = <0 0xe6052000 0 0x50>;
317 gpio-ranges = <&pfc 0 64 15>;
328 reg = <0 0xe6053000 0 0x50>;
332 gpio-ranges = <&pfc 0 96 16>;
343 reg = <0 0xe6054000 0 0x50>;
347 gpio-ranges = <&pfc 0 128 18>;
358 reg = <0 0xe6055000 0 0x50>;
362 gpio-ranges = <&pfc 0 160 26>;
373 reg = <0 0xe6055400 0 0x50>;
377 gpio-ranges = <&pfc 0 192 32>;
388 reg = <0 0xe6055800 0 0x50>;
392 gpio-ranges = <&pfc 0 224 4>;
402 reg = <0 0xe6060000 0 0x50c>;
408 reg = <0 0xe60f0000 0 0x1004>;
421 reg = <0 0xe6130000 0 0x1004>;
440 reg = <0 0xe6140000 0 0x1004>;
459 reg = <0 0xe6148000 0 0x1004>;
477 reg = <0 0xe6150000 0 0x0bb0>;
481 #power-domain-cells = <0>;
487 reg = <0 0xe6160000 0 0x018c>;
492 reg = <0 0xe6180000 0 0x0400>;
498 reg = <0 0xe6198000 0 0x100>,
499 <0 0xe61a0000 0 0x100>,
500 <0 0xe61a8000 0 0x100>;
514 reg = <0 0xe61c0000 0 0x200>;
515 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
528 reg = <0 0xe61e0000 0 0x30>;
542 reg = <0 0xe6fc0000 0 0x30>;
557 reg = <0 0xe6fd0000 0 0x30>;
572 reg = <0 0xe6fe0000 0 0x30>;
586 reg = <0 0xffc00000 0 0x30>;
600 #size-cells = <0>;
603 reg = <0 0xe6500000 0 0x40>;
608 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
609 <&dmac2 0x91>, <&dmac2 0x90>;
617 #size-cells = <0>;
620 reg = <0 0xe6508000 0 0x40>;
625 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
626 <&dmac2 0x93>, <&dmac2 0x92>;
634 #size-cells = <0>;
637 reg = <0 0xe6510000 0 0x40>;
642 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
643 <&dmac2 0x95>, <&dmac2 0x94>;
651 #size-cells = <0>;
654 reg = <0 0xe66d0000 0 0x40>;
659 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
667 #size-cells = <0>;
670 reg = <0 0xe66d8000 0 0x40>;
675 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
683 #size-cells = <0>;
686 reg = <0 0xe66e0000 0 0x40>;
691 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
699 #size-cells = <0>;
702 reg = <0 0xe66e8000 0 0x40>;
707 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
715 #size-cells = <0>;
719 reg = <0 0xe60b0000 0 0x425>;
724 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
733 reg = <0 0xe6540000 0 0x60>;
739 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
740 <&dmac2 0x31>, <&dmac2 0x30>;
751 reg = <0 0xe6550000 0 0x60>;
757 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
758 <&dmac2 0x33>, <&dmac2 0x32>;
769 reg = <0 0xe6560000 0 0x60>;
775 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
776 <&dmac2 0x35>, <&dmac2 0x34>;
787 reg = <0 0xe66a0000 0 0x60>;
793 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
804 reg = <0 0xe66b0000 0 0x60>;
810 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
820 reg = <0 0xe6590000 0 0x200>;
823 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
824 <&usb_dmac1 0>, <&usb_dmac1 1>;
837 reg = <0 0xe6590630 0 0x02>;
842 #clock-cells = <0>;
852 reg = <0 0xe65a0000 0 0x100>;
866 reg = <0 0xe65b0000 0 0x100>;
880 reg = <0 0xe65ee000 0 0x90>;
886 #phy-cells = <0>;
893 reg = <0 0xe6700000 0 0x10000>;
922 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
935 reg = <0 0xe7300000 0 0x10000>;
964 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
977 reg = <0 0xe7310000 0 0x10000>;
1018 reg = <0 0xe6740000 0 0x1000>;
1019 renesas,ipmmu-main = <&ipmmu_mm 0>;
1026 reg = <0 0xe7740000 0 0x1000>;
1034 reg = <0 0xe6570000 0 0x1000>;
1042 reg = <0 0xe67b0000 0 0x1000>;
1051 reg = <0 0xec670000 0 0x1000>;
1059 reg = <0 0xfd800000 0 0x1000>;
1067 reg = <0 0xfd950000 0 0x1000>;
1075 reg = <0 0xfe6b0000 0 0x1000>;
1083 reg = <0 0xfebd0000 0 0x1000>;
1092 reg = <0 0xe6800000 0 0x800>;
1130 rx-internal-delay-ps = <0>;
1131 tx-internal-delay-ps = <0>;
1134 #size-cells = <0>;
1141 reg = <0 0xe6c30000 0 0x1000>;
1157 reg = <0 0xe6c38000 0 0x1000>;
1173 reg = <0 0xe66c0000 0 0x8000>;
1198 reg = <0 0xe6e30000 0 0x8>;
1208 reg = <0 0xe6e31000 0 0x8>;
1218 reg = <0 0xe6e32000 0 0x8>;
1228 reg = <0 0xe6e33000 0 0x8>;
1238 reg = <0 0xe6e34000 0 0x8>;
1248 reg = <0 0xe6e35000 0 0x8>;
1258 reg = <0 0xe6e36000 0 0x8>;
1269 reg = <0 0xe6e60000 0 0x40>;
1275 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1276 <&dmac2 0x51>, <&dmac2 0x50>;
1286 reg = <0 0xe6e68000 0 0x40>;
1292 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1293 <&dmac2 0x53>, <&dmac2 0x52>;
1303 reg = <0 0xe6e88000 0 0x40>;
1309 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1310 <&dmac2 0x13>, <&dmac2 0x12>;
1320 reg = <0 0xe6c50000 0 0x40>;
1326 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1336 reg = <0 0xe6c40000 0 0x40>;
1342 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1352 reg = <0 0xe6f30000 0 0x40>;
1358 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1359 <&dmac2 0x5b>, <&dmac2 0x5a>;
1369 reg = <0 0xe6e90000 0 0x0064>;
1372 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1373 <&dmac2 0x41>, <&dmac2 0x40>;
1378 #size-cells = <0>;
1385 reg = <0 0xe6ea0000 0 0x0064>;
1388 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1389 <&dmac2 0x43>, <&dmac2 0x42>;
1394 #size-cells = <0>;
1401 reg = <0 0xe6c00000 0 0x0064>;
1404 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1409 #size-cells = <0>;
1416 reg = <0 0xe6c10000 0 0x0064>;
1419 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1424 #size-cells = <0>;
1430 reg = <0 0xe6ef0000 0 0x1000>;
1435 renesas,id = <0>;
1440 #size-cells = <0>;
1444 #size-cells = <0>;
1448 vin0csi20: endpoint@0 {
1449 reg = <0>;
1462 reg = <0 0xe6ef1000 0 0x1000>;
1472 #size-cells = <0>;
1476 #size-cells = <0>;
1480 vin1csi20: endpoint@0 {
1481 reg = <0>;
1494 reg = <0 0xe6ef2000 0 0x1000>;
1504 #size-cells = <0>;
1508 #size-cells = <0>;
1512 vin2csi20: endpoint@0 {
1513 reg = <0>;
1526 reg = <0 0xe6ef3000 0 0x1000>;
1536 #size-cells = <0>;
1540 #size-cells = <0>;
1544 vin3csi20: endpoint@0 {
1545 reg = <0>;
1558 reg = <0 0xe6ef4000 0 0x1000>;
1568 #size-cells = <0>;
1572 #size-cells = <0>;
1576 vin4csi20: endpoint@0 {
1577 reg = <0>;
1590 reg = <0 0xe6ef5000 0 0x1000>;
1600 #size-cells = <0>;
1604 #size-cells = <0>;
1608 vin5csi20: endpoint@0 {
1609 reg = <0>;
1622 reg = <0 0xe6ef6000 0 0x1000>;
1632 #size-cells = <0>;
1636 #size-cells = <0>;
1640 vin6csi20: endpoint@0 {
1641 reg = <0>;
1654 reg = <0 0xe6ef7000 0 0x1000>;
1664 #size-cells = <0>;
1668 #size-cells = <0>;
1672 vin7csi20: endpoint@0 {
1673 reg = <0>;
1688 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1694 * clkout : #clock-cells = <0>; <&rcar_sound>;
1698 reg = <0 0xec500000 0 0x1000>, /* SCU */
1699 <0 0xec5a0000 0 0x100>, /* ADG */
1700 <0 0xec540000 0 0x1000>, /* SSIU */
1701 <0 0xec541000 0 0x280>, /* SSI */
1702 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1725 "ssi.1", "ssi.0",
1728 "src.1", "src.0",
1729 "mix.1", "mix.0",
1730 "ctu.1", "ctu.0",
1731 "dvc.0", "dvc.1",
1743 "ssi.1", "ssi.0";
1747 ctu00: ctu-0 { };
1758 dvc0: dvc-0 {
1759 dmas = <&audma1 0xbc>;
1763 dmas = <&audma1 0xbe>;
1769 mix0: mix-0 { };
1774 src0: src-0 {
1776 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1781 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1786 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1791 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1796 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1801 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1806 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1811 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1816 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1821 dmas = <&audma0 0x97>, <&audma1 0xba>;
1827 ssi0: ssi-0 {
1829 dmas = <&audma0 0x01>, <&audma1 0x02>;
1834 dmas = <&audma0 0x03>, <&audma1 0x04>;
1839 dmas = <&audma0 0x05>, <&audma1 0x06>;
1844 dmas = <&audma0 0x07>, <&audma1 0x08>;
1849 dmas = <&audma0 0x09>, <&audma1 0x0a>;
1854 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
1859 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
1864 dmas = <&audma0 0x0f>, <&audma1 0x10>;
1869 dmas = <&audma0 0x11>, <&audma1 0x12>;
1874 dmas = <&audma0 0x13>, <&audma1 0x14>;
1880 ssiu00: ssiu-0 {
1881 dmas = <&audma0 0x15>, <&audma1 0x16>;
1885 dmas = <&audma0 0x35>, <&audma1 0x36>;
1889 dmas = <&audma0 0x37>, <&audma1 0x38>;
1893 dmas = <&audma0 0x47>, <&audma1 0x48>;
1897 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1901 dmas = <&audma0 0x43>, <&audma1 0x44>;
1905 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1909 dmas = <&audma0 0x53>, <&audma1 0x54>;
1913 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1917 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1921 dmas = <&audma0 0x57>, <&audma1 0x58>;
1925 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1929 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1933 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1937 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1941 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1945 dmas = <&audma0 0x63>, <&audma1 0x64>;
1949 dmas = <&audma0 0x67>, <&audma1 0x68>;
1953 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
1957 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
1961 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
1965 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
1969 dmas = <&audma0 0xED>, <&audma1 0xEE>;
1973 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
1977 dmas = <&audma0 0x6f>, <&audma1 0x70>;
1981 dmas = <&audma0 0x21>, <&audma1 0x22>;
1985 dmas = <&audma0 0x23>, <&audma1 0x24>;
1989 dmas = <&audma0 0x25>, <&audma1 0x26>;
1993 dmas = <&audma0 0x27>, <&audma1 0x28>;
1997 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2001 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2005 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2009 dmas = <&audma0 0x71>, <&audma1 0x72>;
2013 dmas = <&audma0 0x17>, <&audma1 0x18>;
2017 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2021 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2025 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2029 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2033 dmas = <&audma0 0x31>, <&audma1 0x32>;
2037 dmas = <&audma0 0x33>, <&audma1 0x34>;
2041 dmas = <&audma0 0x73>, <&audma1 0x74>;
2045 dmas = <&audma0 0x75>, <&audma1 0x76>;
2049 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2053 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2057 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2061 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2065 dmas = <&audma0 0x81>, <&audma1 0x82>;
2069 dmas = <&audma0 0x83>, <&audma1 0x84>;
2073 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2077 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2081 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2085 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2094 reg = <0 0xec700000 0 0x10000>;
2123 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
2136 reg = <0 0xec720000 0 0x10000>;
2178 reg = <0 0xee000000 0 0xc00>;
2189 reg = <0 0xee020000 0 0x400>;
2199 reg = <0 0xee080000 0 0x100>;
2211 reg = <0 0xee0a0000 0 0x100>;
2223 reg = <0 0xee080100 0 0x100>;
2236 reg = <0 0xee0a0100 0 0x100>;
2250 reg = <0 0xee080200 0 0x700>;
2262 reg = <0 0xee0a0200 0 0x700>;
2273 reg = <0 0xee100000 0 0x2000>;
2287 reg = <0 0xee120000 0 0x2000>;
2301 reg = <0 0xee140000 0 0x2000>;
2315 reg = <0 0xee160000 0 0x2000>;
2329 reg = <0 0xee200000 0 0x200>,
2330 <0 0x08000000 0 0x4000000>,
2331 <0 0xee208000 0 0x100>;
2338 #size-cells = <0>;
2345 #address-cells = <0>;
2347 reg = <0x0 0xf1010000 0 0x1000>,
2348 <0x0 0xf1020000 0 0x20000>,
2349 <0x0 0xf1040000 0 0x20000>,
2350 <0x0 0xf1060000 0 0x20000>;
2362 reg = <0 0xfe000000 0 0x80000>;
2365 bus-range = <0x00 0xff>;
2367 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2368 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2369 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2370 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2372 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2377 interrupt-map-mask = <0 0 0 0>;
2378 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2383 iommu-map = <0 &ipmmu_hc 0 1>;
2384 iommu-map-mask = <0>;
2391 reg = <0 0xee800000 0 0x80000>;
2394 bus-range = <0x00 0xff>;
2396 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2397 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2398 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2399 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2401 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2406 interrupt-map-mask = <0 0 0 0>;
2407 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2412 iommu-map = <0 &ipmmu_hc 1 1>;
2413 iommu-map-mask = <0>;
2420 reg = <0x0 0xfe000000 0 0x80000>,
2421 <0x0 0xfe100000 0 0x100000>,
2422 <0x0 0xfe200000 0 0x200000>,
2423 <0x0 0x30000000 0 0x8000000>,
2424 <0x0 0x38000000 0 0x8000000>;
2439 reg = <0x0 0xee800000 0 0x80000>,
2440 <0x0 0xee900000 0 0x100000>,
2441 <0x0 0xeea00000 0 0x200000>,
2442 <0x0 0xc0000000 0 0x8000000>,
2443 <0x0 0xc8000000 0 0x8000000>;
2457 reg = <0 0xfe940000 0 0x2400>;
2467 reg = <0 0xfe950000 0 0x200>;
2476 reg = <0 0xfe96f000 0 0x200>;
2485 reg = <0 0xfea27000 0 0x200>;
2494 reg = <0 0xfea2f000 0 0x200>;
2503 reg = <0 0xfea37000 0 0x200>;
2512 reg = <0 0xfe9af000 0 0x200>;
2521 reg = <0 0xfe960000 0 0x8000>;
2532 reg = <0 0xfea20000 0 0x5000>;
2543 reg = <0 0xfea28000 0 0x5000>;
2554 reg = <0 0xfea30000 0 0x5000>;
2565 reg = <0 0xfe9a0000 0 0x8000>;
2576 reg = <0 0xfea80000 0 0x10000>;
2585 #size-cells = <0>;
2587 port@0 {
2588 reg = <0>;
2593 #size-cells = <0>;
2597 csi20vin0: endpoint@0 {
2598 reg = <0>;
2635 reg = <0 0xfeaa0000 0 0x10000>;
2644 #size-cells = <0>;
2646 port@0 {
2647 reg = <0>;
2652 #size-cells = <0>;
2656 csi40vin0: endpoint@0 {
2657 reg = <0>;
2696 reg = <0 0xfead0000 0 0x10000>;
2707 #size-cells = <0>;
2708 port@0 {
2709 reg = <0>;
2726 reg = <0 0xfeb00000 0 0x70000>;
2732 clock-names = "du.0", "du.1", "du.2";
2734 reset-names = "du.0", "du.2";
2737 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
2741 #size-cells = <0>;
2743 port@0 {
2744 reg = <0>;
2763 reg = <0 0xfeb90000 0 0x14>;
2771 #size-cells = <0>;
2773 port@0 {
2774 reg = <0>;
2787 reg = <0 0xfff00044 0 4>;
2795 thermal-sensors = <&tsc 0>;
2831 cooling-device = <&a57_0 0 2>;
2836 cooling-device = <&a53_0 0 2>;
2868 #clock-cells = <0>;
2869 clock-frequency = <0>;
2874 #clock-cells = <0>;
2875 clock-frequency = <0>;