Lines Matching +full:- +full:resets
1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
11 #include <dt-bindings/power/r8a774a1-sysc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <0>;
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <0>;
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <0>;
41 /* External CAN clock - to be overridden by boards that provide it */
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <0>;
48 cluster0_opp: opp-table-0 {
49 compatible = "operating-points-v2";
50 opp-shared;
52 opp-500000000 {
53 opp-hz = /bits/ 64 <500000000>;
54 opp-microvolt = <820000>;
55 clock-latency-ns = <300000>;
57 opp-1000000000 {
58 opp-hz = /bits/ 64 <1000000000>;
59 opp-microvolt = <820000>;
60 clock-latency-ns = <300000>;
62 opp-1500000000 {
63 opp-hz = /bits/ 64 <1500000000>;
64 opp-microvolt = <820000>;
65 clock-latency-ns = <300000>;
66 opp-suspend;
70 cluster1_opp: opp-table-1 {
71 compatible = "operating-points-v2";
72 opp-shared;
74 opp-800000000 {
75 opp-hz = /bits/ 64 <800000000>;
76 opp-microvolt = <820000>;
77 clock-latency-ns = <300000>;
79 opp-1000000000 {
80 opp-hz = /bits/ 64 <1000000000>;
81 opp-microvolt = <820000>;
82 clock-latency-ns = <300000>;
84 opp-1200000000 {
85 opp-hz = /bits/ 64 <1200000000>;
86 opp-microvolt = <820000>;
87 clock-latency-ns = <300000>;
92 #address-cells = <1>;
93 #size-cells = <0>;
95 cpu-map {
122 compatible = "arm,cortex-a57";
125 power-domains = <&sysc R8A774A1_PD_CA57_CPU0>;
126 next-level-cache = <&L2_CA57>;
127 enable-method = "psci";
128 dynamic-power-coefficient = <854>;
130 operating-points-v2 = <&cluster0_opp>;
131 capacity-dmips-mhz = <1024>;
132 #cooling-cells = <2>;
136 compatible = "arm,cortex-a57";
139 power-domains = <&sysc R8A774A1_PD_CA57_CPU1>;
140 next-level-cache = <&L2_CA57>;
141 enable-method = "psci";
143 operating-points-v2 = <&cluster0_opp>;
144 capacity-dmips-mhz = <1024>;
145 #cooling-cells = <2>;
149 compatible = "arm,cortex-a53";
152 power-domains = <&sysc R8A774A1_PD_CA53_CPU0>;
153 next-level-cache = <&L2_CA53>;
154 enable-method = "psci";
155 #cooling-cells = <2>;
156 dynamic-power-coefficient = <277>;
158 operating-points-v2 = <&cluster1_opp>;
159 capacity-dmips-mhz = <560>;
163 compatible = "arm,cortex-a53";
166 power-domains = <&sysc R8A774A1_PD_CA53_CPU1>;
167 next-level-cache = <&L2_CA53>;
168 enable-method = "psci";
170 operating-points-v2 = <&cluster1_opp>;
171 capacity-dmips-mhz = <560>;
175 compatible = "arm,cortex-a53";
178 power-domains = <&sysc R8A774A1_PD_CA53_CPU2>;
179 next-level-cache = <&L2_CA53>;
180 enable-method = "psci";
182 operating-points-v2 = <&cluster1_opp>;
183 capacity-dmips-mhz = <560>;
187 compatible = "arm,cortex-a53";
190 power-domains = <&sysc R8A774A1_PD_CA53_CPU3>;
191 next-level-cache = <&L2_CA53>;
192 enable-method = "psci";
194 operating-points-v2 = <&cluster1_opp>;
195 capacity-dmips-mhz = <560>;
198 L2_CA57: cache-controller-0 {
200 power-domains = <&sysc R8A774A1_PD_CA57_SCU>;
201 cache-unified;
202 cache-level = <2>;
205 L2_CA53: cache-controller-1 {
207 power-domains = <&sysc R8A774A1_PD_CA53_SCU>;
208 cache-unified;
209 cache-level = <2>;
214 compatible = "fixed-clock";
215 #clock-cells = <0>;
217 clock-frequency = <0>;
221 compatible = "fixed-clock";
222 #clock-cells = <0>;
224 clock-frequency = <0>;
227 /* External PCIe clock - can be overridden by the board */
229 compatible = "fixed-clock";
230 #clock-cells = <0>;
231 clock-frequency = <0>;
235 compatible = "arm,cortex-a53-pmu";
236 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
240 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
244 compatible = "arm,cortex-a57-pmu";
245 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
247 interrupt-affinity = <&a57_0>, <&a57_1>;
251 compatible = "arm,psci-1.0", "arm,psci-0.2";
255 /* External SCIF clock - to be overridden by boards that provide it */
257 compatible = "fixed-clock";
258 #clock-cells = <0>;
259 clock-frequency = <0>;
263 compatible = "simple-bus";
264 interrupt-parent = <&gic>;
265 #address-cells = <2>;
266 #size-cells = <2>;
270 compatible = "renesas,r8a774a1-wdt",
271 "renesas,rcar-gen3-wdt";
275 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
276 resets = <&cpg 402>;
281 compatible = "renesas,gpio-r8a774a1",
282 "renesas,rcar-gen3-gpio";
285 #gpio-cells = <2>;
286 gpio-controller;
287 gpio-ranges = <&pfc 0 0 16>;
288 #interrupt-cells = <2>;
289 interrupt-controller;
291 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
292 resets = <&cpg 912>;
296 compatible = "renesas,gpio-r8a774a1",
297 "renesas,rcar-gen3-gpio";
300 #gpio-cells = <2>;
301 gpio-controller;
302 gpio-ranges = <&pfc 0 32 29>;
303 #interrupt-cells = <2>;
304 interrupt-controller;
306 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
307 resets = <&cpg 911>;
311 compatible = "renesas,gpio-r8a774a1",
312 "renesas,rcar-gen3-gpio";
315 #gpio-cells = <2>;
316 gpio-controller;
317 gpio-ranges = <&pfc 0 64 15>;
318 #interrupt-cells = <2>;
319 interrupt-controller;
321 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
322 resets = <&cpg 910>;
326 compatible = "renesas,gpio-r8a774a1",
327 "renesas,rcar-gen3-gpio";
330 #gpio-cells = <2>;
331 gpio-controller;
332 gpio-ranges = <&pfc 0 96 16>;
333 #interrupt-cells = <2>;
334 interrupt-controller;
336 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
337 resets = <&cpg 909>;
341 compatible = "renesas,gpio-r8a774a1",
342 "renesas,rcar-gen3-gpio";
345 #gpio-cells = <2>;
346 gpio-controller;
347 gpio-ranges = <&pfc 0 128 18>;
348 #interrupt-cells = <2>;
349 interrupt-controller;
351 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
352 resets = <&cpg 908>;
356 compatible = "renesas,gpio-r8a774a1",
357 "renesas,rcar-gen3-gpio";
360 #gpio-cells = <2>;
361 gpio-controller;
362 gpio-ranges = <&pfc 0 160 26>;
363 #interrupt-cells = <2>;
364 interrupt-controller;
366 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
367 resets = <&cpg 907>;
371 compatible = "renesas,gpio-r8a774a1",
372 "renesas,rcar-gen3-gpio";
375 #gpio-cells = <2>;
376 gpio-controller;
377 gpio-ranges = <&pfc 0 192 32>;
378 #interrupt-cells = <2>;
379 interrupt-controller;
381 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
382 resets = <&cpg 906>;
386 compatible = "renesas,gpio-r8a774a1",
387 "renesas,rcar-gen3-gpio";
390 #gpio-cells = <2>;
391 gpio-controller;
392 gpio-ranges = <&pfc 0 224 4>;
393 #interrupt-cells = <2>;
394 interrupt-controller;
396 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
397 resets = <&cpg 905>;
401 compatible = "renesas,pfc-r8a774a1";
406 compatible = "renesas,r8a774a1-cmt0",
407 "renesas,rcar-gen3-cmt0";
412 clock-names = "fck";
413 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
414 resets = <&cpg 303>;
419 compatible = "renesas,r8a774a1-cmt1",
420 "renesas,rcar-gen3-cmt1";
431 clock-names = "fck";
432 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
433 resets = <&cpg 302>;
438 compatible = "renesas,r8a774a1-cmt1",
439 "renesas,rcar-gen3-cmt1";
450 clock-names = "fck";
451 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
452 resets = <&cpg 301>;
457 compatible = "renesas,r8a774a1-cmt1",
458 "renesas,rcar-gen3-cmt1";
469 clock-names = "fck";
470 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
471 resets = <&cpg 300>;
475 cpg: clock-controller@e6150000 {
476 compatible = "renesas,r8a774a1-cpg-mssr";
479 clock-names = "extal", "extalr";
480 #clock-cells = <2>;
481 #power-domain-cells = <0>;
482 #reset-cells = <1>;
485 rst: reset-controller@e6160000 {
486 compatible = "renesas,r8a774a1-rst";
490 sysc: system-controller@e6180000 {
491 compatible = "renesas,r8a774a1-sysc";
493 #power-domain-cells = <1>;
497 compatible = "renesas,r8a774a1-thermal";
505 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
506 resets = <&cpg 522>;
507 #thermal-sensor-cells = <1>;
510 intc_ex: interrupt-controller@e61c0000 {
511 compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc";
512 #interrupt-cells = <2>;
513 interrupt-controller;
522 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
523 resets = <&cpg 407>;
527 compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
532 interrupt-names = "tuni0", "tuni1", "tuni2";
534 clock-names = "fck";
535 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
536 resets = <&cpg 125>;
541 compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
547 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
549 clock-names = "fck";
550 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
551 resets = <&cpg 124>;
556 compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
562 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
564 clock-names = "fck";
565 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
566 resets = <&cpg 123>;
571 compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
576 interrupt-names = "tuni0", "tuni1", "tuni2";
578 clock-names = "fck";
579 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
580 resets = <&cpg 122>;
585 compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
590 interrupt-names = "tuni0", "tuni1", "tuni2";
592 clock-names = "fck";
593 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
594 resets = <&cpg 121>;
599 #address-cells = <1>;
600 #size-cells = <0>;
601 compatible = "renesas,i2c-r8a774a1",
602 "renesas,rcar-gen3-i2c";
606 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
607 resets = <&cpg 931>;
610 dma-names = "tx", "rx", "tx", "rx";
611 i2c-scl-internal-delay-ns = <110>;
616 #address-cells = <1>;
617 #size-cells = <0>;
618 compatible = "renesas,i2c-r8a774a1",
619 "renesas,rcar-gen3-i2c";
623 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
624 resets = <&cpg 930>;
627 dma-names = "tx", "rx", "tx", "rx";
628 i2c-scl-internal-delay-ns = <6>;
633 #address-cells = <1>;
634 #size-cells = <0>;
635 compatible = "renesas,i2c-r8a774a1",
636 "renesas,rcar-gen3-i2c";
640 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
641 resets = <&cpg 929>;
644 dma-names = "tx", "rx", "tx", "rx";
645 i2c-scl-internal-delay-ns = <6>;
650 #address-cells = <1>;
651 #size-cells = <0>;
652 compatible = "renesas,i2c-r8a774a1",
653 "renesas,rcar-gen3-i2c";
657 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
658 resets = <&cpg 928>;
660 dma-names = "tx", "rx";
661 i2c-scl-internal-delay-ns = <110>;
666 #address-cells = <1>;
667 #size-cells = <0>;
668 compatible = "renesas,i2c-r8a774a1",
669 "renesas,rcar-gen3-i2c";
673 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
674 resets = <&cpg 927>;
676 dma-names = "tx", "rx";
677 i2c-scl-internal-delay-ns = <110>;
682 #address-cells = <1>;
683 #size-cells = <0>;
684 compatible = "renesas,i2c-r8a774a1",
685 "renesas,rcar-gen3-i2c";
689 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
690 resets = <&cpg 919>;
692 dma-names = "tx", "rx";
693 i2c-scl-internal-delay-ns = <110>;
698 #address-cells = <1>;
699 #size-cells = <0>;
700 compatible = "renesas,i2c-r8a774a1",
701 "renesas,rcar-gen3-i2c";
705 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
706 resets = <&cpg 918>;
708 dma-names = "tx", "rx";
709 i2c-scl-internal-delay-ns = <6>;
714 #address-cells = <1>;
715 #size-cells = <0>;
716 compatible = "renesas,iic-r8a774a1",
717 "renesas,rcar-gen3-iic",
718 "renesas,rmobile-iic";
722 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
723 resets = <&cpg 926>;
725 dma-names = "tx", "rx";
730 compatible = "renesas,hscif-r8a774a1",
731 "renesas,rcar-gen3-hscif",
738 clock-names = "fck", "brg_int", "scif_clk";
741 dma-names = "tx", "rx", "tx", "rx";
742 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
743 resets = <&cpg 520>;
748 compatible = "renesas,hscif-r8a774a1",
749 "renesas,rcar-gen3-hscif",
756 clock-names = "fck", "brg_int", "scif_clk";
759 dma-names = "tx", "rx", "tx", "rx";
760 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
761 resets = <&cpg 519>;
766 compatible = "renesas,hscif-r8a774a1",
767 "renesas,rcar-gen3-hscif",
774 clock-names = "fck", "brg_int", "scif_clk";
777 dma-names = "tx", "rx", "tx", "rx";
778 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
779 resets = <&cpg 518>;
784 compatible = "renesas,hscif-r8a774a1",
785 "renesas,rcar-gen3-hscif",
792 clock-names = "fck", "brg_int", "scif_clk";
794 dma-names = "tx", "rx";
795 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
796 resets = <&cpg 517>;
801 compatible = "renesas,hscif-r8a774a1",
802 "renesas,rcar-gen3-hscif",
809 clock-names = "fck", "brg_int", "scif_clk";
811 dma-names = "tx", "rx";
812 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
813 resets = <&cpg 516>;
818 compatible = "renesas,usbhs-r8a774a1",
819 "renesas,rcar-gen3-usbhs";
825 dma-names = "ch0", "ch1", "ch2", "ch3";
828 phy-names = "usb";
829 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
830 resets = <&cpg 704>, <&cpg 703>;
834 usb2_clksel: clock-controller@e6590630 {
835 compatible = "renesas,r8a774a1-rcar-usb2-clock-sel",
836 "renesas,rcar-gen3-usb2-clock-sel";
840 clock-names = "ehci_ohci", "hs-usb-if",
842 #clock-cells = <0>;
843 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
844 resets = <&cpg 703>, <&cpg 704>;
845 reset-names = "ehci_ohci", "hs-usb-if";
849 usb_dmac0: dma-controller@e65a0000 {
850 compatible = "renesas,r8a774a1-usb-dmac",
851 "renesas,usb-dmac";
855 interrupt-names = "ch0", "ch1";
857 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
858 resets = <&cpg 330>;
859 #dma-cells = <1>;
860 dma-channels = <2>;
863 usb_dmac1: dma-controller@e65b0000 {
864 compatible = "renesas,r8a774a1-usb-dmac",
865 "renesas,usb-dmac";
869 interrupt-names = "ch0", "ch1";
871 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
872 resets = <&cpg 331>;
873 #dma-cells = <1>;
874 dma-channels = <2>;
877 usb3_phy0: usb-phy@e65ee000 {
878 compatible = "renesas,r8a774a1-usb3-phy",
879 "renesas,rcar-gen3-usb3-phy";
883 clock-names = "usb3-if", "usb3s_clk", "usb_extal";
884 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
885 resets = <&cpg 328>;
886 #phy-cells = <0>;
890 dmac0: dma-controller@e6700000 {
891 compatible = "renesas,dmac-r8a774a1",
892 "renesas,rcar-dmac";
911 interrupt-names = "error",
917 clock-names = "fck";
918 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
919 resets = <&cpg 219>;
920 #dma-cells = <1>;
921 dma-channels = <16>;
932 dmac1: dma-controller@e7300000 {
933 compatible = "renesas,dmac-r8a774a1",
934 "renesas,rcar-dmac";
953 interrupt-names = "error",
959 clock-names = "fck";
960 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
961 resets = <&cpg 218>;
962 #dma-cells = <1>;
963 dma-channels = <16>;
974 dmac2: dma-controller@e7310000 {
975 compatible = "renesas,dmac-r8a774a1",
976 "renesas,rcar-dmac";
995 interrupt-names = "error",
1001 clock-names = "fck";
1002 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1003 resets = <&cpg 217>;
1004 #dma-cells = <1>;
1005 dma-channels = <16>;
1017 compatible = "renesas,ipmmu-r8a774a1";
1019 renesas,ipmmu-main = <&ipmmu_mm 0>;
1020 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1021 #iommu-cells = <1>;
1025 compatible = "renesas,ipmmu-r8a774a1";
1027 renesas,ipmmu-main = <&ipmmu_mm 1>;
1028 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1029 #iommu-cells = <1>;
1033 compatible = "renesas,ipmmu-r8a774a1";
1035 renesas,ipmmu-main = <&ipmmu_mm 2>;
1036 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1037 #iommu-cells = <1>;
1041 compatible = "renesas,ipmmu-r8a774a1";
1045 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1046 #iommu-cells = <1>;
1050 compatible = "renesas,ipmmu-r8a774a1";
1052 renesas,ipmmu-main = <&ipmmu_mm 4>;
1053 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1054 #iommu-cells = <1>;
1058 compatible = "renesas,ipmmu-r8a774a1";
1060 renesas,ipmmu-main = <&ipmmu_mm 5>;
1061 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1062 #iommu-cells = <1>;
1066 compatible = "renesas,ipmmu-r8a774a1";
1068 renesas,ipmmu-main = <&ipmmu_mm 6>;
1069 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1070 #iommu-cells = <1>;
1074 compatible = "renesas,ipmmu-r8a774a1";
1076 renesas,ipmmu-main = <&ipmmu_mm 8>;
1077 power-domains = <&sysc R8A774A1_PD_A3VC>;
1078 #iommu-cells = <1>;
1082 compatible = "renesas,ipmmu-r8a774a1";
1084 renesas,ipmmu-main = <&ipmmu_mm 9>;
1085 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1086 #iommu-cells = <1>;
1090 compatible = "renesas,etheravb-r8a774a1",
1091 "renesas,etheravb-rcar-gen3";
1118 interrupt-names = "ch0", "ch1", "ch2", "ch3",
1126 clock-names = "fck";
1127 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1128 resets = <&cpg 812>;
1129 phy-mode = "rgmii";
1130 rx-internal-delay-ps = <0>;
1131 tx-internal-delay-ps = <0>;
1133 #address-cells = <1>;
1134 #size-cells = <0>;
1139 compatible = "renesas,can-r8a774a1",
1140 "renesas,rcar-gen3-can";
1146 clock-names = "clkp1", "clkp2", "can_clk";
1147 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;
1148 assigned-clock-rates = <40000000>;
1149 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1150 resets = <&cpg 916>;
1155 compatible = "renesas,can-r8a774a1",
1156 "renesas,rcar-gen3-can";
1162 clock-names = "clkp1", "clkp2", "can_clk";
1163 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;
1164 assigned-clock-rates = <40000000>;
1165 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1166 resets = <&cpg 915>;
1171 compatible = "renesas,r8a774a1-canfd",
1172 "renesas,rcar-gen3-canfd";
1176 interrupt-names = "ch_int", "g_int";
1180 clock-names = "fck", "canfd", "can_clk";
1181 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;
1182 assigned-clock-rates = <40000000>;
1183 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1184 resets = <&cpg 914>;
1197 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1199 #pwm-cells = <2>;
1201 resets = <&cpg 523>;
1202 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1207 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1209 #pwm-cells = <2>;
1211 resets = <&cpg 523>;
1212 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1217 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1219 #pwm-cells = <2>;
1221 resets = <&cpg 523>;
1222 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1227 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1229 #pwm-cells = <2>;
1231 resets = <&cpg 523>;
1232 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1237 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1239 #pwm-cells = <2>;
1241 resets = <&cpg 523>;
1242 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1247 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1249 #pwm-cells = <2>;
1251 resets = <&cpg 523>;
1252 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1257 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1259 #pwm-cells = <2>;
1261 resets = <&cpg 523>;
1262 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1267 compatible = "renesas,scif-r8a774a1",
1268 "renesas,rcar-gen3-scif", "renesas,scif";
1274 clock-names = "fck", "brg_int", "scif_clk";
1277 dma-names = "tx", "rx", "tx", "rx";
1278 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1279 resets = <&cpg 207>;
1284 compatible = "renesas,scif-r8a774a1",
1285 "renesas,rcar-gen3-scif", "renesas,scif";
1291 clock-names = "fck", "brg_int", "scif_clk";
1294 dma-names = "tx", "rx", "tx", "rx";
1295 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1296 resets = <&cpg 206>;
1301 compatible = "renesas,scif-r8a774a1",
1302 "renesas,rcar-gen3-scif", "renesas,scif";
1308 clock-names = "fck", "brg_int", "scif_clk";
1311 dma-names = "tx", "rx", "tx", "rx";
1312 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1313 resets = <&cpg 310>;
1318 compatible = "renesas,scif-r8a774a1",
1319 "renesas,rcar-gen3-scif", "renesas,scif";
1325 clock-names = "fck", "brg_int", "scif_clk";
1327 dma-names = "tx", "rx";
1328 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1329 resets = <&cpg 204>;
1334 compatible = "renesas,scif-r8a774a1",
1335 "renesas,rcar-gen3-scif", "renesas,scif";
1341 clock-names = "fck", "brg_int", "scif_clk";
1343 dma-names = "tx", "rx";
1344 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1345 resets = <&cpg 203>;
1350 compatible = "renesas,scif-r8a774a1",
1351 "renesas,rcar-gen3-scif", "renesas,scif";
1357 clock-names = "fck", "brg_int", "scif_clk";
1360 dma-names = "tx", "rx", "tx", "rx";
1361 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1362 resets = <&cpg 202>;
1367 compatible = "renesas,msiof-r8a774a1",
1368 "renesas,rcar-gen3-msiof";
1374 dma-names = "tx", "rx", "tx", "rx";
1375 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1376 resets = <&cpg 211>;
1377 #address-cells = <1>;
1378 #size-cells = <0>;
1383 compatible = "renesas,msiof-r8a774a1",
1384 "renesas,rcar-gen3-msiof";
1390 dma-names = "tx", "rx", "tx", "rx";
1391 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1392 resets = <&cpg 210>;
1393 #address-cells = <1>;
1394 #size-cells = <0>;
1399 compatible = "renesas,msiof-r8a774a1",
1400 "renesas,rcar-gen3-msiof";
1405 dma-names = "tx", "rx";
1406 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1407 resets = <&cpg 209>;
1408 #address-cells = <1>;
1409 #size-cells = <0>;
1414 compatible = "renesas,msiof-r8a774a1",
1415 "renesas,rcar-gen3-msiof";
1420 dma-names = "tx", "rx";
1421 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1422 resets = <&cpg 208>;
1423 #address-cells = <1>;
1424 #size-cells = <0>;
1429 compatible = "renesas,vin-r8a774a1";
1433 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1434 resets = <&cpg 811>;
1439 #address-cells = <1>;
1440 #size-cells = <0>;
1443 #address-cells = <1>;
1444 #size-cells = <0>;
1450 remote-endpoint = <&csi20vin0>;
1454 remote-endpoint = <&csi40vin0>;
1461 compatible = "renesas,vin-r8a774a1";
1465 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1466 resets = <&cpg 810>;
1471 #address-cells = <1>;
1472 #size-cells = <0>;
1475 #address-cells = <1>;
1476 #size-cells = <0>;
1482 remote-endpoint = <&csi20vin1>;
1486 remote-endpoint = <&csi40vin1>;
1493 compatible = "renesas,vin-r8a774a1";
1497 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1498 resets = <&cpg 809>;
1503 #address-cells = <1>;
1504 #size-cells = <0>;
1507 #address-cells = <1>;
1508 #size-cells = <0>;
1514 remote-endpoint = <&csi20vin2>;
1518 remote-endpoint = <&csi40vin2>;
1525 compatible = "renesas,vin-r8a774a1";
1529 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1530 resets = <&cpg 808>;
1535 #address-cells = <1>;
1536 #size-cells = <0>;
1539 #address-cells = <1>;
1540 #size-cells = <0>;
1546 remote-endpoint = <&csi20vin3>;
1550 remote-endpoint = <&csi40vin3>;
1557 compatible = "renesas,vin-r8a774a1";
1561 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1562 resets = <&cpg 807>;
1567 #address-cells = <1>;
1568 #size-cells = <0>;
1571 #address-cells = <1>;
1572 #size-cells = <0>;
1578 remote-endpoint = <&csi20vin4>;
1582 remote-endpoint = <&csi40vin4>;
1589 compatible = "renesas,vin-r8a774a1";
1593 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1594 resets = <&cpg 806>;
1599 #address-cells = <1>;
1600 #size-cells = <0>;
1603 #address-cells = <1>;
1604 #size-cells = <0>;
1610 remote-endpoint = <&csi20vin5>;
1614 remote-endpoint = <&csi40vin5>;
1621 compatible = "renesas,vin-r8a774a1";
1625 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1626 resets = <&cpg 805>;
1631 #address-cells = <1>;
1632 #size-cells = <0>;
1635 #address-cells = <1>;
1636 #size-cells = <0>;
1642 remote-endpoint = <&csi20vin6>;
1646 remote-endpoint = <&csi40vin6>;
1653 compatible = "renesas,vin-r8a774a1";
1657 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1658 resets = <&cpg 804>;
1663 #address-cells = <1>;
1664 #size-cells = <0>;
1667 #address-cells = <1>;
1668 #size-cells = <0>;
1674 remote-endpoint = <&csi20vin7>;
1678 remote-endpoint = <&csi40vin7>;
1686 * #sound-dai-cells is required if simple-card
1688 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1689 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1692 * #clock-cells is required for audio_clkout0/1/2/3
1694 * clkout : #clock-cells = <0>; <&rcar_sound>;
1695 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1697 compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3";
1703 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1722 clock-names = "ssi-all",
1733 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1734 resets = <&cpg 1005>,
1740 reset-names = "ssi-all",
1747 ctu00: ctu-0 { };
1748 ctu01: ctu-1 { };
1749 ctu02: ctu-2 { };
1750 ctu03: ctu-3 { };
1751 ctu10: ctu-4 { };
1752 ctu11: ctu-5 { };
1753 ctu12: ctu-6 { };
1754 ctu13: ctu-7 { };
1758 dvc0: dvc-0 {
1760 dma-names = "tx";
1762 dvc1: dvc-1 {
1764 dma-names = "tx";
1769 mix0: mix-0 { };
1770 mix1: mix-1 { };
1774 src0: src-0 {
1777 dma-names = "rx", "tx";
1779 src1: src-1 {
1782 dma-names = "rx", "tx";
1784 src2: src-2 {
1787 dma-names = "rx", "tx";
1789 src3: src-3 {
1792 dma-names = "rx", "tx";
1794 src4: src-4 {
1797 dma-names = "rx", "tx";
1799 src5: src-5 {
1802 dma-names = "rx", "tx";
1804 src6: src-6 {
1807 dma-names = "rx", "tx";
1809 src7: src-7 {
1812 dma-names = "rx", "tx";
1814 src8: src-8 {
1817 dma-names = "rx", "tx";
1819 src9: src-9 {
1822 dma-names = "rx", "tx";
1827 ssi0: ssi-0 {
1830 dma-names = "rx", "tx";
1832 ssi1: ssi-1 {
1835 dma-names = "rx", "tx";
1837 ssi2: ssi-2 {
1840 dma-names = "rx", "tx";
1842 ssi3: ssi-3 {
1845 dma-names = "rx", "tx";
1847 ssi4: ssi-4 {
1850 dma-names = "rx", "tx";
1852 ssi5: ssi-5 {
1855 dma-names = "rx", "tx";
1857 ssi6: ssi-6 {
1860 dma-names = "rx", "tx";
1862 ssi7: ssi-7 {
1865 dma-names = "rx", "tx";
1867 ssi8: ssi-8 {
1870 dma-names = "rx", "tx";
1872 ssi9: ssi-9 {
1875 dma-names = "rx", "tx";
1880 ssiu00: ssiu-0 {
1882 dma-names = "rx", "tx";
1884 ssiu01: ssiu-1 {
1886 dma-names = "rx", "tx";
1888 ssiu02: ssiu-2 {
1890 dma-names = "rx", "tx";
1892 ssiu03: ssiu-3 {
1894 dma-names = "rx", "tx";
1896 ssiu04: ssiu-4 {
1898 dma-names = "rx", "tx";
1900 ssiu05: ssiu-5 {
1902 dma-names = "rx", "tx";
1904 ssiu06: ssiu-6 {
1906 dma-names = "rx", "tx";
1908 ssiu07: ssiu-7 {
1910 dma-names = "rx", "tx";
1912 ssiu10: ssiu-8 {
1914 dma-names = "rx", "tx";
1916 ssiu11: ssiu-9 {
1918 dma-names = "rx", "tx";
1920 ssiu12: ssiu-10 {
1922 dma-names = "rx", "tx";
1924 ssiu13: ssiu-11 {
1926 dma-names = "rx", "tx";
1928 ssiu14: ssiu-12 {
1930 dma-names = "rx", "tx";
1932 ssiu15: ssiu-13 {
1934 dma-names = "rx", "tx";
1936 ssiu16: ssiu-14 {
1938 dma-names = "rx", "tx";
1940 ssiu17: ssiu-15 {
1942 dma-names = "rx", "tx";
1944 ssiu20: ssiu-16 {
1946 dma-names = "rx", "tx";
1948 ssiu21: ssiu-17 {
1950 dma-names = "rx", "tx";
1952 ssiu22: ssiu-18 {
1954 dma-names = "rx", "tx";
1956 ssiu23: ssiu-19 {
1958 dma-names = "rx", "tx";
1960 ssiu24: ssiu-20 {
1962 dma-names = "rx", "tx";
1964 ssiu25: ssiu-21 {
1966 dma-names = "rx", "tx";
1968 ssiu26: ssiu-22 {
1970 dma-names = "rx", "tx";
1972 ssiu27: ssiu-23 {
1974 dma-names = "rx", "tx";
1976 ssiu30: ssiu-24 {
1978 dma-names = "rx", "tx";
1980 ssiu31: ssiu-25 {
1982 dma-names = "rx", "tx";
1984 ssiu32: ssiu-26 {
1986 dma-names = "rx", "tx";
1988 ssiu33: ssiu-27 {
1990 dma-names = "rx", "tx";
1992 ssiu34: ssiu-28 {
1994 dma-names = "rx", "tx";
1996 ssiu35: ssiu-29 {
1998 dma-names = "rx", "tx";
2000 ssiu36: ssiu-30 {
2002 dma-names = "rx", "tx";
2004 ssiu37: ssiu-31 {
2006 dma-names = "rx", "tx";
2008 ssiu40: ssiu-32 {
2010 dma-names = "rx", "tx";
2012 ssiu41: ssiu-33 {
2014 dma-names = "rx", "tx";
2016 ssiu42: ssiu-34 {
2018 dma-names = "rx", "tx";
2020 ssiu43: ssiu-35 {
2022 dma-names = "rx", "tx";
2024 ssiu44: ssiu-36 {
2026 dma-names = "rx", "tx";
2028 ssiu45: ssiu-37 {
2030 dma-names = "rx", "tx";
2032 ssiu46: ssiu-38 {
2034 dma-names = "rx", "tx";
2036 ssiu47: ssiu-39 {
2038 dma-names = "rx", "tx";
2040 ssiu50: ssiu-40 {
2042 dma-names = "rx", "tx";
2044 ssiu60: ssiu-41 {
2046 dma-names = "rx", "tx";
2048 ssiu70: ssiu-42 {
2050 dma-names = "rx", "tx";
2052 ssiu80: ssiu-43 {
2054 dma-names = "rx", "tx";
2056 ssiu90: ssiu-44 {
2058 dma-names = "rx", "tx";
2060 ssiu91: ssiu-45 {
2062 dma-names = "rx", "tx";
2064 ssiu92: ssiu-46 {
2066 dma-names = "rx", "tx";
2068 ssiu93: ssiu-47 {
2070 dma-names = "rx", "tx";
2072 ssiu94: ssiu-48 {
2074 dma-names = "rx", "tx";
2076 ssiu95: ssiu-49 {
2078 dma-names = "rx", "tx";
2080 ssiu96: ssiu-50 {
2082 dma-names = "rx", "tx";
2084 ssiu97: ssiu-51 {
2086 dma-names = "rx", "tx";
2091 audma0: dma-controller@ec700000 {
2092 compatible = "renesas,dmac-r8a774a1",
2093 "renesas,rcar-dmac";
2112 interrupt-names = "error",
2118 clock-names = "fck";
2119 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2120 resets = <&cpg 502>;
2121 #dma-cells = <1>;
2122 dma-channels = <16>;
2133 audma1: dma-controller@ec720000 {
2134 compatible = "renesas,dmac-r8a774a1",
2135 "renesas,rcar-dmac";
2154 interrupt-names = "error",
2160 clock-names = "fck";
2161 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2162 resets = <&cpg 501>;
2163 #dma-cells = <1>;
2164 dma-channels = <16>;
2176 compatible = "renesas,xhci-r8a774a1",
2177 "renesas,rcar-gen3-xhci";
2181 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2182 resets = <&cpg 328>;
2187 compatible = "renesas,r8a774a1-usb3-peri",
2188 "renesas,rcar-gen3-usb3-peri";
2192 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2193 resets = <&cpg 328>;
2198 compatible = "generic-ohci";
2203 phy-names = "usb";
2204 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2205 resets = <&cpg 703>, <&cpg 704>;
2210 compatible = "generic-ohci";
2215 phy-names = "usb";
2216 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2217 resets = <&cpg 702>;
2222 compatible = "generic-ehci";
2227 phy-names = "usb";
2229 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2230 resets = <&cpg 703>, <&cpg 704>;
2235 compatible = "generic-ehci";
2240 phy-names = "usb";
2242 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2243 resets = <&cpg 702>;
2247 usb2_phy0: usb-phy@ee080200 {
2248 compatible = "renesas,usb2-phy-r8a774a1",
2249 "renesas,rcar-gen3-usb2-phy";
2253 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2254 resets = <&cpg 703>, <&cpg 704>;
2255 #phy-cells = <1>;
2259 usb2_phy1: usb-phy@ee0a0200 {
2260 compatible = "renesas,usb2-phy-r8a774a1",
2261 "renesas,rcar-gen3-usb2-phy";
2264 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2265 resets = <&cpg 702>;
2266 #phy-cells = <1>;
2271 compatible = "renesas,sdhi-r8a774a1",
2272 "renesas,rcar-gen3-sdhi";
2276 clock-names = "core", "clkh";
2277 max-frequency = <200000000>;
2278 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2279 resets = <&cpg 314>;
2285 compatible = "renesas,sdhi-r8a774a1",
2286 "renesas,rcar-gen3-sdhi";
2290 clock-names = "core", "clkh";
2291 max-frequency = <200000000>;
2292 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2293 resets = <&cpg 313>;
2299 compatible = "renesas,sdhi-r8a774a1",
2300 "renesas,rcar-gen3-sdhi";
2304 clock-names = "core", "clkh";
2305 max-frequency = <200000000>;
2306 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2307 resets = <&cpg 312>;
2313 compatible = "renesas,sdhi-r8a774a1",
2314 "renesas,rcar-gen3-sdhi";
2318 clock-names = "core", "clkh";
2319 max-frequency = <200000000>;
2320 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2321 resets = <&cpg 311>;
2327 compatible = "renesas,r8a774a1-rpc-if",
2328 "renesas,rcar-gen3-rpc-if";
2332 reg-names = "regs", "dirmap", "wbuf";
2335 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2336 resets = <&cpg 917>;
2337 #address-cells = <1>;
2338 #size-cells = <0>;
2342 gic: interrupt-controller@f1010000 {
2343 compatible = "arm,gic-400";
2344 #interrupt-cells = <3>;
2345 #address-cells = <0>;
2346 interrupt-controller;
2354 clock-names = "clk";
2355 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2356 resets = <&cpg 408>;
2360 compatible = "renesas,pcie-r8a774a1",
2361 "renesas,pcie-rcar-gen3";
2363 #address-cells = <3>;
2364 #size-cells = <2>;
2365 bus-range = <0x00 0xff>;
2372 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2376 #interrupt-cells = <1>;
2377 interrupt-map-mask = <0 0 0 0>;
2378 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2380 clock-names = "pcie", "pcie_bus";
2381 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2382 resets = <&cpg 319>;
2383 iommu-map = <0 &ipmmu_hc 0 1>;
2384 iommu-map-mask = <0>;
2389 compatible = "renesas,pcie-r8a774a1",
2390 "renesas,pcie-rcar-gen3";
2392 #address-cells = <3>;
2393 #size-cells = <2>;
2394 bus-range = <0x00 0xff>;
2401 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2405 #interrupt-cells = <1>;
2406 interrupt-map-mask = <0 0 0 0>;
2407 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2409 clock-names = "pcie", "pcie_bus";
2410 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2411 resets = <&cpg 318>;
2412 iommu-map = <0 &ipmmu_hc 1 1>;
2413 iommu-map-mask = <0>;
2417 pciec0_ep: pcie-ep@fe000000 {
2418 compatible = "renesas,r8a774a1-pcie-ep",
2419 "renesas,rcar-gen3-pcie-ep";
2425 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
2430 clock-names = "pcie";
2431 resets = <&cpg 319>;
2432 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2436 pciec1_ep: pcie-ep@ee800000 {
2437 compatible = "renesas,r8a774a1-pcie-ep",
2438 "renesas,rcar-gen3-pcie-ep";
2444 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
2449 clock-names = "pcie";
2450 resets = <&cpg 318>;
2451 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2460 power-domains = <&sysc R8A774A1_PD_A3VC>;
2461 resets = <&cpg 119>;
2469 power-domains = <&sysc R8A774A1_PD_A3VC>;
2470 resets = <&cpg 615>;
2478 power-domains = <&sysc R8A774A1_PD_A3VC>;
2479 resets = <&cpg 607>;
2487 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2488 resets = <&cpg 603>;
2496 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2497 resets = <&cpg 602>;
2505 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2506 resets = <&cpg 601>;
2514 power-domains = <&sysc R8A774A1_PD_A3VC>;
2515 resets = <&cpg 611>;
2524 power-domains = <&sysc R8A774A1_PD_A3VC>;
2525 resets = <&cpg 626>;
2535 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2536 resets = <&cpg 623>;
2546 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2547 resets = <&cpg 622>;
2557 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2558 resets = <&cpg 621>;
2568 power-domains = <&sysc R8A774A1_PD_A3VC>;
2569 resets = <&cpg 631>;
2575 compatible = "renesas,r8a774a1-csi2";
2579 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2580 resets = <&cpg 714>;
2584 #address-cells = <1>;
2585 #size-cells = <0>;
2592 #address-cells = <1>;
2593 #size-cells = <0>;
2599 remote-endpoint = <&vin0csi20>;
2603 remote-endpoint = <&vin1csi20>;
2607 remote-endpoint = <&vin2csi20>;
2611 remote-endpoint = <&vin3csi20>;
2615 remote-endpoint = <&vin4csi20>;
2619 remote-endpoint = <&vin5csi20>;
2623 remote-endpoint = <&vin6csi20>;
2627 remote-endpoint = <&vin7csi20>;
2634 compatible = "renesas,r8a774a1-csi2";
2638 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2639 resets = <&cpg 716>;
2643 #address-cells = <1>;
2644 #size-cells = <0>;
2651 #address-cells = <1>;
2652 #size-cells = <0>;
2658 remote-endpoint = <&vin0csi40>;
2662 remote-endpoint = <&vin1csi40>;
2666 remote-endpoint = <&vin2csi40>;
2670 remote-endpoint = <&vin3csi40>;
2674 remote-endpoint = <&vin4csi40>;
2678 remote-endpoint = <&vin5csi40>;
2682 remote-endpoint = <&vin6csi40>;
2686 remote-endpoint = <&vin7csi40>;
2694 compatible = "renesas,r8a774a1-hdmi",
2695 "renesas,rcar-gen3-hdmi";
2700 clock-names = "iahb", "isfr";
2701 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2702 resets = <&cpg 729>;
2706 #address-cells = <1>;
2707 #size-cells = <0>;
2711 remote-endpoint = <&du_out_hdmi0>;
2725 compatible = "renesas,du-r8a774a1";
2732 clock-names = "du.0", "du.1", "du.2";
2733 resets = <&cpg 724>, <&cpg 722>;
2734 reset-names = "du.0", "du.2";
2740 #address-cells = <1>;
2741 #size-cells = <0>;
2749 remote-endpoint = <&dw_hdmi0_in>;
2755 remote-endpoint = <&lvds0_in>;
2762 compatible = "renesas,r8a774a1-lvds";
2765 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2766 resets = <&cpg 727>;
2770 #address-cells = <1>;
2771 #size-cells = <0>;
2776 remote-endpoint = <&du_out_lvds0>;
2791 thermal-zones {
2792 sensor1_thermal: sensor1-thermal {
2793 polling-delay-passive = <250>;
2794 polling-delay = <1000>;
2795 thermal-sensors = <&tsc 0>;
2796 sustainable-power = <3874>;
2799 sensor1_crit: sensor1-crit {
2807 sensor2_thermal: sensor2-thermal {
2808 polling-delay-passive = <250>;
2809 polling-delay = <1000>;
2810 thermal-sensors = <&tsc 1>;
2811 sustainable-power = <3874>;
2814 sensor2_crit: sensor2-crit {
2822 sensor3_thermal: sensor3-thermal {
2823 polling-delay-passive = <250>;
2824 polling-delay = <1000>;
2825 thermal-sensors = <&tsc 2>;
2826 sustainable-power = <3874>;
2828 cooling-maps {
2831 cooling-device = <&a57_0 0 2>;
2836 cooling-device = <&a53_0 0 2>;
2841 target: trip-point1 {
2847 sensor3_crit: sensor3-crit {
2857 compatible = "arm,armv8-timer";
2858 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
2862 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
2865 /* External USB clocks - can be overridden by the board */
2867 compatible = "fixed-clock";
2868 #clock-cells = <0>;
2869 clock-frequency = <0>;
2873 compatible = "fixed-clock";
2874 #clock-cells = <0>;
2875 clock-frequency = <0>;