Lines Matching +full:reg +full:- +full:io +full:- +full:width

1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 	interrupt-parent = <&gic>;
14 	#address-cells = <1>;
15 	#size-cells = <1>;
17 	reserved-memory {
18 		#address-cells = <1>;
19 		#size-cells = <1>;
23 			reg = <0x2f000 0x1000>;
27 			reg = <0x1ffe000 0x4000>;
31 			reg = <0x10100000 0xf00000>;
32 			no-map;
37 		#address-cells = <1>;
38 		#size-cells = <0>;
42 			compatible = "arm,cortex-a55";
43 			reg = <0x0>;
44 			enable-method = "psci";
45 			next-level-cache = <&l2>;
50 			compatible = "arm,cortex-a55";
51 			reg = <0x100>;
52 			enable-method = "psci";
53 			next-level-cache = <&l3>;
58 			compatible = "arm,cortex-a55";
59 			reg = <0x200>;
60 			enable-method = "psci";
61 			next-level-cache = <&l3>;
66 			compatible = "arm,cortex-a55";
67 			reg = <0x300>;
68 			enable-method = "psci";
69 			next-level-cache = <&l3>;
74 			compatible = "arm,cortex-a55";
75 			reg = <0x400>;
76 			enable-method = "psci";
77 			next-level-cache = <&l3>;
82 			compatible = "arm,cortex-a55";
83 			reg = <0x500>;
84 			enable-method = "psci";
85 			next-level-cache = <&l3>;
88 		l2: l2-cache {
90 			next-level-cache = <&l3>;
91 			cache-level = <2>;
92 			cache-unified;
96 		l3: l3-cache {
98 			cache-level = <3>;
99 			cache-unified;
104 		compatible = "arm,armv8-timer";
112 		compatible = "arm,cortex-a55-pmu";
114 		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>,
119 		compatible = "arm,psci-1.0";
124 		compatible = "fixed-clock";
125 		clock-frequency = <27000000>;
126 		clock-output-names = "osc27M";
127 		#clock-cells = <0>;
131 		compatible = "simple-bus";
132 		#address-cells = <1>;
133 		#size-cells = <1>;
138 			compatible = "simple-bus";
139 			reg = <0x98000000 0x200000>;
140 			#address-cells = <1>;
141 			#size-cells = <1>;
145 				compatible = "syscon", "simple-mfd";
146 				reg = <0x0 0x1000>;
147 				reg-io-width = <4>;
148 				#address-cells = <1>;
149 				#size-cells = <1>;
154 				compatible = "syscon", "simple-mfd";
155 				reg = <0x7000 0x1000>;
156 				reg-io-width = <4>;
157 				#address-cells = <1>;
158 				#size-cells = <1>;
163 				compatible = "syscon", "simple-mfd";
164 				reg = <0x1a000 0x1000>;
165 				reg-io-width = <4>;
166 				#address-cells = <1>;
167 				#size-cells = <1>;
172 				compatible = "syscon", "simple-mfd";
173 				reg = <0x1b000 0x1000>;
174 				reg-io-width = <4>;
175 				#address-cells = <1>;
176 				#size-cells = <1>;
181 				compatible = "syscon", "simple-mfd";
182 				reg = <0x1d000 0x1000>;
183 				reg-io-width = <4>;
184 				#address-cells = <1>;
185 				#size-cells = <1>;
190 		gic: interrupt-controller@ff100000 {
191 			compatible = "arm,gic-v3";
192 			reg = <0xff100000 0x10000>,
195 			interrupt-controller;
196 			#interrupt-cells = <3>;
203 		compatible = "snps,dw-apb-uart";
204 		reg = <0x800 0x400>;
205 		reg-shift = <2>;
206 		reg-io-width = <4>;
208 		clock-frequency = <27000000>;
215 		compatible = "snps,dw-apb-uart";
216 		reg = <0x200 0x400>;
217 		reg-shift = <2>;
218 		reg-io-width = <4>;
220 		clock-frequency = <432000000>;
225 		compatible = "snps,dw-apb-uart";
226 		reg = <0x400 0x400>;
227 		reg-shift = <2>;
228 		reg-io-width = <4>;
230 		clock-frequency = <432000000>;